JPS6031266A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6031266A JPS6031266A JP58140832A JP14083283A JPS6031266A JP S6031266 A JPS6031266 A JP S6031266A JP 58140832 A JP58140832 A JP 58140832A JP 14083283 A JP14083283 A JP 14083283A JP S6031266 A JPS6031266 A JP S6031266A
- Authority
- JP
- Japan
- Prior art keywords
- region
- resistor
- contact
- protection
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000000295 complement effect Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置、特にＭＯ８集積回路装置等に内蔵
される静電破壊防止保護回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a protection circuit for preventing electrostatic damage built into a semiconductor device, particularly an MO8 integrated circuit device.
一般に、ＭＯ８集積回路は静電気で破壊されやすいｆｃ
ｈｌ）、Ｍ ＯＳ ）ランジスタのゲート保護の目的で
入力端子とＭＯＳ）ランジスタのゲートとの間に入力保
護回路が必ず内蔵されている。In general, MO8 integrated circuits are easily destroyed by static electricity.
For the purpose of protecting the gates of the MOS) transistors, an input protection circuit is always built in between the input terminal and the gate of the MOS) transistors.
第１図は従来の入力保護回路付き相補型ＭＯＳインバー
タの一例を示す等価回路である。相補型の二つのＭＯＳ
）ランジスタＱｌ、Ｑ２のゲートと入力端子Ｔとの間に
抵抗Ｒが接続され、入力端子Ｔと正および負の電源ＶＤ
Ｐ ｖｓｓとの間に各々入力サージ防止用の保護ダイオ
ードＤ１．Ｄｚが接続されている。また抵抗Ｒは拡散抵
抗を用いるため等測的にダイオードＤ３が電源ＶｌｌＤ
間に接続される。ところが、各々のダイオードＤ１〜Ｄ
３には電源間にシリーズ抵抗としてＲ１，Ｒｚ、Ｒ，＋
が寄生抵抗として必然的に入ることになり、特に従来パ
ターン設計上Ｒ＋ 、Ｒ２、Ｒｓの寄性抵抗に対する配
慮が欠けていた。このため、保護ダイオードＤ３のスウ
ィッチングスピードが遅くなり、ゲート保咥の機能が低
下してゲート破壊を発生させていた。FIG. 1 is an equivalent circuit showing an example of a conventional complementary MOS inverter with an input protection circuit. Two complementary MOSs
) A resistor R is connected between the gates of transistors Ql and Q2 and an input terminal T, and a resistor R is connected between the input terminal T and the positive and negative power supplies VD.
A protective diode D1.P for input surge prevention is connected between D1 and Pvss. Dz is connected. Also, since the resistor R uses a diffused resistor, the diode D3 is isometrically connected to the power supply VllD.
connected between. However, each of the diodes D1 to D
3 has R1, Rz, R, + as a series resistor between the power supplies.
are inevitably introduced as parasitic resistances, and in particular, conventional pattern design has lacked consideration for the parasitic resistances of R+, R2, and Rs. As a result, the switching speed of the protection diode D3 is slowed down, and the gate protection function is degraded, resulting in gate breakdown.
本発明は、特に寄性抵抗Ｒ３のシリーズ抵抗を低下させ
ることによシゲート破壊強度を向上させることを目的と
するものである。The present invention particularly aims at improving the silicate breakdown strength by lowering the series resistance of the parasitic resistor R3.
本発明は、保護用抵抗領域に沿って電源用コンタクトを
設けたことを特徴とする。The present invention is characterized in that a power supply contact is provided along the protective resistance region.
第２図は、第１図で示した入力保護回路の従来のパター
ン形状例を示すものである。保護ダイオードＤ＋、Ｄ３
および抵抗■はそれぞれＮ型半導体基板２０に形成され
たＰ型領域４，７ および６として構成される。領域６
は所定の抵抗長を得るためにだ行している。保距ダイオ
ードＤ２はＰ−ウェル１２に形成されたＮ型領域１３で
構成される。FIG. 2 shows an example of a conventional pattern shape of the input protection circuit shown in FIG. Protection diode D+, D3
and resistor (1) are configured as P-type regions 4, 7, and 6 formed in N-type semiconductor substrate 20, respectively. Area 6
is proceeding in order to obtain a predetermined resistance length. The distance keeping diode D2 is composed of an N-type region 13 formed in a P-well 12.
基板２０にはコンタクト１０を介してＶＤＤ配線２よシ
ＶＤＤ電位が与えられ、Ｐ−ウェル１２にはコンタクト
１１を通してＶ８８配＋！Ｉ１１よシＶｓｓ雷１位が力
見られている。入力電極（図示せず）に接続された配線
３はコンタクト５で領域４およびコンタクト１４で領域
１３にそれぞれ接続される。コンタクト９を介して取り
出された配線８はＱｌ、Ｑ２のゲートに接続される。こ
のように基板２０に与える電源はＶｎｎ市源配＃１２下
のみより寿えられていたため、保時抵抗Ｒおよび保静ダ
イオードＤ３を形成するＰ型領域６，７を電源コンタク
ト１゜との間の等価シリーズ抵抗１１３が大きい。この
結果ゲート保砕の機能が低下する。つまシミ源コンタク
ト１０の配置によって、ゲート破壊強度が大きく依存す
ることを意味する。The VDD potential is applied to the substrate 20 via the contact 10 through the VDD wiring 2, and the V88 wiring is applied to the P-well 12 through the contact 11. I11 Yoshi Vss Rai 1st place is seen as powerful. Wiring 3 connected to an input electrode (not shown) is connected to region 4 through contact 5 and region 13 through contact 14, respectively. The wiring 8 taken out through the contact 9 is connected to the gates of Ql and Q2. In this way, since the power supplied to the substrate 20 was maintained only from below the Vnn connection #12, the P-type regions 6 and 7 forming the time-keeping resistor R and the keeping diode D3 were connected to the power supply contact 1°. The equivalent series resistance 113 of is large. As a result, the gate crushing function deteriorates. This means that the gate breakdown strength largely depends on the arrangement of the tab stain source contacts 10.
本発明は前記欠点を改善するために拡散抵抗領域に沿っ
て電源コンタクトを設け、軍、源に対するシリーズ抵抗
を小さくすることによりゲート破壊強度を改善したもの
である。これによって保護ダイオードのスウィッチング
スピードが速くなり、かつ抵抗Ｒ，Ｒｓによる抵抗分割
による電位が低下する。The present invention improves the gate breakdown strength by providing a power supply contact along the diffused resistance region and reducing the series resistance to the source. This increases the switching speed of the protection diode and reduces the potential due to resistance division by the resistors R and Rs.
第３図に本発明の一実施例を示す。すなわち、電源コン
タクト１１０が抵抗領域６およびダイオードＤ３領域７
０周辺に配ｖ１′されている。ただし、保護ダイオード
４の周辺には電源コンタク） １１０を配置してい々い
。これは入力サージにょシ保酔ダイオードＤ１が破壊す
ることを防止するためである。FIG. 3 shows an embodiment of the present invention. That is, the power contact 110 is connected to the resistance region 6 and the diode D3 region 7.
v1' is placed around 0. However, a power supply contact (110) may be placed around the protection diode 4. This is to prevent the input surge from destroying the locking diode D1.
第３図は相補型ＭＯ８の保時回路のパターン例を示した
が、ＰチャンネルＭＯ８，ＮチャンネルＭＯ８の場合で
も入力保設抵抗として拡散抵抗を用いるれば一般的にそ
の抵抗の形状に無関係に周辺に電源コンタクトを配置し
対電源のシリーズ抵抗を小さくすることにょシ同等の効
果が得られる。Figure 3 shows an example of the pattern of a complementary MO8 timekeeping circuit, but even in the case of P-channel MO8 and N-channel MO8, if a diffused resistor is used as the input holding resistor, it is generally independent of the shape of the resistor. The same effect can be obtained by arranging power contacts around the periphery and reducing the series resistance to the power supply.
第１図は入力保護回路付相補型ＭＯＳインバータの等価
回路である。第２図は第１図に示す保護回路をＮ型基板
に形成した従来のパターン形状である。第３図は本発明
の一実施例を示すパターン形状である。
１・・・・・・Ｖｓｓ電源配線、２・・・・・・Ｖｌ）
ｌ）電源配線、３・・・・・・入力端子からのアルミ配
線、４・・・・・・Ｐ型保−ダイオードＤ１．６・・・
・・・Ｐ型拡散を用いた抵抗領域、７・・・・・・Ｐ型
保護ダイオードＤ３．１２・・・・・・Ｐウェル領域、
１３・・・・・・Ｎ型保裏ダイオードＤ２．８・・・・
・・ＭＯＳゲート入力へのアルミ配線、２０・・・・・
・Ｎ甲基板、４，９，１０，１１，１４，１１．０・旧
・・コンタクト穴。FIG. 1 is an equivalent circuit of a complementary MOS inverter with an input protection circuit. FIG. 2 shows a conventional pattern shape in which the protection circuit shown in FIG. 1 is formed on an N-type substrate. FIG. 3 shows a pattern shape showing one embodiment of the present invention. 1...Vss power supply wiring, 2...Vl)
l) Power supply wiring, 3...Aluminum wiring from input terminal, 4...P-type protection diode D1.6...
...Resistance region using P-type diffusion, 7...P-type protection diode D3.12...P well region,
13...N-type protection diode D2.8...
...Aluminum wiring to MOS gate input, 20...
・N A board, 4, 9, 10, 11, 14, 11.0・Old・・Contact hole.
Claims (1)
を有する半導体装置において、前記保護用抵抗領域に沿
って前記−導電型半導体へのコンタクト穴を設けたこと
を特徴とする半導体装置。A semiconductor device having a protective resistance region of an opposite layer conductivity type formed in a semiconductor of one conductivity type, characterized in that a contact hole to the semiconductor of the -conductivity type is provided along the protection resistance region. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58140832A JPS6031266A (en) | 1983-08-01 | 1983-08-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58140832A JPS6031266A (en) | 1983-08-01 | 1983-08-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6031266A true JPS6031266A (en) | 1985-02-18 |
Family
ID=15277749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58140832A Pending JPS6031266A (en) | 1983-08-01 | 1983-08-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6031266A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164258A (en) * | 1986-12-25 | 1988-07-07 | Fujitsu Ltd | Input/output circuit characterized by high breakdown strength |
| JPS6455873A (en) * | 1987-08-27 | 1989-03-02 | Matsushita Electronics Corp | Semiconductor integrated circuit having surge protecting function |
| US4976553A (en) * | 1987-12-09 | 1990-12-11 | Max Co., Ltd. | Very small displacement enlargement mechanism and printing head using the same |
-
1983
- 1983-08-01 JP JP58140832A patent/JPS6031266A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164258A (en) * | 1986-12-25 | 1988-07-07 | Fujitsu Ltd | Input/output circuit characterized by high breakdown strength |
| JPS6455873A (en) * | 1987-08-27 | 1989-03-02 | Matsushita Electronics Corp | Semiconductor integrated circuit having surge protecting function |
| US4976553A (en) * | 1987-12-09 | 1990-12-11 | Max Co., Ltd. | Very small displacement enlargement mechanism and printing head using the same |
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