JP2005217314A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a small area of a power supply interconnection arranged in a circumference of a macro cell, and suitable for an automatic interconnection easily connected to an upper layer power supply interconnection and the macro cell. <P>SOLUTION: Ring power supply interconnections 101, 102 for the macro cell are arranged in the circumference of the macro cell 100. The upper layer power supply interconnections 111-114 are arranged at the position passing through over the macro cell 100 in the interconnection layer more superordinate than the macro cell 100 and the power supply interconnections 101, 102 for the macro cell. The power supply interconnections 101, 102 for the macro cell and the upper layer power supply interconnections 111-114 are mutually connected at their crossing point. Widths of the power supply interconnections 101, 102 for the macro cell are set to that of the interconnection required for supplying the power supply current to the macro cell 100 with the use of only the interconnection. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that includes a macro cell and has a multilayer wiring structure.

  In recent years, semiconductor integrated circuits called system-on-chip, in which system functions are integrated on a single semiconductor chip, have been actively developed. In order to design such a semiconductor integrated circuit, a plurality of macrocells in which a plurality of elements (for example, logic gates, memory elements, etc.) are arranged in a certain region are prepared, and these macrocells are combined to form the entire system. A method for realizing the function is used. In a semiconductor integrated circuit including a macro cell, power is supplied to the macro cell from an external terminal or an internal power circuit. In recent semiconductor integrated circuits, the macro cell occupies a large area in the chip. For this reason, in order to supply the power current evenly to the macro cell, the macro cell power wiring having a wiring width capable of flowing the current consumed by the macro cell is arranged around the macro cell. A method of supplying a power supply current from a plurality of directions to the macro cell is used.

  In the conventional semiconductor integrated circuit, when wiring the macro cell power supply wiring, different wiring layers are used in the horizontal direction and the vertical direction so as to be easily connected to the power supply wiring extending in the horizontal direction and the vertical direction of the macro cell ( For example, refer nonpatent literature 1). In recent semiconductor integrated circuits, as the operation speed is improved, power supply wiring is arranged in a grid pattern in a wiring layer higher than the wiring layer used in the macro cell, and the power supply wiring arranged in the grid pattern is changed to the macro cell. On the other hand, a method of supplying power is also adopted.

  With reference to FIGS. 9 and 10, a power supply method for a macro cell in a conventional semiconductor integrated circuit will be described. In FIG. 9, a macro cell 600 is a macro cell including a plurality of logic gates and configured by a wiring layer of the fourth layer or lower. Around the macro cell 600, the following four types of power supply wirings 601 to 604 are provided. The macro cell horizontal VDD power supply wiring 601 is a power supply wiring extending in the horizontal direction to supply the power supply level VDD. The macro cell horizontal VSS power supply wiring 602 is a power supply wiring extending in the horizontal direction in order to supply the ground level VSS. The macro cell vertical VDD power supply wiring 603 is a power supply wiring extending in the vertical direction in order to supply the power supply level VDD. The macro cell vertical VSS power supply wiring 604 is a power supply wiring extending in the vertical direction in order to supply the ground level VSS. The macro cell horizontal VDD power wiring 601 and the macro cell horizontal VSS power wiring 602 are formed in the fourth wiring layer, and the macro cell vertical VDD power wiring 603 and the macro cell vertical VSS power wiring 604 are formed in the third layer. It is formed in the wiring layer.

  The macro cell horizontal VDD power supply wiring 601 and the macro cell vertical VDD power supply wiring 603 are connected to each other by a contact (not shown) arranged at a location where they intersect. Further, the macro cell horizontal VSS power supply wiring 602 and the macro cell vertical VSS power supply wiring 604 are connected to each other by a contact (not shown) arranged at a location where they intersect. Further, the macro cell 600 and the power supply wirings 601 to 604 are connected by a power supply wiring (not shown) extending in the horizontal direction or the vertical direction. The widths of the power supply lines 601 to 604 are set to values that can supply the current consumed by the macro cell 600 from the power supply lines 601 to 604.

  An outer periphery (indicated by a one-dot chain line) of an area including the macro cell 600 and the power supply wirings 601 to 604 is referred to as a macro cell layout frame 620. The macro cell layout frame 620 is used when determining the arrangement position of the macro cell 600 in the semiconductor integrated circuit.

  Four further types of power supply wirings 611 to 614 are provided outside the macro cell layout frame 620. The horizontal VDD power supply wiring 611 is a power supply wiring extending in the horizontal direction in order to supply the power supply level VDD. The horizontal VSS power supply wiring 612 is a power supply wiring extending in the horizontal direction in order to supply the ground level VSS. The vertical VDD power supply wiring 613 is a power supply wiring extending in the vertical direction in order to supply the power supply level VDD. The vertical VSS power supply wiring 614 is a power supply wiring extending in the vertical direction in order to supply the ground level VSS. The horizontal VDD power wiring 611 and the horizontal VSS power wiring 612 are formed in the fourth wiring layer, and the vertical VDD power wiring 613 and the vertical VSS power wiring 614 are formed in the third wiring layer.

  In the third and fourth wiring layers, a VDD power connection terminal 621 is provided at the end of the macro cell horizontal VDD power wiring 601 and the macro cell vertical VDD power wiring 603. The macro cell horizontal VDD power wiring 601 is connected to a horizontal VDD power wiring 611 disposed outside the macro cell 600 via a VDD power connection terminal 621. The macro cell vertical VDD power supply wiring 603 is connected to a vertical VDD power supply wiring 613 disposed outside the macro cell 600 through a VDD power supply connection terminal 621.

  In the fourth wiring layer, a VSS power connection terminal 622 is provided at the end of the macro cell horizontal VSS power wiring 602. The macro cell horizontal VSS power wiring 602 is connected to a horizontal VSS power wiring 612 arranged outside the macro cell 600 via a VSS power connection terminal 622. In the third wiring layer, a VSS power connection terminal 623 is provided at the end of the macro cell vertical VSS power wiring 604. The macro cell vertical VSS power wiring 604 is connected to a vertical VSS power wiring 614 disposed outside the macro cell 600 via a VSS power connection terminal 623.

  FIG. 10 is a diagram showing a connection example of the macro cell and the upper layer power supply wiring in the semiconductor integrated circuit shown in FIG. In FIG. 10, a horizontal VDD power supply wiring 711, a horizontal VSS power supply wiring 712, a vertical VDD power supply wiring 713, and a vertical VSS power supply wiring 714 (hereinafter collectively referred to as upper layer power supply wiring) supply power to the entire semiconductor integrated circuit. This is a power supply wiring provided for this purpose. The horizontal VDD power supply wiring 711 is a power supply wiring extending in the horizontal direction in order to supply the power supply level VDD. The horizontal VSS power supply wiring 712 is a power supply wiring extending in the horizontal direction in order to supply the ground level VSS. The vertical VDD power supply wiring 713 is a power supply wiring extending in the vertical direction in order to supply the power supply level VDD. The vertical VSS power supply wiring 714 is a power supply wiring extending in the vertical direction to supply the ground level VSS.

  The upper layer power supply wirings 711 to 714 are arranged in a grid pattern on a wiring layer higher than the wiring layers used in the macro cell 600 and the power supply wirings 601 to 604 by using an automatic wiring tool which is a kind of EDA (Electronic Design Automation) tool. Be placed. In the example shown in FIG. 10, the horizontal VDD power supply wiring 711 and the horizontal VSS power supply wiring 712 are formed in the fifth wiring layer, and the vertical VDD power supply wiring 713 and the vertical VSS power supply wiring 714 are the sixth layer wiring. Formed in layers. As a result, the upper layer power supply wirings 711 to 714 pass through the upper part of the macro cell 600.

In order to supply a power supply current from the upper layer power supply wirings 711 to 714 to the macro cell 600, the VDD power supply connection terminal 621 has a horizontal VDD power supply wiring 611, a vertical VDD power supply wiring 613, and contacts (indicated by white squares in FIG. 10). Or the like to the horizontal VDD power supply wiring 711 or the vertical VDD power supply wiring 713. Similarly, the VSS power connection terminal 622 is connected to the horizontal VSS power wiring 712 or the vertical VSS power wiring 714 via the horizontal VSS power wiring 612, the vertical VSS power wiring 614, contacts, and the like. The same applies to the VSS power connection terminal 623.
2002 STARC Donation Lecture, Waseda University SoC Design Technology, “System LSI Design LSI Design Lecture Materials”, Chapter 6, Layout Design 2, 34

  However, the conventional semiconductor integrated circuit has the following problems. First, in a conventional semiconductor integrated circuit, a macro cell power supply wiring having a wiring width corresponding to a current consumed in the macro cell is arranged around the macro cell. For this reason, even if the macro cell has a small area, for example, when the output signal has a large wiring load and it is necessary to drive the output signal at a high speed, it is necessary to supply a large current to the macro cell. Therefore, even if the area of the macro cell itself is small, the width of the macro cell power supply wiring is increased, and the macro cell layout area when the macro cell power supply wiring is included is increased. In particular, in recent semiconductor integrated circuits, interwiring capacitance and wiring resistance have increased with the miniaturization of wiring, and the operating frequency has increased. For this reason, in order to correctly supply the power source current to the macro cell, it is necessary to increase the width of the macro cell power source wiring.

  Further, in the layout processing of a semiconductor integrated circuit, processing for rotating the macro cell by 90 degrees is also performed. However, in the conventional semiconductor integrated circuit, the macro cell power supply wiring extending in the horizontal direction and the macro cell power supply extending in the vertical direction are used. The wiring is formed in a different wiring layer (for example, the former is in the fourth wiring layer and the latter is in the third wiring layer). For this reason, the power wiring ends of both the power supply level VDD and the ground level VSS are arranged on each side of the macro cell, and when a certain macro cell is rotated 90 degrees and placed near another macro cell, the same wiring layer The power supply wirings having different potentials face each other between the two macro cells. Therefore, it is necessary to provide a certain space between adjacent macro cells, and the area of the semiconductor integrated circuit increases.

  Further, since the macro cell power supply wiring extending in the horizontal direction and the macro cell power supply wiring extending in the vertical direction are formed in different wiring layers, one of the contacts is provided when the contact is provided between the upper power supply wiring and the macro cell. For the macro cell power wiring (for example, the macro cell power wiring extending in the vertical direction formed in the third wiring layer), the other macro cell power wiring (for example, the horizontal wiring formed in the fourth wiring layer). It is necessary to stack a larger number of contacts than the macro cell power supply wiring extending in the direction. In this case, in the former macro cell power supply wiring, the power contact resistance increases more than necessary.

  Furthermore, in the conventional semiconductor integrated circuit, since the power connection terminal is locally provided in the macro cell power wiring, when connecting the upper layer power wiring and the power connection terminal provided in the macro cell, both of them are connected. Arrangement position may not match. In this case, it is necessary to provide a space for arranging power supply wiring (for example, power supply wiring 611 to 614 shown in FIG. 10) for connecting the upper layer power supply wiring and the power supply connection terminal around the macro cell. The area of the circuit increases.

  Further, in the conventional semiconductor integrated circuit, since the power connection terminal is locally provided in the macro cell power wiring, in order to provide the contact connected to the upper layer power wiring in the upper part of the macro cell, in the semiconductor integrated circuit It is necessary to add a power connection terminal inside the macro cell according to the arrangement position of the macro cell, and to provide a space for connecting a power source inside the macro cell. For this reason, it is necessary to modify the existing macro cell, and the design man-hour of the semiconductor integrated circuit increases.

  When the macro cell is a memory macro cell, a contact for connecting to the upper layer power supply wiring cannot be provided inside the memory cell array occupying most of the macro cell. Further, since the memory macrocells are laid out at a high density, it is difficult to provide contacts for connecting to the upper layer power supply wiring in other circuit portions included in the memory macrocells.

  Therefore, an object of the present invention is to provide a semiconductor integrated circuit suitable for automatic wiring, in which the area of the power supply wiring arranged around the macrocell is small and the connection between the upper power supply wiring and the macrocell is easy.

  A semiconductor integrated circuit according to the present invention has a macro cell configured using a wiring layer of a predetermined size or less, and at least a pair of opposing portions arranged at positions sandwiching the macro cell, and supplies a macro cell power supply current to the macro cell. And an upper layer power supply wiring arranged at a position passing through the upper part of the macrocell in a wiring layer higher than the wiring layer used in the macrocell and the macrocell power supply wiring. The macro cell power supply wiring and the upper layer power supply wiring are connected to each other at the intersection of the opposing portion of the macro cell power supply wiring and the upper layer power supply wiring. The width of the macro cell power supply wiring is the same as that of the macro cell. The wiring width is set to be narrower than that required for supplying the power supply current.

  In this case, the macro cell power supply wiring may be formed in a single wiring layer, more preferably in the same wiring layer as the uppermost wiring layer used in the macro cell. Further, the upper layer power supply wiring may be formed in a wiring layer having a sheet resistance lower than that of the wiring layer used in the macro cell. Further, the upper layer power supply wires controlled to the same potential may be connected to each other at a crossing point in the upper part of the macro cell.

  Further, when the macro cell has a rectangular shape having first and second sides perpendicular to each other, the macro cell power supply wiring is arranged in parallel with the first side. You may have a power supply wiring as an opposing part. In this case, the macro cell power supply wiring may have third and fourth power supply wirings arranged in parallel to the second side as further opposing portions. More preferably, the macro cell power supply wiring may be ring-shaped wiring that includes the first to fourth power supply wirings and surrounds the macro cell.

  Alternatively, the opposing portion is provided with a power connection terminal having a length equal to or greater than the length of the first side, and the power supply wiring arranged outside the macro cell is connected to the power connection terminal. Also good. Alternatively, a power connection terminal is provided in the opposite portion, and the upper layer power supply wiring extending in the direction of the first side is not connected to the power connection terminal and extends in the direction of the second side. Upper layer power supply wiring may be connected.

  Further, the semiconductor integrated circuit may include a plurality of macro cells and a macro cell power wiring for each macro cell, and a part of the macro cell power wiring may be disposed at the same position between adjacent macro cells. . In the case where the semiconductor integrated circuit includes a plurality of macro cell power supply wirings arranged at different distances from each macro cell for each macro cell, the macro integrated circuit is arranged at a position farthest from each macro cell between adjacent macro cells. A part of the macro cell power supply wiring (or other macro cell power supply wiring) may be arranged at the same position.

  In addition, the semiconductor integrated circuit has a shield disposed at a position covering a part of the macro cell in a wiring layer higher than the wiring layer used in the macro cell and lower than the wiring layer used in the upper power supply wiring. Power supply wiring may be further provided. The upper layer power supply wiring and the shield wiring are connected to each other at a crossing point in the upper part of the macro cell. More preferably, the input / output terminals of the macro cell may be formed in the same wiring layer as the uppermost wiring layer used in the macro cell, and more preferably, the macro cell is a memory macro cell including a plurality of memory elements. May be.

  According to the semiconductor integrated circuit of the present invention, the upper layer power supply wiring fulfills a part of the power supply function for the macrocell by connecting the macrocell power supply wiring and the upper layer power supply wiring to each other at the intersection. Therefore, even if the width of the macro cell power supply wiring is made narrower than before, the power can be correctly supplied to the macro cell. Therefore, the width of the macro cell power supply wiring can be made narrower than before, the macro cell layout area can be reduced when the macro cell power supply wiring is included, and a reduction in the area and cost of the semiconductor integrated circuit can be achieved. .

  In addition, by forming the macro cell power supply wiring in a single wiring layer, especially in the same wiring layer as the uppermost wiring layer used in the macro cell, the number of stacked stages of contacts connecting the upper layer power supply wiring and the macro cell power supply wiring Can be reduced. Thereby, the resistance of the power supply wiring connected to the macro cell can be reduced, and the power supply voltage drop can be suppressed. Further, the power supply voltage drop in the upper layer power supply wiring can be suppressed by forming the upper layer power supply wiring in a wiring layer having a sheet resistance lower than that of the wiring layer used in the macro cell. Further, the upper layer power supply wiring controlled to the same potential is connected to each other at the intersecting portion in the upper part of the macro cell, whereby the potential of the upper layer power supply wiring can be stabilized.

  In addition, when the macro cell power supply wiring has the first and second power supply wirings arranged in parallel to the first side of the macro cell as opposed portions, the third and the third power supply wirings arranged in parallel to the second side of the macro cell. In the case where the fourth power supply wiring is provided as a further opposing portion, and in the case of a ring-shaped wiring surrounding the macrocell, the width of the macrocell power supply wiring can be reduced according to each configuration.

  Also, by providing the power connection terminal, when the upper layer power supply wiring is arranged on the top of the macro cell using the automatic wiring tool, a contact for supplying a power supply current from the upper layer power supply wiring to the macro cell is provided. Can be automatically provided in the interior. Therefore, there is no need to draw extra power supply wiring around the macro cell, and even when layout processing is performed using an automatic wiring tool, the layout area does not increase, so that the semiconductor integrated circuit can be reduced in area and cost. be able to. In particular, by setting the length of the power connection terminal to be equal to or longer than the length of the first side of the macro cell, a large number of contacts can be provided on the macro cell power wiring with a high degree of freedom. In addition, the power supply connection terminal is connected to the power supply connection by connecting the upper layer power supply line extending in the direction of the second side of the macro cell without connecting the upper layer power supply line extending in the direction of the first side of the macro cell. Even when two upper-layer power supply wirings controlled at different potentials from the terminal for use intersect at one place, the two contacts are not provided overlapping each other. For this reason, automatic wiring can be performed so that the two power supply wirings controlled to different potentials are not short-circuited, so that the step of correcting the layout result after automatic wiring can be omitted.

  Also, when the semiconductor integrated circuit includes a plurality of macro cells, by arranging a part of the macro cell power supply wiring at the same position between the macro cells arranged adjacent to each other, between the macro cells arranged adjacent to each other. By sharing a part of the macro cell power supply wiring, it is possible to reduce the area and cost of the semiconductor integrated circuit.

  In addition, since the shield power supply wiring is provided, the macro cell layout is formed above the macro cell even when it is difficult to provide a contact inside the macro cell layout frame due to the high density layout as in the memory macro cell. Contacts can be provided inside the frame. Accordingly, since it is not necessary to modify the layout data of the macrocell in order to make a space for arranging the contacts, it is possible to reduce the area and cost of the semiconductor integrated circuit and reduce the number of layout steps. . In addition, by forming the input / output terminals of the macro cell in the same wiring layer as the uppermost wiring layer used in the macro cell, the signal wiring formed in the wiring layer higher than the wiring layer used in the macro cell and the macro cell. Can be directly connected using a contact, so that a reduction in area and cost of the semiconductor integrated circuit can be achieved.

  Hereinafter, semiconductor integrated circuits according to first to fifth embodiments of the present invention will be described with reference to FIGS. 1 to 8 all show the layout results of the semiconductor integrated circuit including the macro cell. Among the constituent elements of each embodiment, the same constituent elements as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted. Hereinafter, the horizontal direction and the vertical direction in each drawing are simply referred to as the horizontal direction and the vertical direction, respectively.

(First embodiment)
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to the first embodiment of the present invention. The semiconductor integrated circuit shown in FIG. 1 includes a macro cell 100, two macro cell power lines (macro cell VDD power line 101 and macro cell VSS power line 102), and four types of upper layer power lines (horizontal VDD power line 111, Horizontal VSS power wiring 112, vertical VDD power wiring 113, and vertical VSS power wiring 114).

  The macro cell 100 is a macro cell (also referred to as a functional block) that includes a plurality of logic gates and is configured using a fourth or lower wiring layer. Around the macro cell 100, in order to supply a power source current to the macro cell 100, ring-shaped macro cell power wirings 101 and 102 are arranged. The macro cell VDD power wiring 101 is a power wiring for supplying the power level VDD to the macro cell 100, and the macro cell VSS power wiring 102 is a power wiring for supplying the ground level VSS to the macro cell 100. The macro cell 100 and the macro cell VDD power line 101 and the macro cell 100 and the macro cell VSS power line 102 are connected by power lines (not shown) extending in the horizontal direction or the vertical direction, respectively.

  The macro cell power supply wirings 101 and 102 are formed in a single wiring layer. In the present embodiment, the macro cell power supply wirings 101 and 102 are both formed in the same wiring layer as the uppermost wiring layer used in the macro cell 100, that is, in the fourth wiring layer. In FIG. 1, the macro cell VDD power supply wiring 101 is arranged outside the macro cell VSS power supply wiring 102, but they may be arranged at opposite positions.

  An outer periphery (indicated by a one-dot chain line) of an area including the macro cell 100 and the macro cell power supply wires 101 and 102 is referred to as a macro cell layout frame 130. The macro cell layout frame 130 is used when determining the arrangement position of the macro cell 100 in the semiconductor integrated circuit.

  The upper layer power supply lines 111 to 114 are power supply lines for supplying a power supply current to various circuit blocks (including the macro cell 100) included in the semiconductor integrated circuit. The upper layer power supply wires 111 to 114 are typically arranged at regular intervals in a lattice pattern using an automatic wiring tool. The horizontal VDD power wiring 111 is a power wiring extending in the horizontal direction in order to supply the power level VDD. The horizontal VSS power supply wiring 112 is a power supply wiring extending in the horizontal direction in order to supply the ground level VSS. The vertical VDD power supply wiring 113 is a power supply wiring extending in the vertical direction in order to supply the power supply level VDD. The vertical VSS power supply wiring 114 is a power supply wiring extending in the vertical direction in order to supply the ground level VSS.

  Upper layer power supply wirings 111 to 114 are arranged at positions that pass above the macrocell 100 in a wiring layer higher than the wiring layer used in the macrocell 100 and the macrocell power supply wirings 101 and 102. Further, the upper layer power supply wires 111 to 114 are formed in a wiring layer having a sheet resistance lower than that of the wiring layer used in the macro cell 100. In this embodiment, the horizontal VDD power wiring 111 and the horizontal VSS power wiring 112 are arranged in the fifth wiring layer, and the vertical VDD power wiring 113 and the vertical VSS power wiring 114 are arranged in the sixth wiring layer. The In order to connect two power supply lines, the horizontal VDD power supply line 111 and the vertical VDD power supply line 113 intersect with each other, and the horizontal VSS power supply line 112 and the vertical VSS power supply line 114 intersect with each other in order to connect two power supply lines (see FIG. (Not shown) may be provided.

  The macro cell 100 has a rectangular shape having a horizontal side and a vertical side. The macro cell VDD power supply wiring 101 includes two power supply wirings extending in the horizontal direction (hereinafter referred to as first and second power supply wirings) and two power supply wirings extending in the vertical direction (hereinafter referred to as third and third power supply wirings). 4 power supply wiring). Hereinafter, a pair of power supply wirings arranged at positions sandwiching the macro cell 100 on the substrate plane of the semiconductor integrated circuit will be referred to as opposing portions. The first and second power supply wirings constitute a first opposing part, and the third and fourth power supply wirings constitute a second opposing part. In other words, the macro cell VDD power supply wiring 101 has the first and second power supply wirings as opposing portions, and has the third and fourth power supply wirings as further opposing portions. The same applies to the macro cell VSS power supply wiring 102.

  On the macro cell VDD power wiring 101, a VDD power connection terminal 131 for connecting to a VDD power wiring arranged outside the macro cell 100 is provided. Further, a VSS power connection terminal 132 for connection to a VSS power wiring arranged outside the macro cell 100 is provided on the macro cell VSS power wiring 102. The horizontal length of the VDD power connection terminal 131 is set to be equal to or greater than the horizontal length of the macro cell 100, and the vertical length of the VSS power connection terminal 132 is equal to or greater than the vertical length of the macro cell 100. Set to Note that providing a power supply terminal on a power supply line means defining a region where the power supply line exists as a power supply connection terminal.

  Contacts 121 to 124 are provided at locations where the power connection terminals 131 and 132 intersect with the upper layer power supply wires 111 to 114. More specifically, a contact 121 that connects the fourth and fifth wiring layers is provided at a location where the VDD power connection terminal 131 and the horizontal VDD power wiring 111 intersect. The macro cell VDD power supply wiring 101 and the horizontal VDD power supply wiring 111 are connected to each other by the contact 121. A contact 122 for connecting the fourth and fifth wiring layers is provided at a location where the VSS power connection terminal 132 and the horizontal VSS power wiring 112 intersect. The macro cell VSS power wiring 102 and the horizontal VSS power wiring 112 are connected to each other by the contact 122. A contact 123 that connects the fourth and sixth wiring layers is provided at a location where the VDD power connection terminal 131 and the vertical VDD power wiring 113 intersect. The macro cell VDD power supply wire 101 and the vertical VDD power supply wire 113 are connected to each other by the contact 123. A contact 124 for connecting the fourth and sixth wiring layers is provided at a location where the VSS power connection terminal 132 and the vertical VSS power wiring 114 intersect. The macro cell VSS power wiring 102 and the vertical VSS power wiring 114 are connected to each other by the contact 124.

  The process of providing the contacts 121 to 124 at the intersections of the power connection terminals 131 and 132 and the upper layer power wirings 111 to 114 can be automatically performed using an automatic wiring tool. As described above, the horizontal length of the VDD power connection terminal 131 is longer than the horizontal length of the macro cell 100, and the vertical length of the VSS power connection terminal 132 is the vertical length of the macro cell 100. By setting as described above, a large number of contacts can be provided with a high degree of freedom. In FIG. 1, the contacts 121 to 124 are provided at all the locations where the power connection terminals 131 and 132 and the upper power supply wirings 111 to 114 intersect. However, the contacts are provided at some of the locations where the two intersect. It is good as well.

  In the semiconductor integrated circuit according to the present embodiment, the width of the macro cell power supply wirings 101 and 102 is set narrower than that of the conventional semiconductor integrated circuit (FIG. 9). More specifically, the width of the macrocell power supply wirings 101 and 102 is set to be narrower than the wiring width required for supplying the power supply current to the macrocell 100 using only the macrocell power supply wirings 101 and 102.

  As described above, even if the width of the macro cell power supply wirings 101 and 102 is narrower than the conventional one, the current consumed by the macro cell 100 can be correctly supplied to the macro cell 100 for the following reason. For example, a portion (first opposing portion) extending in the horizontal direction of the macro cell VDD power supply wiring 101 and the horizontal VDD power supply wiring 111 perform the same function as the macro cell horizontal VDD power supply wiring 601 in the conventional semiconductor integrated circuit. Since the horizontal VDD power supply wiring 111 fulfills a part of the function of the macro cell horizontal VDD power supply wiring 601, the width of the first facing portion is necessary to supply the power supply current using only the macro cell power supply wirings 101 and 102. Even if it is narrower than the wiring width (that is, the width of the macro cell horizontal VDD power wiring 601), there is no problem in power supply to the macro cell 100.

  Similarly, the vertically extending portion (second opposing portion) of the macro cell VDD power supply wiring 101 and the vertical VDD power supply wiring 113 have the same function as the macro cell vertical VDD power supply wiring 603 in the conventional semiconductor integrated circuit. Fulfill. Since the vertical VDD power supply wiring 113 performs a part of the function of the macro cell vertical VDD power supply wiring 603, even if the width of the second opposing portion is narrower than that of the macro cell vertical VDD power supply wiring 603, power can be supplied to the macro cell 100. There will be no hindrance. The same applies to the width of the macro cell VSS power supply wiring 102. From the above, it is possible to correctly supply power to the macro cell 100 even if the width of the macro cell power wirings 101 and 102 is narrower than that of the conventional one.

  As described above, in the semiconductor integrated circuit according to the present embodiment, the upper layer power supply wirings 111 to 114 are connected by connecting the macrocell power supply wirings 101 and 102 and the upper layer power supply wirings 111 to 114 to each other at the intersections. Since part of the power supply function for the macro cell 100 is achieved, the power supply to the macro cell 100 can be correctly performed even if the width of the macro cell power supply wirings 101 and 102 is narrower than the conventional one. Therefore, the width of the macro cell power supply wirings 101 and 102 is made narrower than before, the macro cell 100 layout area is reduced when the macro cell power supply wirings 101 and 102 are included, and the semiconductor integrated circuit is reduced in area and cost. Can be achieved.

  Further, by forming the macro cell power supply wirings 101 and 102 in a single wiring layer, more preferably in the same wiring layer as the uppermost wiring layer used in the macro cell 100, the upper layer power supply wirings 111 to 114 and the macro cell are formed. The number of stacked stages of the contacts 121 to 124 connecting the power supply wirings 101 and 102 can be reduced. Thereby, the resistance of the power supply wiring connected to the macro cell 100 can be reduced, and the power supply voltage drop can be suppressed.

  Furthermore, by providing the power connection terminals 131 and 132 on the macro cell power lines 101 and 102, when the upper layer power lines 111 to 114 are arranged on the macro cell 100 using an automatic wiring tool, the upper layer power lines Contacts for supplying a power supply current from 111 to 114 to the macro cell 100 can be automatically provided in the macro cell layout frame 130. Therefore, it is not necessary to draw extra power supply wiring around the macro cell 100, and the layout area does not increase even when layout processing is performed using an automatic wiring tool. Thereby, the area reduction and cost reduction of the semiconductor integrated circuit can be achieved.

  Note that the semiconductor integrated circuit according to the present embodiment can be configured as follows. For example, as shown in FIG. 2, the semiconductor integrated circuit may include contacts 141 and 142 where the upper power supply wires 111 to 114 controlled to the same potential intersect. In FIG. 2, a contact 141 connecting the fifth and sixth wiring layers is provided at a location where the horizontal VDD power wiring 111 and the vertical VDD power wiring 113 intersect. The horizontal VDD power supply wiring 111 and the vertical VDD power supply wiring 113 are connected to each other by the contact 141. A contact 142 for connecting the fifth and sixth wiring layers is also provided at a location where the horizontal VSS power wiring 112 and the vertical VSS power wiring 114 intersect. The horizontal VSS power wiring 112 and the vertical VSS power wiring 114 are connected to each other by the contact 142. The semiconductor integrated circuit shown in FIG. 2 has the same effect as the semiconductor integrated circuit shown in FIG. In the semiconductor integrated circuit shown in FIG. 2, the contacts 141 and 142 are provided at all the locations where the upper-layer power supply wires 111 to 114 controlled to the same potential intersect. A contact may be provided.

  Further, the semiconductor integrated circuit only needs to include a macro cell power supply wiring having at least a pair of opposing portions, and may have the configuration shown in FIGS. 3 and 4, for example. In the semiconductor integrated circuit shown in FIG. 3, the macro cell VDD power wirings 151a and 151b constitute a pair of opposing portions, and the macro cell VSS power wirings 152a and 152b constitute a further pair of opposing portions. In the semiconductor integrated circuit shown in FIG. 4, when the macro cell VDD power supply wiring 161 is disassembled into two power supply wirings extending in the horizontal direction and one power supply wiring extending in the vertical direction, a pair extending in the horizontal direction. The power supply wiring forms a pair of opposed portions. The same applies to the VSS power wiring 162 for the macro cell. The semiconductor integrated circuit shown in FIGS. 3 and 4 has the same effect as the semiconductor integrated circuit shown in FIG. 1 although there is a difference in the degree of narrowing of the macro cell power supply wiring.

(Second Embodiment)
FIG. 5 is a diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. The semiconductor integrated circuit shown in FIG. 5 includes a macro cell 100, two macro cell power supply wires 101 and 102, and four types of upper layer power supply wires 111 to 114. This semiconductor integrated circuit is characterized in that only upper layer power wirings 111 to 114 extending in a specific direction are connected to power connection terminals 201 to 204 provided on the macro cell power wirings 101 and 102. And

  The following four types of power connection terminals 201 to 204 are provided on the macro cell power lines 101 and 102 in order to connect to the upper layer power lines 111 to 114 orthogonal to the respective lines. A vertical VDD power supply connection terminal 201 is provided on the power supply wiring extending in the horizontal direction in the macrocell VDD power supply wiring 101. A vertical VSS power supply connection terminal 202 is provided on the power supply wiring extending in the horizontal direction in the macro cell VSS power supply wiring 102. A horizontal VDD power supply connection terminal 203 is provided on the power supply wiring extending in the vertical direction in the macrocell VDD power supply wiring 101. A horizontal VSS power connection terminal 204 is provided on the power supply wiring extending in the vertical direction in the macro cell VSS power supply wiring 102. The vertical VDD power supply connection terminal 201 and the vertical VSS power supply connection terminal 202 are given an attribute to be connected only to the power supply wiring extending in the vertical direction, and the horizontal VDD power supply connection terminal 203 and the horizontal VSS power supply connection terminal 204 are given. Is given the attribute of connecting only to the power supply wiring extending in the horizontal direction.

  Similar to the semiconductor integrated circuit (FIG. 1) according to the first embodiment, contacts 121 to 124 are provided at locations where the power connection terminals 201 to 204 intersect with the upper layer power supply wires 111 to 114. However, in the semiconductor integrated circuit according to the present embodiment, the contacts 121 to 124 are provided according to the attributes of the power connection terminals 201 to 204. More specifically, a contact 123 is provided at a location where the vertical VDD power supply connection terminal 201 and the vertical VDD power supply wiring 113 intersect, but at a location where the vertical VDD power supply connection terminal 201 and the horizontal VDD power supply wiring 111 intersect. There is no contact. A contact 124 is provided at a location where the vertical VSS power connection terminal 202 and the vertical VSS power supply wiring 114 intersect, but a contact is not provided at a location where the vertical VSS power connection terminal 202 and the horizontal VSS power supply wiring 112 intersect. . A contact 121 is provided at a location where the horizontal VDD power supply connection terminal 203 and the horizontal VDD power supply wiring 111 intersect, but a contact is not provided at a location where the horizontal VDD power supply connection terminal 203 and the vertical VDD power supply wiring 113 intersect. . A contact 122 is provided at a location where the horizontal VSS power connection terminal 204 and the horizontal VSS power wiring 112 intersect, but a contact is not provided at a location where the horizontal VSS power connection terminal 204 and the vertical VSS power wiring 114 intersect. .

  As a result, the power supply wiring extending in the horizontal direction in the macro cell VDD power supply wiring 101 is not connected to the horizontal VDD power supply wiring 111 but is connected to the vertical VDD power supply wiring 113. Of the macro cell VSS power wiring 102, the power wiring extending in the horizontal direction is not connected to the horizontal VSS power wiring 112 but is connected to the vertical VSS power wiring 114. The power supply wiring extending in the vertical direction in the macrocell VDD power supply wiring 101 is not connected to the vertical VDD power supply wiring 113 but connected to the horizontal VDD power supply wiring 111. Of the macro cell VSS power wiring 102, the power wiring extending in the vertical direction is not connected to the vertical VSS power wiring 114 but is connected to the horizontal VSS power wiring 112.

  As described above, in the semiconductor integrated circuit according to the present embodiment, the power connection terminals 201 to 204 provided on the macro cell power lines 101 and 102 include the terminals of the upper layer power lines 111 to 114. Only the power supply wires extending in the short direction (that is, extending in the direction orthogonal to the macrocell power supply wires 101 and 102) are connected. For this reason, when the macro cell power supply wirings 101 and 102 and the upper layer power supply wirings 111 to 114 are overlapped in parallel, no contact is provided at a crossing point between the macro cell power supply wirings 101 and 102 and the upper layer power supply wirings 111 to 114. When 114 overlaps perpendicularly, contacts 121 to 124 are provided at locations where the two intersect. Therefore, even when two upper layer power supply wirings controlled at different potentials from the power connection terminal intersect at one place, the two contacts are not provided overlapping each other. Therefore, automatic wiring can be performed so that the two power supply wirings controlled to different potentials are not short-circuited, so that the step of correcting the layout result after automatic wiring can be omitted.

(Third embodiment)
FIG. 6 is a diagram showing a configuration of a semiconductor integrated circuit according to the third embodiment of the present invention. The semiconductor integrated circuit shown in FIG. 3 includes two macrocells 100a and 100b, two macrocell power supply wires 101 and 102, and four types of upper layer power supply wires 111 to 114. The macro cell 100a and the macro cell 100b are arranged adjacent to each other.

  Similar to the semiconductor integrated circuit according to the first embodiment (FIG. 1), the macro cell VDD power wiring 101 is disposed outside and the macro cell VSS power wiring 102 is disposed inside the macro cell 100a. The upper layer power supply lines 111 to 114 are arranged at positions passing through the upper part of the macro cell 100a. The same applies to the macro cell 100b.

  As shown in FIG. 6, a part of the macro cell VDD power wiring 101 surrounding the macro cell 100a and a part of the macro cell VDD power wiring 101 surrounding the macro cell 100b are located at the same position in the region 301. Has been placed. Since the macro cell VDD power wiring 101 is formed in the fourth wiring layer, the macro cell VDD power wiring 101 can be formed as one power wiring inside the region 301.

  As described above, according to the semiconductor integrated circuit according to the present embodiment, the outermost of the macrocells 100a and 100b that are arranged adjacent to each other, including the case where one macrocell is rotated by 90 degrees. Can share a part of the macro cell VDD power supply wiring 101. Thereby, the area reduction and cost reduction of the semiconductor integrated circuit can be achieved.

(Fourth embodiment)
FIG. 7 is a diagram showing a configuration of a semiconductor integrated circuit according to the fourth embodiment of the present invention. The semiconductor integrated circuit shown in FIG. 7 includes two macrocells 100a and 100b, two macrocell power supply wires 101 and 102, and four types of upper layer power supply wires 111 to 114. Hereinafter, differences between the semiconductor integrated circuit according to the present embodiment and the semiconductor integrated circuit according to the third embodiment (FIG. 6) will be described.

  In the semiconductor integrated circuit according to the present embodiment, as in the semiconductor integrated circuit according to the third embodiment, a part of the macro cell VDD power wiring 101 surrounding the macro cell 100a and the macro cell VDD power wiring surrounding the macro cell 100b. A part of 101 is arranged at the same position. In addition, a part of the macro cell VSS power wiring 102 surrounding the macro cell 100 a and a part of the macro cell VSS power wiring 102 surrounding the macro cell 100 b are arranged at the same position in the region 401. ing. Since the macro cell VSS power wiring 102 is formed in the fourth wiring layer, the macro cell VSS power wiring 102 can be formed as a single power wiring inside the region 401.

  In order to connect the macro cell VSS power wiring 102 surrounding the macro cell 100a and the macro cell VSS power wiring 102 surrounding the macro cell 100b, the semiconductor integrated circuit includes two bridge power wirings 402 and four contacts 403. ing. The bridge power supply wiring 402 is a power supply wiring that connects the macro cell VSS power supply wiring 102 surrounding the macro cell 100a and the macro cell VSS power supply wiring 102 surrounding the macro cell 100b. The bridge power supply wiring 402 is formed in a lower wiring layer than the wiring layer used in the macrocell power supply wirings 101 and 102. In this embodiment, the bridge power supply wiring 402 is formed in a third wiring layer lower than the fourth wiring layer used in the macrocell power supply wirings 101 and 102. A contact 403 connects the third and fourth wiring layers. The bridge power supply wiring 402 and the macro cell VSS power supply wiring 102 are connected to each other by the contact 403, whereby the macro cell VSS power supply wiring 102 that surrounds the macro cell 100a and the macro cell VSS power supply wiring 102 that surrounds the macro cell 100b are: Connected to each other.

  As described above, according to the semiconductor integrated circuit according to the present embodiment, the outermost of the macrocells 100a and 100b that are arranged adjacent to each other, including the case where one macrocell is rotated by 90 degrees. It is possible to share a part of the macro cell VSS power supply wiring 102 other than those arranged in the above. Thereby, the area reduction and cost reduction of the semiconductor integrated circuit can be achieved.

(Fifth embodiment)
FIG. 8 is a diagram showing a configuration of a semiconductor integrated circuit according to the fifth embodiment of the present invention. The semiconductor integrated circuit shown in FIG. 8 includes a macro cell 500, two macro cell power supply wires 101 and 102, four types of upper layer power supply wires 111 to 114, and shield power supply wires 501 and 502.

  Unlike the semiconductor integrated circuits according to the first to fourth embodiments, the macro cell 500 is a memory macro cell that includes a plurality of memory elements and includes a third or lower wiring layer. The macro cell 500 has a signal connection terminal 508 in the same wiring layer (here, the third wiring layer) as the uppermost wiring layer used in the macro cell 500. A signal wiring (not shown) formed in a wiring layer higher than the wiring layer used in the macro cell 500 is connected to the signal connection terminal 508.

  Shield power supply wirings 501 and 502 are arranged at positions that cover a part of the macrocell 500 in a wiring layer higher than the wiring layer used in the macrocell 500 and lower than the upper power supply wirings 111 to 114. . In the present embodiment, the shield power supply wirings 501 and 502 are formed in the fourth wiring layer. The shield power supply wirings 501 and 502 are connected to the macrocell power supply wirings 101 and 102 formed in the fourth wiring layer, respectively. Since the macro cell VSS power supply line 102 is disposed inside the macro cell VDD power supply line 101, the shield power supply line 502 and the macro cell VSS power supply line 102 are directly connected. On the other hand, the shield power supply wiring 501 and the macro cell VDD power supply wiring 101 include a power supply wiring 503 formed in the third wiring layer, and a contact 504 connecting the power supply wiring 503 and the macro cell VDD power supply wiring 101. The power supply wiring 503 and the contact 505 connecting the shield power supply wiring 501 are connected. The shield power supply wirings 501 and 502 connected in this manner have a function of shielding noise from the upper power supply wirings 111 to 114 with respect to the macro cell 500 (specifically, a memory element included in the macro cell 500).

  A power connection terminal 506 for connecting to the upper layer power lines 111 and 112 is provided on the shield power lines 501 and 502. The location where the power supply connection terminal 506 provided on the shield power supply wiring 501 and the horizontal VDD power supply wiring 111 intersect, and the power supply connection terminal 506 provided on the shield power supply wiring 502 and the horizontal VSS power supply wiring A contact 507 for connecting the fourth and fifth wiring layers is provided at a location where 112 intersects.

  As described above, in the semiconductor integrated circuit according to the present embodiment, the power connection terminal 506 is provided on the shield power wirings 501 and 502 disposed on the macro cell 500, and the power connection terminal 506 and the upper layer are connected. A contact 507 is provided at a location where the power supply lines 111 and 112 intersect. Accordingly, even when it is difficult to provide a contact inside the macro cell layout frame because the memory macro cell is laid out at a high density, a contact is provided inside the macro cell layout frame above the macro cell 500. Can do. Therefore, it is not necessary to modify the layout data of the macro cell in order to make a space for arranging the contact. Therefore, it is possible to reduce the area and cost of the semiconductor integrated circuit and reduce the number of layout steps.

  Further, by providing the signal connection terminal 508 in the uppermost wiring layer used in the macro cell 500, the signal wiring (see FIG. 5) formed in the macro cell 500 and a wiring layer higher than the wiring layer used in the macro cell 500. Can be directly connected using contacts (not shown). Thereby, the area reduction and cost reduction of the semiconductor integrated circuit can be achieved.

  In this embodiment, as an example, the macro cell 500 is a memory macro cell. However, the macro cell 500 may be provided with a contact for connecting to a power supply wiring or a signal wiring, such as an analog cell. Other types of macro cells that are difficult may be used.

  The semiconductor integrated circuit of the present invention is characterized in that the macro cell power supply wiring is narrow and has a small area and low cost. Therefore, the semiconductor integrated circuit can be used for a system-on-chip in which a plurality of macro cells are integrated on a single semiconductor chip. Can do.

The figure which shows the structure of the semiconductor integrated circuit which concerns on the 1st Embodiment of this invention. The figure which shows the structure of the semiconductor integrated circuit which concerns on the 1st modification of the 1st Embodiment of this invention. The figure which shows the structure of the semiconductor integrated circuit which concerns on the 2nd modification of the 1st Embodiment of this invention. The figure which shows the structure of the semiconductor integrated circuit which concerns on the 3rd modification of the 1st Embodiment of this invention. The figure which shows the structure of the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. The figure which shows the structure of the semiconductor integrated circuit which concerns on the 3rd Embodiment of this invention. The figure which shows the structure of the semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. The figure which shows the structure of the semiconductor integrated circuit which concerns on the 5th Embodiment of this invention. The figure which shows the structure of the conventional semiconductor integrated circuit The figure which shows the example of a connection of the macrocell and upper layer power supply wiring in the semiconductor integrated circuit shown in FIG.

Explanation of symbols

100, 500 ... Macro cell 101, 151, 161 ... Macro cell VDD power supply wiring 102, 152, 162 ... Macro cell VSS power supply wiring 111 ... Horizontal VDD power supply wiring 112 ... Horizontal VSS power supply wiring 113 ... Vertical VDD power supply wiring 114 ... Vertical VSS power supply Wiring 121-124, 141, 142, 403, 504, 505, 507 ... Contact 130 ... Macro cell layout frame 131 ... VDD power supply connection terminal 132 ... VSS power supply connection terminal 201 ... Vertical VDD power supply connection terminal 202 ... Vertical VSS power supply Connection terminal 203 ... Horizontal VDD power supply connection terminal 204 ... Horizontal VSS power supply connection terminals 301 and 401 ... Region 402 ... Bridge power supply wiring 501 and 502 ... Shield power supply wiring 503 ... Power supply wiring 506 ... Power supply connection terminal 508 ... Signal Terminal for connection

Claims (16)

A semiconductor integrated circuit having a multilayer wiring structure,
A macro cell configured using a predetermined or less wiring layer;
Having at least a pair of opposed portions arranged at positions sandwiching the macro cell, and supplying a macro cell power supply wiring for supplying a power source current to the macro cell;
In the wiring layer higher than the wiring layer used in the macro cell and the power supply wiring for the macro cell, an upper layer power wiring arranged at a position passing through the upper part of the macro cell, and
The macro cell power supply wiring and the upper layer power supply wiring are connected to each other at a location where the facing portion of the macro cell power supply wiring and the upper layer power supply wiring intersect,
A width of the macro cell power supply wiring is narrower than a width of a wiring required for supplying a power supply current to the macro cell using only the wiring.   2. The semiconductor integrated circuit according to claim 1, wherein the macro cell power supply wiring is formed in a single wiring layer.   3. The semiconductor integrated circuit according to claim 2, wherein the macro cell power supply wiring is formed in the same wiring layer as the uppermost wiring layer used in the macro cell.   The semiconductor integrated circuit according to claim 1, wherein the upper layer power supply wiring is formed in a wiring layer having a sheet resistance lower than that of a wiring layer used in the macro cell.   2. The semiconductor integrated circuit according to claim 1, wherein the upper layer power supply lines controlled to the same potential are connected to each other at a crossing position in an upper portion of the macro cell. The macrocell has a rectangular shape having first and second sides orthogonal to each other,
2. The semiconductor integrated circuit according to claim 1, wherein the macro cell power supply wiring includes first and second power supply wirings arranged in parallel to the first side as the facing portion. 3.   The semiconductor integrated circuit according to claim 6, wherein the macro cell power supply wiring further includes third and fourth power supply wirings arranged in parallel to the second side as the opposing portion.   8. The semiconductor integrated circuit according to claim 7, wherein the macro cell power supply wiring is a ring-shaped wiring that includes the first to fourth power supply wirings and surrounds the macro cell.   The opposing portion is provided with a power connection terminal having a length equal to or longer than the length of the first side, and a power wiring arranged outside the macro cell is connected to the power connection terminal. The semiconductor integrated circuit according to claim 6, wherein:   The opposing portion is provided with a power supply connection terminal, and the power supply connection terminal is not connected to the upper layer power supply wiring extending in the direction of the first side, and is connected to the second side. The semiconductor integrated circuit according to claim 6, wherein the upper layer power supply wiring extending in a direction is connected. A plurality of said macrocells;
The macro cell power supply wiring for each macro cell,
2. The semiconductor integrated circuit according to claim 1, wherein a part of the macro cell power supply wiring is disposed at the same position between the macro cells arranged adjacent to each other. For each of the macrocells, the plurality of macrocell power supply wirings arranged at different distances from each macrocell,
12. The semiconductor according to claim 11, wherein a part of the power wiring for the macro cell arranged at a position farthest from each macro cell is arranged at the same position between the macro cells arranged adjacent to each other. Integrated circuit. For each of the macrocells, the plurality of macrocell power supply wirings arranged at different distances from each macrocell,
The part of the macro cell power supply wiring other than the one arranged farthest from each macro cell is arranged at the same position between the macro cells arranged adjacent to each other. The semiconductor integrated circuit as described. A shielding power supply wiring disposed at a position covering a part of the macrocell in a wiring layer higher than the wiring layer used in the macrocell and lower than the wiring layer used in the upper power supply wiring. In addition,
2. The semiconductor integrated circuit according to claim 1, wherein the upper layer power supply wiring and the shield wiring are connected to each other at an intersecting portion in an upper portion of the macro cell.   15. The semiconductor integrated circuit according to claim 14, wherein the input / output terminals of the macro cell are formed in the same wiring layer as the uppermost wiring layer used in the macro cell. The semiconductor integrated circuit according to claim 14, wherein the macro cell is a memory macro cell including a plurality of memory elements.

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