JP2006210678A - Semiconductor integrated circuit device and its layout design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device improving analog characteristics, further improving the degree of freedom of a design and inhibiting the increase of a substrate area. <P>SOLUTION: A gate region 12 in which an analog macro-region 14 with a built-in area I/0 for an analog power supply or for an analog signal is arranged, and a peripheral I/0 circuit region 16, are formed to the semiconductor integrated circuit device. An analog macro region 14 and a micro region 13 are arranged at the arbitrary places of the gate region 12 on a chip 11. The analog macro 14 may also contain a singular number or a plurality of the areas I/O. A basic cell and a plurality of logic gates are further disposed in the gate region 12. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a layout design of a semiconductor integrated circuit having an analog macro region.

  Conventionally, various methods have been proposed as a layout design method for a semiconductor integrated circuit device having an analog macro region depending on the purpose.

  FIG. 4 is a plan view showing a semiconductor integrated circuit device designed by the layout designing method according to the first conventional example. In the layout design method of the semiconductor integrated circuit device shown in FIG. 1, an analog power supply or analog signal is supplied to an analog macro cell in the analog macro area 102, so that an analog macro input / output circuit area ( Hereinafter, the “analog macro I / O circuit area” 101) 101 and the analog macro area 102 are connected to each other by wiring. Therefore, as shown in FIG. 4, the analog macro area 102 is arranged in the vicinity of the analog macro I / O circuit area 101 in consideration of ensuring of analog characteristics and noise care at the time of design.

  FIGS. 5A and 5B are a plan view (left view) and a cross-sectional view (right view) for explaining the layout design method of the semiconductor integrated circuit device according to the second conventional example. In the layout design method according to this conventional example, the wiring connecting each circuit is divided into the upper wiring 202 and the lower wiring 204 connected to the upper wiring 202 by the contact via 203, and the upper wiring 202, the lower wiring 204, The wiring resistance can be lowered by superimposing them in a plane. For this reason, the layout design method according to the second conventional example is used to ensure the characteristics of the analog circuit, such as when the wiring resistance of the analog signal wiring must be kept below a certain reference value.

  FIG. 6 is a plan view showing a part of a semiconductor integrated circuit device designed by the layout designing method according to the third conventional example. As shown in the figure, in the layout design method according to the third conventional example, the noise of the digital signal is reduced by setting the interval between the analog wiring 301 and the digital wiring 302 to a predetermined value or more in the same wiring layer. Is prevented from interfering with analog signals.

  FIG. 7 is a plan view showing a part of a semiconductor integrated circuit device designed by the layout designing method according to the fourth conventional example. As shown in the figure, noise can be absorbed by the VSS wiring 401 by arranging the VSS wiring 401 on both sides or one side of the analog wiring 402. Therefore, it is possible to design a semiconductor integrated circuit device in which noise propagating to the analog wiring 402 is suppressed and analog characteristics are improved.

  FIG. 8 is a plan view showing a part of a semiconductor integrated circuit device designed by the layout designing method according to the fifth conventional example. In this layout design method, a signal input to the first analog macro area 501 and a signal output from the first analog macro area 501 are input to the second analog macro area 502 and from the second analog macro area 502. This is used when each signal output must be simultaneous. As shown in FIG. 8, in the layout design method according to the fifth conventional example, the length of the first analog wiring 504 connecting the first analog macro area 501 and the analog macro I / O circuit area 503 is as follows. It is designed to be equal to the length of the second analog wiring 505 connecting the second analog macro area 502 and the analog macro I / O circuit area 503. According to this method, since the wiring resistance in the first analog wiring 504 and the wiring resistance in the second analog wiring 505 can be made equal, the signal input to the first analog macro area 501 and the first analog macro area 501 are made. Can be made substantially equal to the signal input to the second analog macro region 502 and the signal output from the second analog macro region 502, respectively.

As described above, various layout design methods have been proposed in the past in order to manufacture a semiconductor integrated circuit device in which deterioration of analog characteristics is suppressed.
JP 2004-47516 A

  However, in the first conventional example, the analog macro area 102 is necessarily arranged in the vicinity of the analog macro I / O circuit area 101 in order to shorten the wiring length, and the degree of freedom in layout design is reduced. There is a problem that.

  FIG. 9 is a plan view schematically showing a part of a semiconductor integrated circuit device according to a third conventional example. As shown in the figure, in the semiconductor integrated circuit device designed by the methods of the second conventional example and the third conventional example, the analog macro I / O circuit region 601 (the analog macro I / O circuit of FIG. 5) is used. The analog macro area 604 is connected to the analog macro area 604 (corresponding to the analog macro area 201 in FIG. 5 and the analog macro area 303 in FIG. 6). A dead space 603 occurs between the / O circuit region 601 and the chip size increases. Further, in the fourth conventional example, since the VSS wiring 401 is arranged around the analog wiring 401, the chip area is increased by the area of the VSS wiring 401. In the fifth conventional example, it may be difficult in layout design to make the length of the first analog wiring 504 and the length of the second analog wiring 505 equal.

  Thus, there is room for improvement in any of the conventional layout design methods.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a layout design method for a semiconductor integrated circuit device in which the degree of freedom in layout design is improved while improving analog characteristics. It is another object of the present invention to provide a layout design method capable of suppressing an increase in chip size and equalizing input / output timings in a plurality of analog macro areas.

  The semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device provided on a chip, and includes a gate region in which an analog macro region having an analog macro cell and an area I / O for the analog macro cell is arranged. ing.

  With this configuration, the position where the analog macro area can be arranged is not limited as compared with the case where the analog macro cell I / O circuit is arranged around the periphery of the chip, and the degree of freedom in layout can be improved. In addition, the semiconductor integrated circuit device of the present invention has an analog macro area with built-in area I / O, which eliminates the need to use an analog macro I / O circuit area, thereby reducing the number of I / O circuits. can do. In addition, since the wiring for connecting the analog macro area and the analog macro cell I / O circuit can be omitted or shortened, the analog wiring is arranged away from the digital wiring, or the analog wiring is VSS wiring (ground line). It is no longer necessary to take measures to suppress the influence of noise, such as by placing it adjacent to. Therefore, dead space can be reduced and increase in circuit area and chip size can be suppressed. In addition, with the configuration of the semiconductor integrated circuit device of the present invention, a layout that satisfies the conditions can be easily designed even when two analog macrocells connected to the same I / O circuit need to input / output signals simultaneously. Will be able to.

  The semiconductor integrated circuit device preferably further includes a peripheral I / O circuit region disposed in the peripheral portion of the chip.

  The area I / O preferably includes an analog power supply area I / O or an analog signal area I / O.

  In the layout design method for a semiconductor integrated circuit device according to the present invention, an analog macro region including an analog macro cell and an area I / O for the analog macro cell is arranged in a gate region provided on a chip using a computer. Has steps.

  According to this method, the analog macro area in which the area I / O is built in can be arranged at an arbitrary position in the gate area, so that the degree of freedom in layout design can be improved. In addition, since the wiring connecting the analog macro region and the analog macrocell I / O circuit can be shortened, a semiconductor integrated circuit device with reduced wiring resistance can be designed. Furthermore, it is possible to easily design a semiconductor integrated circuit device in which dead space generated during noise countermeasures is reduced. In addition, even in the case where two analog macrocells connected to the same I / O circuit need to input and output signals at the same time, a layout that satisfies the conditions can be easily designed.

  According to the layout design method for a semiconductor integrated circuit of the present invention, the analog macro area containing the area I / O is provided at an arbitrary position in the gate area. Therefore, the analog macro I / O circuit is provided at the peripheral portion of the chip. The degree of freedom in layout design can be improved as compared with the case of arrangement.

  Further, according to the semiconductor integrated circuit layout design method of the present invention, the dead space generated on the chip can be reduced, and the increase in the chip area can be suppressed. Furthermore, according to the layout design method of the present invention, it is possible to design a semiconductor integrated circuit device that sufficiently satisfies the characteristics of the analog macro region without considering power supply to the analog macro region and noise countermeasures.

  Furthermore, by directly bonding signal wiring to the I / O circuit pads of the analog macros with a plurality of area I / Os, the layout for equalizing the input / output timing of signals in the plurality of analog macro areas can be easily performed. You can do it.

  Hereinafter, an example of a semiconductor integrated circuit device and a layout design method thereof according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a plan view schematically showing an analog macro region in the semiconductor integrated circuit device according to this embodiment. FIG. 2 is a schematic view of a chip provided with the semiconductor integrated circuit device according to this embodiment. FIG.

  As shown in FIG. 1, the layout design method for a semiconductor integrated circuit device according to the present embodiment has an analog power supply area input / output circuit (hereinafter abbreviated as “analog power supply area I / O”) inside an analog macro region 14. ) 15a, an area input / output circuit for analog signals (hereinafter, abbreviated as “analog signal area I / O”) 15b, and the like. Here, the analog macro area 14 is an area where a large number of analog macro cells including analog elements are arranged on the chip 11.

  As shown in FIG. 2, the semiconductor integrated circuit device formed on the chip 11 and designed by the layout design method of this embodiment has a macro area 13 in which macro cells are arranged, an analog power supply area I / O 15a, an analog signal, and the like. Gate area 12 provided with analog macro area 14 and basic cells (not shown) incorporating area I / O such as area I / O 15b, and peripheral I / O circuit disposed in the peripheral portion of chip 11 Region 16.

  The peripheral I / O circuit region 16 is a region where input / output circuits for cells other than analog macro cells such as macro cells, basic cells, and logic cells are provided. The peripheral I / O circuit area 16 is continuously provided in the entire area where elements can be installed in the vicinity of the outer periphery of the chip 11.

  As described above, the gate region 12 is provided on the chip 11 and has a macro cell having a function such as a RAM (Random Access Memory) and a ROM (Read Only Memory), a basic cell, an analog macro region incorporating an area I / O, a logic This is the area where cells are placed.

  The analog macro area 14 incorporating the area I / O is provided at an arbitrary position on the chip 11. That is, in the semiconductor integrated circuit device of this embodiment, the positions of the gate region 12 including the analog macro region 14 and the peripheral I / O circuit region 16 can be freely arranged without being fixed in advance.

  Next, an example of a layout design method for a semiconductor integrated circuit device according to the present invention will be described. FIG. 3 is a flowchart showing the layout design method of this embodiment.

  First, in step S1 shown in FIG. 3, the designer prepares information necessary for layout design, that is, circuit connection information, a library of basic cells, macro cells, other cells, I / O circuit arrangement information, position information, and the like. To do. These pieces of information are stored in advance in hardware means such as a memory.

  Next, in step S2, the size of the chip 11 is determined, and on the basis of the I / O circuit arrangement information prepared in step S1, the I / O circuit for the basic cell and the macro area 13 is added to the chip 11. It is arranged in the peripheral I / O circuit area 16 provided.

  Next, in step S3, an analog macro area 14 including an analog macro cell and an area I / O for the analog macro cell and a macro area 13 including the macro cell are arranged in the gate area 12 provided in the chip 11. . Note that one or more analog macro regions 14 are provided in the gate region 12.

  Next, in step S4, basic cells and other cells are arranged in the gate region 12 excluding the macro region 13 and the analog macro region 14 arranged in step S3.

  Through the above steps, the layout design of the semiconductor integrated circuit of the present embodiment is realized. Note that steps S2 to S4 are performed by a computer or the like in which a layout design tool is incorporated.

  In the layout design method of the present embodiment, the analog macro area 14 in which the analog macro cell and the area I / O for the analog macro cell are arranged as one design unit. Therefore, a dead space can be set at an arbitrary place on the chip 11. The analog macro area 14 can be arranged while suppressing enlargement.

  Further, according to the layout design method of the present embodiment, it is not necessary to arrange the analog macro area 14 in the vicinity of the analog macro I / O circuit area 101 (see FIG. 4), so the first conventional technique shown in FIG. The degree of freedom in layout can be improved compared to the example. Further, by using the analog macro area 14 in which the area I / O is arranged, it is not necessary to use the analog macro I / O circuit area 101, so that the number of I / O circuits can be reduced.

  Furthermore, in the semiconductor integrated circuit device laid out by the method of the present embodiment, the power supply wiring (power supply terminal) is connected to the analog power supply area I / O 15a and the analog signal area I / O arranged in the analog macro area 14, respectively. ) And signal wiring (signal terminals) are directly bonded to each other, so that the power supply voltage and signal are supplied. Therefore, the wiring for connecting the analog macro I / O circuit and the analog macro area can be omitted or shortened. Therefore, the wiring resistance between the analog macro I / O circuit and the analog macro cell can be reduced as compared with the conventional semiconductor integrated circuit. Further, in the semiconductor integrated circuit device of this embodiment, it is possible to suppress the dead space generated or increased when the methods of the second to fourth conventional examples are performed. That is, according to the layout design method of the present embodiment, it is possible to design a semiconductor integrated circuit device in which analog characteristics are ensured while suppressing an increase in chip size.

  Further, in the case where two analog macrocells connected to the same I / O circuit need to simultaneously input and output signals, the analog signal area I / O 15b includes an analog macrocell 14 including a plurality of analog macrocells. Therefore, a layout satisfying the conditions can be easily designed. In addition, according to the layout design method of the present embodiment, two analog macro areas 14 are provided, and the design when signals are input / output simultaneously in both analog macro areas 14 can be easily performed.

  As described above, according to the layout design method of the present embodiment, it is possible to improve the degree of freedom in layout design while ensuring the required analog characteristics, and to suppress an increase in chip size. it can.

  In the example shown in FIG. 2, only one analog power source area I / O 15 a and one analog signal area I / O 15 b are provided in the analog macro area 14. Good.

  In addition, the layout design method of this embodiment uses the size of the peripheral I / O circuit region 16 formed on the chip 11 and the arrangement configuration of pads provided on the peripheral I / O circuit region 16 (for example, a lattice shape or a staggered pattern). ), Even when the pad pitch is changed, it can be applied in the same manner as in the above example.

  As described above, the layout design method of the present invention is useful for the design of a semiconductor integrated circuit device on which an analog circuit is mounted. The semiconductor integrated circuit device designed by the method of the present invention can be used in various electrical devices. Used.

It is a top view which shows typically an analog macro area | region among the semiconductor integrated circuit devices which concern on embodiment of this invention. 1 is a plan view schematically showing a chip provided with a semiconductor integrated circuit device according to an embodiment of the present invention. It is a flowchart which shows the layout design method which concerns on embodiment of this invention. It is a top view which shows the semiconductor integrated circuit device designed by the layout design method concerning the 1st prior art example. It is the top view (left figure) and sectional drawing (right figure) for demonstrating the layout design method of the semiconductor integrated circuit device based on a 2nd prior art example. It is a top view which shows a part of semiconductor integrated circuit device designed by the layout design method concerning a 3rd prior art example. It is a top view which shows a part of semiconductor integrated circuit device designed by the layout design method concerning the 4th prior art example. It is a top view which shows a part of semiconductor integrated circuit device designed by the layout design method concerning the 5th prior art example. It is a top view which shows typically a part of semiconductor integrated circuit device based on a 3rd prior art example.

Explanation of symbols

11 Chip 12 Gate area 13 Macro area 14 Analog macro area 15a Analog power supply area I / O
15b Analog signal area I / O
16 Peripheral I / O circuit area

Claims (6)

A semiconductor integrated circuit device provided on a chip,
A semiconductor integrated circuit device comprising a gate region in which an analog macro region having an analog macro cell and an area I / O for the analog macro cell is disposed.   The semiconductor integrated circuit device according to claim 1, further comprising a peripheral I / O circuit region disposed in a peripheral portion of the chip.   2. The semiconductor integrated circuit device according to claim 1, wherein the area I / O includes an analog power supply area I / O or an analog signal area I / O.   A layout design method for a semiconductor integrated circuit device, comprising: using a computer to arrange an analog macro area including an analog macro cell and an area I / O for the analog macro cell in a gate area provided on a chip. .   5. The semiconductor integrated circuit device layout design method according to claim 4, wherein the area I / O is an I / O circuit for an analog power supply or an analog signal.   5. The layout design method for a semiconductor integrated circuit device according to claim 4, wherein the analog macro region is arranged at an arbitrary position of the gate region.

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