JP2008218751A - Semiconductor device and i/o cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of an I/O cell can be used for any arrangement of a vertical arrangement and a horizontal arrangement. <P>SOLUTION: The semiconductor device comprises a core circuit, a plurality of power supply wiring for supplying a plurality of power supply voltage, and the I/O cell electrically connected to the plurality of power supply wirings through a plurality of contact positions and outputing/inputting a signal between the core circuit and the outside. Differing contact positions connected to differing power supply voltages out of the plurality of contact positions are not arranged on an identical straight line in any direction of a long side direction and a short side direction of the I/O cell. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention generally relates to semiconductor devices, and particularly relates to an I / O cell of a semiconductor device.

  In a semiconductor integrated circuit, input / output of signals between an external pin and a core circuit is performed via a lead frame, bonding wires, pads, and I / O cells. Here, the I / O cell is a section made up of input / output semiconductor elements provided corresponding to pads for bonding wire connection. The I / O cell may be provided with a circuit for preventing electrostatic breakdown in addition to the input / output semiconductor element. The electrical connection between the pad and the I / O cell is made through multilayer wiring.

  In recent years, the number of pins of a semiconductor integrated circuit has increased, and accordingly, it is necessary to reduce the pitch of the arrangement of I / O cells (partitions where input / output semiconductor elements are provided). When I / O cells are arranged on the outer periphery of the core circuit area, in order to arrange as many I / O cells as possible, the I / O cells are arranged so that the length direction of the I / O cells is perpendicular to the chip side. It is desirable to do.

  FIG. 1 is a diagram showing a configuration in which I / O cells are arranged so that the length direction of the I / O cells is perpendicular to the sides of the chip. A semiconductor chip 10 shown in FIG. 1 includes a core circuit 11, a plurality of I / O cells 12 arranged on the outer periphery of the chip, and power supply wirings 13 to 15. The power supply wirings 13 to 15 supply, for example, two different power supply voltages and one ground voltage.

  FIG. 2 is an enlarged view of a portion A shown in FIG. As shown in FIG. 2, the I / O cell 12 is provided with a plurality of contact regions 16, and these contact regions 16 are electrically connected to the power supply wirings 13 to 15. The I / O cell 12 receives the power supply voltage and the ground voltage from the power supply wirings 13 to 15 through the contact region 16. As shown in FIGS. 1 and 2, the I / O cell 12 is a substantially rectangular region, and the length direction (direction in which the long side extends) is perpendicular to the side of the semiconductor chip 10, that is, the width. The direction (the direction in which the short side extends) is arranged to be horizontal with the side of the semiconductor chip 10.

  The arrangement of the I / O cell 12 as shown in FIG. 1 has the advantage that a large number of pins can be provided at a narrow pitch, but the length direction of the I / O cell 12 is perpendicular to the side of the semiconductor chip 10. For this reason, the chip size is increased by the length of the long side of the I / O cell 12. Therefore, when there is a strong demand for reducing the chip size, a configuration in which the length direction of the I / O cell 12 is parallel to the side of the semiconductor chip 10 can be considered.

  FIG. 3 is a diagram illustrating a configuration in which the I / O cells are arranged so that the length direction of the I / O cells is parallel to the side of the chip. 3, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted. In FIG. 3, the plurality of I / O cells 12 </ b> A are arranged so that the length direction thereof is parallel to the side of the semiconductor chip 10.

  FIG. 4 is an enlarged view of a portion A shown in FIG. As shown in FIG. 4, the I / O cell 12 </ b> A is provided with a plurality of contact regions 17, and these contact regions 17 are electrically connected to the power supply wirings 13 to 15. The I / O cell 12A receives the power supply voltage and the ground voltage from the power supply wirings 13 to 15 through the contact region 17. As shown in FIGS. 3 and 4, the I / O cell 12 is a substantially rectangular region, and the length direction (direction in which the long side extends) is parallel to the side of the semiconductor chip 10, that is, the width. The direction (the direction in which the short side extends) is arranged to be perpendicular to the side of the semiconductor chip 10.

  The I / O cell 12 arranged as shown in FIG. 1 and FIG. 2 and the I / O cell 12A arranged as shown in FIG. 3 and FIG. I can't. This is because the power contact position 16 between the I / O cell 12 and the power wirings 13 to 15 shown in FIG. 2 is different from the power contact position 17 between the I / O cell 12A and the power wirings 13 to 15 shown in FIG. It is.

  FIG. 5 is a diagram showing an example of a cross-sectional view of the power supply contact arrangement of the I / O cell. In FIG. 5, a plurality of wells 21 are formed in the semiconductor substrate 20, and a diffusion layer 22 is formed in each well 21. A gate electrode 23 is provided between the adjacent diffusion layers 22 in each well 21 to constitute a transistor. These transistors are input / output semiconductor elements of the I / O cell, and are connected to the pads 26 or the core circuit inside the chip through contacts, wiring layers, vias, and the like. The pad 26 is provided in an opening portion of the surface protective film 27 provided further above the uppermost layer of the wiring layer, and the pad 26 is connected to an external lead frame or the like with a bonding wire, for example.

  In FIG. 5, it is assumed that the wiring 25 electrically connected to the diffusion layer 22 through the contact 24 is a power supply wiring. Further, it is assumed that the contact 24 is a contact provided at a position B shown in FIG. 2, for example. If the I / O cell 12 of FIG. 2 and the I / O cell 12A of FIG. 4 are I / O cells of the same design, FIG. 4 corresponding to the position B in the I / O cell 12 of FIG. Since the contact position in the I / O cell 12A is the position C, the contact at the position C in FIG. 4 is the contact 24 in FIG. However, the contact region 16 provided at the position B in FIG. 2 is connected to the power supply wiring 13, and the contact region 17 provided at the position C in FIG. 4 is connected to the power supply wiring 15. . Therefore, the same circuit portion of the I / O cell of the same design (the diffusion layer 22 to which the contact 24 of FIG. 5 is connected) has different power supply wirings (that is, different power supply voltages) in the arrangement of FIG. ) Will be connected. For this reason, the I / O cell 12 of the vertical arrangement shown in FIGS. 1 and 2 and the I / O cell 12A of the horizontal arrangement shown in FIGS. 3 and 4 have the same design. Cannot be used.

Therefore, in the case where it is possible to cope with either the vertical arrangement shown in FIGS. 1 and 2 and the horizontal arrangement shown in FIGS. It is necessary to design and prepare individual I / O cells for each of the horizontal installations. This leads to an increase in design man-hours, that is, development costs, which is not preferable.
Japanese Patent Laid-Open No. 7-14926

  In view of the above, an object of the present invention is to provide an I / O cell having a configuration that can be used for both vertical and horizontal placement.

  The semiconductor device includes a core circuit, a plurality of power supply wirings that supply a plurality of power supply voltages, and a plurality of contact positions electrically connected to the plurality of power supply wirings via a plurality of contact positions, and signals between the core circuit and the outside. Including the I / O cell for input / output, different contact positions connected to different power supply voltages among the plurality of contact positions are on the same straight line in both the long side direction and the short side direction of the I / O cell. It arrange | positions so that it may not be located in.

  According to at least one embodiment of the present invention, different contact positions connected to different power supply voltages among a plurality of contact positions are collinear in both the long side direction and the short side direction of the I / O cell. By designing the I / O cell so that it is not positioned at the same position, it is possible to connect each contact appropriately to the linearly extending power supply wiring regardless of whether the I / O cell is placed vertically or horizontally. It becomes possible. Therefore, when both the vertical placement and the horizontal placement can be supported and one of them is appropriately selected and implemented, one I / O cell is commonly used for the vertical placement and the horizontal placement. Design and prepare. This makes it possible to reduce design man-hours, that is, development costs, as compared to the case where individual I / O cells are designed and prepared as in the prior art.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 6 is a diagram showing a configuration in which the I / O cells according to the embodiment of the present invention are arranged so that the length direction thereof is perpendicular to the side of the chip. The semiconductor chip 30 shown in FIG. 6 includes a core circuit 31, a plurality of I / O cells 32 arranged on the outer periphery of the chip, and power supply wirings 33 to 35. The power supply wirings 33 to 35 supply, for example, power supply voltages having two different potentials and one ground voltage.

  FIG. 7 is an enlarged view of a portion A shown in FIG. As shown in FIG. 7, the I / O cell 32 is provided with a plurality of contact regions 36, and these contact regions 36 are electrically connected to power supply wirings 33 to 35. The I / O cell 32 receives the power supply voltage and the ground voltage from the power supply wirings 33 to 35 through the contact region 36. As shown in FIGS. 6 and 7, the I / O cell 32 is a substantially rectangular region, and the length direction (the direction in which the long side extends) is perpendicular to the side of the semiconductor chip 30, that is, the width. The direction (the direction in which the short side extends) is arranged so as to be horizontal with the side of the semiconductor chip 30.

  As shown in FIG. 7, in the embodiment of the present invention, the core circuit 31 and the semiconductor chip 30 are electrically connected to the plurality of power supply wirings 33 to 35 through the plurality of contact positions (positions of the contact regions 36). In the I / O cell 32 for inputting / outputting signals to / from the outside, different contact positions connected to different power supply voltages among the plurality of contact positions are either in the long side direction or the short side direction of the I / O cell 32. It is arranged so that it is not located on the same straight line in the direction. That is, in FIG. 7, the three contact regions 36 connected to the three different power supply lines 33 to 35 are arranged so as not to be located on the same straight line in the long side direction of the I / O cell 32 indicated by the arrow A1. Has been. Further, the three contact regions 36 connected to the three different power supply lines 33 to 35 are arranged so as not to be located on the same straight line in the short side direction of the I / O cell 32 indicated by the arrow A2. . More specifically, the plurality of contact positions are arranged substantially in a row in an oblique direction in the I / O cell 32.

  When the I / O cell 32 is arranged as shown in FIG. 6, there is an advantage that a large number of pins can be provided with a narrow pitch, but the length direction of the I / O cell 32 is perpendicular to the side of the semiconductor chip 30. For this reason, the chip size is increased by the length of the long side of the I / O cell 32. Thus, when there is a strong demand for reducing the chip size, a configuration in which the length direction of the I / O cell 32 is parallel to the side of the semiconductor chip 30 can be considered.

  FIG. 8 is a diagram showing a configuration in which the I / O cells are arranged so that the length direction of the I / O cells is parallel to the side of the chip. In FIG. 8, the same components as those of FIG. 6 are referred to by the same numerals, and a description thereof will be omitted. In FIG. 8, the plurality of I / O cells 32 are arranged so that the length direction thereof is parallel to the side of the semiconductor chip 30.

  FIG. 9 is an enlarged view of a portion A shown in FIG. As shown in FIG. 9, the I / O cell 32 is provided with a plurality of contact regions 36, and these contact regions 36 are electrically connected to power supply wirings 33 to 35. The I / O cell 32 receives the power supply voltage and the ground voltage from the power supply wirings 33 to 35 through the contact region 36. As shown in FIGS. 8 and 9, the I / O cell 32 is a substantially rectangular region, and the length direction (the direction in which the long side extends) is parallel to the side of the semiconductor chip 30, that is, the width. The direction (the direction in which the short side extends) is arranged to be perpendicular to the side of the semiconductor chip 30.

  The I / O cell 32 arranged as shown in FIGS. 6 and 7 and the I / O cell 32 arranged as shown in FIGS. 8 and 9 are I / O cells having the same design. That is, the power contact position (region) 36 between the I / O cell 32 and the power supply wires 33 to 35 shown in FIG. 7 is the power contact position (region) between the I / O cell 32 and the power supply wires 33 to 35 shown in FIG. ) 36. When attention is focused on one contact region 36, the target contact region 36 is connected to the same power supply wiring regardless of the layout of FIG. 7 or the layout of FIG.

  This will be described with reference to FIG. 5 as in the case of the prior art. In FIG. 5, it is assumed that the wiring 25 electrically connected to the diffusion layer 22 through the contact 24 is a power supply wiring. Further, it is assumed that the contact 24 is a contact provided at a position B shown in FIG. 7, for example. The I / O cell 32 in FIG. 7 and the I / O cell 32 in FIG. 9 are I / O cells having the same design, and the I / O cell in FIG. 9 corresponding to the position B in the I / O cell 32 in FIG. Since the contact position in the cell 32 is the position C, the contact at the position C in FIG. 9 is the contact 24 in FIG. In FIG. 7, the contact region 36 provided at the position B is connected to the power supply wiring 33, and in FIG. 9, the contact region 36 provided at the position C is connected to the power supply wiring 33. Therefore, the same circuit portion (the diffusion layer 22 to which the contact 24 in FIG. 5 is connected) of the I / O cell of the same design has the same power supply wiring (that is, the same wiring) in the arrangement of FIG. Power supply voltage).

  As described above, the I / O cell 32 has different contact positions connected to different power supply voltages so as not to be positioned on the same straight line in either the long side direction or the short side direction of the I / O cell 32. When the O cell 32 is designed, each contact can be appropriately connected to the power supply wiring extending in a straight line regardless of whether the I / O cell 32 is arranged vertically or horizontally. Accordingly, in the case where the vertical placement shown in FIGS. 6 and 7 and the horizontal placement shown in FIGS. 8 and 9 can be supported, and either one is appropriately selected and implemented, One I / O cell may be designed and prepared in common for the horizontal installation. This makes it possible to reduce design man-hours, that is, development costs, as compared to the case where individual I / O cells are designed and prepared as in the prior art.

  FIG. 10 is a diagram showing a modification of the configuration in which the I / O cells according to the embodiment of the present invention are arranged so that the length direction thereof is parallel to the side of the chip. In FIG. 10, the same components as those of FIG. 6 are referred to by the same numerals, and a description thereof will be omitted.

  A semiconductor chip 30A illustrated in FIG. 10 includes a core circuit 31, a plurality of I / O cells 32 disposed on the outer periphery of the chip, and power supply wirings 33 to 35. In the configuration shown in FIG. 10, the power supply wirings 33 to 35 are arranged in triplicate on the outer peripheral portion of the semiconductor chip 30A. That is, a first set of power supply wirings 33 to 35 is provided immediately outside the core circuit 31, a second set of power supply wirings 33 to 35 is provided immediately outside the core circuit 31, and the power supply wiring 33 is immediately further outside. A third set of thru 35 is provided.

  The plurality of I / O cells 32 are arranged such that the long side direction thereof is substantially parallel to the side of the semiconductor chip 30A, and the plurality of I / O cells 32 are arranged in a direction substantially perpendicular to the side of the semiconductor chip 30A. ing. That is, the I / O cells 32 are arranged in triplicate in a direction perpendicular to the side of the semiconductor chip 30A corresponding to each of the three sets of power supply wirings provided in triplicate.

  FIG. 11 is an enlarged view of a portion A shown in FIG. As shown in FIG. 11, each I / O cell 32 is provided with a plurality of contact regions 36, and these contact regions 36 are electrically connected to power supply wirings 33 to 35. Each I / O cell 32 receives the power supply voltage and the ground voltage from the power supply wirings 33 to 35 through the contact region 36. As described above, the I / O cells 32 are arranged in triplicate in a direction perpendicular to the side of the semiconductor chip corresponding to each of the three sets of power supply wirings provided in triplicate.

  10 and 11, the total of the lengths of the n short sides of the I / O cell 32 when the I / O cell 32 is arranged in n stages perpendicular to the side of the semiconductor chip is 1 If it is shorter than the length of the long side of one I / O cell 32, the chip size can be reduced as compared with the arrangement shown in FIG. That is, when the length of the short side of the I / O cell 32 is X and the length of the long side is Y, the I / O cell 32 is shown in FIGS. As shown in FIG. 11, by arranging a plurality of stages in a horizontal arrangement, the chip size can be reduced as compared with a vertical arrangement as shown in FIG.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a figure which shows the structure which has arrange | positioned the I / O cell so that the length direction of an I / O cell may become perpendicular | vertical to the edge | side of a chip | tip. It is a figure which expands and shows the part A shown in FIG. It is a figure which shows the structure which has arrange | positioned the I / O cell so that the length direction of an I / O cell may become parallel to the edge | side of a chip | tip. It is a figure which expands and shows the part A shown in FIG. It is a figure which shows an example of sectional drawing of the power supply contact arrangement | positioning of an I / O cell. It is a figure which shows the structure which has arrange | positioned the I / O cell by the Example of this invention so that the length direction may become perpendicular | vertical to the edge | side of a chip | tip. It is a figure which expands and shows the part A shown in FIG. It is a figure which shows the structure which has arrange | positioned the I / O cell so that the length direction of an I / O cell may become parallel to the edge | side of a chip | tip. It is a figure which expands and shows the part A shown in FIG. It is a figure which shows the modification of the structure which has arrange | positioned the I / O cell by the Example of this invention so that the length direction may become parallel to the edge | side of a chip | tip. It is a figure which expands and shows the part A shown in FIG.

Explanation of symbols

30 Semiconductor chip 31 Core circuit 32 I / O cells 33 to 35 Power supply wiring 36 Contact region

Claims (5)

The core circuit,
A plurality of power supply wirings for supplying a plurality of power supply voltages;
An I / O cell that is electrically connected to the plurality of power supply wirings via a plurality of contact positions and inputs / outputs a signal between the core circuit and the outside, and has a different power supply voltage among the plurality of contact positions. A semiconductor device, wherein different contact positions to be connected are arranged so as not to be positioned on the same straight line in any of the long side direction and the short side direction of the I / O cell.   2. The semiconductor device according to claim 1, wherein the plurality of contact positions are arranged in a substantially oblique line in the I / O cell.   The I / O cells are arranged such that a long side direction thereof is substantially parallel to a side of the chip of the semiconductor device, and a plurality of the I / O cells are arranged in a direction substantially perpendicular to the side of the chip of the semiconductor device. The semiconductor device according to claim 1. An I / O cell that is electrically connected to a plurality of power supply wirings via a plurality of contact positions and inputs / outputs signals between the core circuit and the outside,
Different contact positions connected to different power supply voltages among the plurality of contact positions are arranged so as not to be located on the same straight line in any of the long side direction and the short side direction of the I / O cell. Characteristic I / O cell.   5. The I / O cell according to claim 4, wherein the plurality of contact positions are arranged in a substantially oblique line in the I / O cell.

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