KR950003908B1 - Semiconductor lead frame - Google Patents

Semiconductor lead frame Download PDF

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Publication number
KR950003908B1
KR950003908B1 KR1019920002797A KR920002797A KR950003908B1 KR 950003908 B1 KR950003908 B1 KR 950003908B1 KR 1019920002797 A KR1019920002797 A KR 1019920002797A KR 920002797 A KR920002797 A KR 920002797A KR 950003908 B1 KR950003908 B1 KR 950003908B1
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South Korea
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semiconductor
chip
lead frame
lead
inner lead
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KR1019920002797A
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Korean (ko)
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KR930018703A (en
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오동렬
정현조
권홍규
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삼성전자 주식회사
김광호
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Priority to KR1019920002797A priority Critical patent/KR950003908B1/en
Priority to JP4306906A priority patent/JP2507855B2/en
Priority to US08/006,202 priority patent/US5250840A/en
Publication of KR930018703A publication Critical patent/KR930018703A/en
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Publication of KR950003908B1 publication Critical patent/KR950003908B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06156—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

The lead frame is used for a rectangular semiconductor chip which includes a number of bonding pads which enable external connection of circuits contained in the chip, and which are arranged in bands confined in central regions of the chip and extending in length and width directions of the chip at right angles to one another to form a cross arrangement of the pads. The lead frame includes a number of leads with inner and outer ends, a number of bus bars, and an insulator to electrically insulating the chips and the leads. A number of metal wires respectively electrically connect the inner ends of the leads to selected bonding pads, and the bus bars in common to other selected bonding pads.

Description

반도체 리드 프레임Semiconductor leadframe

제1도는 종래의 LOC용 리드 프레임의 평면도이고,1 is a plan view of a conventional lead frame for LOC,

제2도는 이 발명에 따른 LOC용 리드 프레임의 평면도이다.2 is a plan view of a lead frame for LOC according to the present invention.

이 발명은 반도체 리드 프레임에 관한 것으로, 특히 십자형으로 배열 형성된 칩 본딩 패드를 이용하여 디바이스의 신뢰성 향상 및 특성을 개선할 수 있는 반도체 리드 프레임에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor lead frame, and more particularly, to a semiconductor lead frame capable of improving reliability and characteristics of a device by using a chip bonding pad arranged in a cross shape.

현재 반도체 소자는 대형화, 다기능화, 고집적화를 꾸준히 하고 있다. 따라서 이것을 탑재하는 리드 프레임은 한층 더 다핀화가 요구되고 있다. 그리고 일반적으로 반도체 패키징 기술은 리드 프레임의 다이패드에 에폭시등의 접착제 물질을 도포한 후 반도체 칩을 탑재하는 방법이 이용되었다.At present, semiconductor devices have been steadily becoming larger, more versatile, and more highly integrated. Therefore, the lead frame in which this is mounted is required to be more pinned. In general, the semiconductor packaging technology is a method of mounting a semiconductor chip after applying an adhesive material such as epoxy to the die pad of the lead frame.

그러나 근래에 와서는 반도체 패키지를 더욱 소형화하기 위하여 다이패드를 제거하고 칩위에 리드를 직접 부착할 수 있는 즉 다이패드가 없는 칩 온리드(Chip on Lead; 이하 COL이라 한다)나 리드 온 칩(Lead on Chip; 이하 LOC라 한다)용 리드 프레임을 사용하고 있다. 이를테면 다이패드로 인한 반도체 신뢰성 문제 및 패키지 디자인의 제약으로 COL 또는 LOC용 리드 프레임을 사용하고 있다.However, in recent years, in order to further miniaturize the semiconductor package, a chip on lead (hereinafter referred to as COL) or a lead on chip (ie, COL) without a die pad can be removed and a lead can be directly attached onto the chip. lead chip for on chip (hereinafter referred to as LOC). For example, lead frames for COL or LOC are used due to the problems of semiconductor reliability and package design due to die pads.

나아가서는 다양화되는 패키지로의 전개상 LOC는 칩의 패드 위치 변경을 필요로하지 않는다는 이점이 있다. 또 다품종 패키지로 양산성을 유지하면서 전개하기 위해서는 칩의 패드 위치를 품종별로 변경시키지 않고 대응할 수 있는 LOC가 유리하다.Further, the advantage of LOC in deployment to a diversified package is that it does not require changing the pad position of the chip. In addition, LOC that can respond without changing the pad position of the chip for varieties while maintaining mass production in a multi-variety package is advantageous.

이와 같은 LOC용 리드 프레임에 있어서 종래 칩 본딩 패드가 일자형으로 배열된 LOC용 리드 프레임은 제1도에 도시한 바와 같이, 주변에 회로 및 여러개의 외부단자가 형성된 사각형상의 반도체 칩(10)와, 중간부분이 돌출된 형태이며 폭이 가늘고 간격의 폭이 넓게 형성된 내부리드(12)와, 상기 내부리드(12)와 접속되어 있으며 내부리드부(12)에서 멀어지는 방향으로 연장하는 외부리드부(14)로 되는 여러개의 리드(16)와, 상기 리드(16)의 주위에 형성된 버스바(24)와, 상기 반도체 칩(10)과 내부리드부(12) 사이에 개재해서 전기적으로 절연하기 위한 적어도 1개의 절연체(18)와, 상기 외부단자와 내부리드를 전기적으로 접속하기 위한 금속 와이어(20)와, 내부리드부(14)의 끝단으로부터 근접된 접속하기 위한 금속 와이어(20)와, 내부리드부(14)의 끝단으로부터 근접된 부분 즉 반도체 칩(10)의 중앙부에 일자형으로 배열 형성된 칩의 본딩 패드(22)와, 내부리드부(12)를 지지하는 지지내(Support Bar)(26)로 구성되었다.In the LOC lead frame, the LOC lead frame in which the conventional chip bonding pads are arranged in a straight line has a rectangular semiconductor chip 10 having a circuit and a plurality of external terminals formed therein, as shown in FIG. An inner lead 12 having a middle portion protruding in shape and having a narrow width and a wide interval therebetween, and an outer lead portion 14 connected to the inner lead 12 and extending in a direction away from the inner lead portion 12. At least for electrically insulated between a plurality of leads 16, the bus bars 24 formed around the leads 16, and the semiconductor chip 10 and the internal lead portion 12, respectively. One insulator 18, a metal wire 20 for electrically connecting the external terminal and the inner lead, a metal wire 20 for connecting close to the end of the inner lead portion 14, and an inner lead. Proximate from the end of section 14 Part of the semiconductor chip 10 is composed of a bonding pad 22 of the chip arranged in a straight line and a support bar 26 for supporting the inner lead portion 12.

그러나 이와 같이 구성된 반도체 리드 프레임(30)은 로우 핀 카운트(Low pin count) 패키지에 적용할 때에는 어려운 문제점이 없으나 다 핀 카운트(High pin count) 패키지에 적용할 때는 칩의 크기가 상대적으로 커져야 하는 문제점이 있었다. 따라서 칩 크기의 증대에 따른 코스트(cost) 몇 디바이스(Device)의 특성이 좋지않게 되는 문제점이 있었다.However, the semiconductor lead frame 30 configured as described above does not have a difficult problem when applied to a low pin count package, but when applied to a high pin count package, a chip size must be relatively large. There was this. Therefore, there is a problem in that the characteristics of some devices are not good due to the increase in chip size.

이 발명의 목적은 상기 설명한 종래 기술의 문제점을 극복하기 위하여 십자형으로 배열 형성된 칩 본딩 패드를 이용함으로서 반도체 조립 공정에서 신뢰성 향상 및 디바이스의 특성을 개선시킬 수 있는 반도체 리드 프레임을 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor lead frame capable of improving reliability and device characteristics in a semiconductor assembly process by using chip bonding pads formed in a cross shape to overcome the problems of the prior art described above.

이 발명의 목적은 리드 프레임의 설계 및 칩 본딩 패드의 배열 자유도를 증대시킬 수 있는 반도체 리드 프레임을 제공하는 것이다. 이 발명의 다른 목적은 버스바를 다수개까지 자유롭게 설계할 수 있는 반도체 리드 프레임을 제공하는 것이다.An object of the present invention is to provide a semiconductor lead frame capable of increasing the design of the lead frame and the degree of freedom of arrangement of the chip bonding pads. Another object of the present invention is to provide a semiconductor lead frame in which a plurality of busbars can be freely designed.

이 발명에 따른 반도체 리드 프레임은 주변에 회로 및 여러개의 외부단자가 형성된 사각형상의 반도체 칩과, 내부리드부와 상기 내부리드부와 접촉되어 있으며 내부리드에서 멀어지는 방향으로 연장하는 외부리드부로 되는 여러개의 리드와, 상기 리드의 주위에 형성된 버스바와 상기 반도체 칩과 내부리드부 사이에 개재해서 전기적으로 절연화하기 위한 적어도 1개의 절연체와, 상기 외부단자와 내부리드를 전기적으로 접속하기 위한 금속 와이어를 포함하는 반도체 리드 프레임으로서 상기 외부단자와 내부리드를 전기적으로 접속하기 위하여 다수개의 칩 본딩 패드를 십자형으로 배열 형성시킨 십자형태의 칩 본딩 패드를 구비한다. 또한, 이 발명의 반도체 리드 프레임은 십자형태로 배열 형성된 칩 본딩 패드를 사용할때 최대한 많은 핀의 배열이 가능하며, 또 버스바를 다수개 설계할 수 있다.The semiconductor lead frame according to the present invention includes a rectangular semiconductor chip having a circuit and a plurality of external terminals formed therein, and an outer lead portion which is in contact with the inner lead portion and the inner lead portion and extends in a direction away from the inner lead. A lead, a bus bar formed around the lead, at least one insulator for electrically insulating between the semiconductor chip and the inner lead portion, and a metal wire for electrically connecting the outer terminal and the inner lead; A semiconductor lead frame includes a cross-shaped chip bonding pad in which a plurality of chip bonding pads are arranged in a cross shape to electrically connect the external terminal and the inner lead. In addition, the semiconductor lead frame of the present invention is capable of arranging as many pins as possible using a chip bonding pad formed in a cross shape, and designing a plurality of busbars.

이와 같이 구성된 이 발명의 반도체 리드 프레임을 첨부된 도면과 관련하여 상세히 설명하면 다음과 같다.The semiconductor lead frame of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

제2도는 이 발명에 따른 반도체 리드 프레임의 평면도이다.2 is a plan view of a semiconductor lead frame according to the present invention.

반도체 리드 프레임(60)은 최대한 많은 핀의 배열이 가능할 수 있도록 십자형태의 칩 본딩 패드(52)를 구비하게 된다. 상기 칩 본딩 패드(52)는 일정한 간격으로 배치되지만 사용자의 사용목적에 따라서 예정된 간격으로 배열할 수 있다. 또한 반도체 리드 프레임(60)은 30°~60°정도 경사지게 형성된 내부리드부(42)를 구비한다. 또한 반도체 리드 프레임(60)은 사용자의 의도에 따라서 저항이 감소되는 효과를 크게하기 위해 사용되는 버스바(54)를 2개에서 4개 정도까지 자유롭게 설계할 수 있다.The semiconductor lead frame 60 is provided with a cross-shaped chip bonding pad 52 to enable the arrangement of as many pins as possible. The chip bonding pads 52 are arranged at regular intervals, but may be arranged at predetermined intervals according to a user's purpose of use. In addition, the semiconductor lead frame 60 includes an inner lead portion 42 formed to be inclined by about 30 ° to about 60 °. In addition, the semiconductor lead frame 60 may freely design two to four bus bars 54 which are used to increase the effect of reducing resistance according to a user's intention.

이와 같이 구성된 반도체 리드 프레임(60)은 내부리드부(42)의 끝단과 십자형으로 배열 형성된 칩 본딩패드(52)를 전기적으로 접속하기 위해 금속 와이어(50)로 와이어 본딩할 수 있다. 또한 리드(46)의 주위에 형성된 버스바(54)와 십자형으로 배열 형성된 칩 본딩 패드(52)를 전기적으로 접속하는 와이어 본딩을 할 수 있다. 따라서 반도체 칩(40)과 리드(46)의 와이어 본딩 부위가 증가하게 됨으로써 와이어 본딩부의 선택이 자유롭게 된다. 또한 패키지의 고집적화 및 고용량화를 실현할 수 있다.The semiconductor lead frame 60 configured as described above may be wire-bonded with the metal wire 50 to electrically connect the chip bonding pads 52 formed in a cross shape with the ends of the inner lead portion 42. Moreover, the wire bonding which electrically connects the bus bar 54 formed around the lead 46 and the chip bonding pad 52 formed in the cross shape in the cross shape can be performed. Therefore, the wire bonding portion of the semiconductor chip 40 and the lead 46 is increased to freely select the wire bonding portion. In addition, high integration and high capacity of the package can be realized.

이 발명에 의한 반도체 리드 프레임에 의하면 상술한 바와 같이 최근의 고집적화되어 있는 반도체 소자에 대응하여 다핀의 반도체 장치를 용이하게 형성할 수 있다. 또한 이 발명은 동일한 칩의 크기로 다핀화 LOC가 가능하며 본딩 패드의 배열 자유도가 증대되고, 패드까지의 배선의 길이를 짧게할 수 있으므로 디바이스의 노이즈(noise) 감소 및 특성을 개선할 수 있는 효과가 있다. 또한 버스바를 2개에서 4개까지 설치할 수 있으므로 버스바 설계의 자유도가 증대되는 효과가 있다. 또한 반도체 장치의 동작성에 관해서 더한 층 신뢰성을 높일 수 있다.According to the semiconductor lead frame according to the present invention, as described above, a multi-pin semiconductor device can be easily formed in response to the recent highly integrated semiconductor elements. In addition, the present invention is capable of multi-pinning LOC with the same chip size, increases the degree of freedom in the arrangement of bonding pads, and shortens the length of wiring to the pads, thereby reducing noise and improving characteristics of the device. There is. In addition, two to four busbars can be installed, which increases the degree of freedom in busbar design. In addition, the layer reliability can be improved with respect to the operability of the semiconductor device.

Claims (3)

주변에 회로 및 여러개의 외부단자가 형성된 사각형상의 반도체 칩과, 내부리드부와 상기 내부리드부와 접속되어 있으며 내부리드에서 멀어지는 방향으로 연장하는 외부리드부로 되는 여러개의 리드와, 상기 리드의 주위에 형성된 버스바와, 상기 반도체 칩과 내부리드 사이에 개재해서 전기적으로 절연하기 위한 적어도 1개의 절연체와, 상기 외부단자와 내부리드를 전기적으로 접속하기 위한 금속와이어를 포함하는 반도체 리드 프레임으로서, 상기 외부단자와 내부리드를 전기적으로 접속하기 위하여 다수개의 칩 본딩 패드를 십자형으로 배열 형성시킨 십자형태의 칩 본딩 패드를 구비한 반도체 리드 프레임.A plurality of leads including a rectangular semiconductor chip having a circuit and a plurality of external terminals formed therein, an inner lead portion and an outer lead portion connected to the inner lead portion and extending away from the inner lead, and around the lead A semiconductor lead frame comprising a formed bus bar, at least one insulator for electrically insulating between the semiconductor chip and an inner lead, and a metal wire for electrically connecting the outer terminal and the inner lead, wherein the outer terminal And a cross-shaped chip bonding pad in which a plurality of chip bonding pads are arranged in a cross shape in order to electrically connect the internal leads to the internal leads. 제1항에 있어서, 상기 내부리드부는 30~60°정도 경사지게 형성할 수 있도록 한 반도체 리드 프레임.The semiconductor lead frame of claim 1, wherein the inner lead part is formed to be inclined by about 30 ° to about 60 °. 제1항에 있어서, 상기 버스바는 2개에서 4개 정도까지 설치할 수 있도록 한 반도체 리드 프레임.The semiconductor lead frame according to claim 1, wherein the bus bars can be installed in two to four pieces.
KR1019920002797A 1992-02-24 1992-02-24 Semiconductor lead frame KR950003908B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019920002797A KR950003908B1 (en) 1992-02-24 1992-02-24 Semiconductor lead frame
JP4306906A JP2507855B2 (en) 1992-02-24 1992-11-17 Semiconductor device
US08/006,202 US5250840A (en) 1992-02-24 1993-01-19 Semiconductor lead frame with a chip having bonding pads in a cross arrangement

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Application Number Priority Date Filing Date Title
KR1019920002797A KR950003908B1 (en) 1992-02-24 1992-02-24 Semiconductor lead frame

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KR950003908B1 true KR950003908B1 (en) 1995-04-20

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KR100708046B1 (en) * 2001-10-23 2007-04-16 앰코 테크놀로지 코리아 주식회사 Substrate for semiconductor package

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