JPH05283592A - Semiconductor lead frame - Google Patents
Semiconductor lead frameInfo
- Publication number
- JPH05283592A JPH05283592A JP4306906A JP30690692A JPH05283592A JP H05283592 A JPH05283592 A JP H05283592A JP 4306906 A JP4306906 A JP 4306906A JP 30690692 A JP30690692 A JP 30690692A JP H05283592 A JPH05283592 A JP H05283592A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor
- chip
- lead frame
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
- H01L2224/06156—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体リードフレー
ムに関し、特に十字形に配列形成されたチップのボンデ
ィングパッドを利用して、デバイスの信頼性向上及び特
性を改善することのできる半導体リードフレームに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor lead frame, and more particularly to a semiconductor lead frame which can improve the reliability and characteristics of a device by utilizing bonding pads of chips arranged in a cross shape. .
【０００２】[0002]
【従来の技術】現在、半導体素子は小形化、多機能化、
高集積化が進められている。従って、これを搭載するリ
ードフレームはさらに多ピン化が要求されている。そし
て、一般に半導体パッケージング技術は、リードフレー
ムのダイパッドにエポキシなどの接着剤物質を塗布した
後、半導体チップを搭載する方法が利用されている。2. Description of the Related Art Currently, semiconductor devices are becoming smaller and more multifunctional.
High integration is being promoted. Therefore, the lead frame mounting the same is required to have more pins. In general, the semiconductor packaging technique uses a method of mounting a semiconductor chip after applying an adhesive substance such as epoxy to a die pad of a lead frame.
【０００３】しかし、半導体パッケージをさらに小形化
するためダイパッドを除去し、チップ上にリードを直接
接続することのできる、即ちダイパッドを使用しないチ
ップオンリード（Chip on Lead；以下ＣＯＬという）や
リードオンチップ（Lead onChip；以下ＬＯＣという）
用リードフレームを使用している。例えば、ダイパッド
による半導体信頼性問題及びパッケージデザインの制約
で、ＣＯＬあるいはＬＯＣ用リードフレームを使用して
いる。上記ＬＯＣは半導体パッケージの多様な種類に対
応して予定された位置に対するチップのパッド位置を変
更する必要がない利点がある。However, in order to further miniaturize the semiconductor package, the die pad can be removed and the leads can be directly connected to the chip, that is, a chip on lead (hereinafter referred to as COL) or a lead on chip without using the die pad. (Lead on Chip; hereinafter referred to as LOC)
I am using a lead frame for. For example, a COL or LOC lead frame is used because of semiconductor reliability issues due to die pads and package design constraints. The LOC has an advantage in that it is not necessary to change the pad position of the chip with respect to a predetermined position corresponding to various types of semiconductor packages.
【０００４】このようなＬＯＣ用リードフレームにおい
て、従来チップボンディングパッドが一字形に配列され
たＬＯＣ用リードフレームは、図２に示したごとく、周
辺に回路及び多数個の外部端子が形成された四角形状の
半導体チップ１０と、中間部分が突出された形態であ
り、幅が狭く間隔の幅が広く形成された内部リード１２
と、上記内部リード１２と接続されており内部リード１
２から外側へ延長された外部リード１４とからなる多数
個のリード１６と、上記リード１６の周囲に形成された
バスバー２４と、上記半導体チップ１０と内部リード１
２間に配置して電気的に絶縁するための少なくとも１個
の絶縁体１８と、上記外部端子と内部リードを電気的に
接続するための金属ワイヤ２０と、内部リード１４の終
端に位置するように半導体チップ１０の中央部に一字形
に配列形成されたチップのボンディングパッド２２と、
内部リード１２を支持する支持台２６とから構成されて
いた。In such a LOC lead frame in which chip bonding pads are arranged in a single letter shape, a conventional LOC lead frame has a rectangular shape in which circuits and a large number of external terminals are formed in the periphery, as shown in FIG. -Shaped semiconductor chip 10 and internal lead 12 having a shape in which a middle portion is protruded and a width of which is narrow and which is wide.
And the internal lead 1 connected to the internal lead 12 described above.
2. A large number of leads 16 each including an outer lead 14 extending outward from the lead wire 2, a bus bar 24 formed around the lead 16, the semiconductor chip 10 and the inner lead 1.
At least one insulator 18 disposed between the two to electrically insulate, a metal wire 20 for electrically connecting the external terminal and the inner lead, and an end of the inner lead 14. Chip bonding pads 22 arranged in a line in the center of the semiconductor chip 10, and
It was composed of a support base 26 that supports the inner leads 12.
【０００５】しかしこのように構成された半導体リード
フレームは、ロウピンカウントパッケージに適用する時
には問題点はないが、多ピンカウント（High pin coun
t）パッケージに適用する時はチップの大きさを相対的
に大きくしなければならないという問題点があった。従
って、チップの大きさの増大によるコスト及びデバイス
の特性が良いなくなるという問題点があった。However, the semiconductor lead frame having such a structure has no problem when it is applied to a low pin count package.
t) When applied to a package, there was a problem that the size of the chip had to be relatively large. Therefore, there is a problem that the cost and device characteristics are deteriorated due to the increase of the chip size.
【０００６】[0006]
【発明が解決しようとする課題】この発明の目的は、上
記従来技術の問題点を克服するため、十字形に配列形成
されたチップボンディングパッドを利用することによ
り、半導体組立工程の信頼性向上及びデバイスの特性を
改善させることのできる半導体リードフレームを提供す
るものである。SUMMARY OF THE INVENTION An object of the present invention is to improve the reliability of a semiconductor assembly process by using chip bonding pads arranged in a cross shape in order to overcome the problems of the prior art. Provided is a semiconductor lead frame capable of improving device characteristics.
【０００７】また、この発明の他の目的は、リードフレ
ームの設計及びチップボンディングパッドの配列自由度
を増大させることのできる半導体リードフレームを提供
するものである。Another object of the present invention is to provide a semiconductor lead frame capable of increasing the degree of freedom in designing the lead frame and arranging the chip bonding pads.
【０００８】さらに、この発明の他の目的は、バスバー
を多数個まで自由に設計することのできる半導体リード
フレームを提供するものである。Further, another object of the present invention is to provide a semiconductor lead frame in which a large number of bus bars can be freely designed.
【０００９】[0009]
【課題を解決するための手段】この発明による半導体リ
ードフレームは、周辺に回路及び複数の外部端子が形成
された四角形状の半導体チップと、内部リード部と上記
内部リード部と接続されており内部リードから延長形成
された外部リード部とからなる多数個のリードと、上記
リードの周囲に形成されたバスバーと、上記半導体チッ
プと内部リード間に配置して電気的に絶縁するための少
なくとも１個の絶縁体と、上記外部端子と内部リードを
電気的に接続するための金属ワイヤを含む半導体リード
フレームであって、上記外部端子と内部リードを電気的
に接続するため多数個のチップボンディングパッドを十
字形に配列形成した十字形態のチップボンディングパッ
ドを備えて構成される。A semiconductor lead frame according to the present invention has a rectangular semiconductor chip having a circuit and a plurality of external terminals formed on the periphery thereof, an internal lead portion and the internal lead portion, which are connected to each other. A large number of leads each including an external lead part extended from the lead, a bus bar formed around the lead, and at least one for electrically insulating the semiconductor chip from the internal lead. A semiconductor lead frame including an insulator and a metal wire for electrically connecting the external terminal and the internal lead, and a plurality of chip bonding pads for electrically connecting the external terminal and the internal lead. The cross-shaped chip bonding pads are arranged in a cross shape.
【００１０】[0010]
【実施例】この発明の半導体リードフレームを添付され
た図面により詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor lead frame of the present invention will be described in detail with reference to the accompanying drawings.
【００１１】図１はこの発明による半導体リードフレー
ムの平面図である。図１において、半導体リードフレー
ム６０は、多くのピンが配列可能となるように十字形態
のチップボンディングパッド５２を備えている。上記チ
ップボンディングパッド５２は一定の間隔で配置されて
使用者の使用目的に応じて予定された間隔で配列するこ
とができる。また、半導体リードフレーム６０は３０°
〜６０°程度に傾斜するように形成された内部リード部
４２を備えている。さらに、半導体リードフレーム６０
は使用者の意図により抵抗が削減される効果を大きくす
るため、使用されるバスバー５４を２個から４個程度ま
で自由に設計することができる。FIG. 1 is a plan view of a semiconductor lead frame according to the present invention. In FIG. 1, the semiconductor lead frame 60 is provided with a cross-shaped chip bonding pad 52 so that many pins can be arranged. The chip bonding pads 52 may be arranged at regular intervals and may be arranged at predetermined intervals according to the purpose of use of the user. Also, the semiconductor lead frame 60 is 30 °
The inner lead portion 42 is formed so as to be inclined at about 60 °. Further, the semiconductor lead frame 60
Since the effect of reducing the resistance is increased according to the intention of the user, the number of bus bars 54 to be used can be freely designed from 2 to 4.
【００１２】このように構成された半導体リードフレー
ム６０は、内部リード部４２の終端と十字形に配列形成
されたチップボンディングパッド５２を電気的に接続す
るため、金属ワイヤ５０でワイヤボンディングすること
ができる。また、リード４６の周囲に形成されたバスバ
ー５４と十字形に配列形成されたチップボンディングパ
ッド５２を電気的に接続するワイヤボンディングをする
ことができる。The semiconductor lead frame 60 having the above-described structure electrically connects the terminal ends of the inner lead portions 42 and the chip bonding pads 52 arranged in a cross shape, and therefore can be wire-bonded with the metal wires 50. it can. Further, it is possible to perform wire bonding for electrically connecting the bus bar 54 formed around the lead 46 and the chip bonding pad 52 formed in a cross shape.
【００１３】従って、半導体チップ４０とリード４６の
ワイヤボンディング部位が増加するようになることによ
り、ワイヤボンディング部の選択が自由になる。かつ、
パッケージの高集積化及び高容量化を実現することがで
きる。この発明による半導体リードフレームによれば、
上述のように最近の高集積化されている半導体素子に対
応して多ピンの半導体装置を容易に形成するものであ
る。Therefore, the number of wire bonding portions of the semiconductor chip 40 and the lead 46 is increased, so that the wire bonding portion can be freely selected. And,
It is possible to realize high integration and high capacity of the package. According to the semiconductor lead frame of the present invention,
As described above, a multi-pin semiconductor device can be easily formed corresponding to the recent highly integrated semiconductor element.
【００１４】[0014]
【発明の効果】この発明は、同一なチップの大きさで多
ピン化のＬＯＣが可能となり、ボンディングパッドの配
列自由度が増大され、パッドまでの配線の長さを短くす
ることができるので、デバイスのノイズ減少及び特性を
改善することのできる効果がある。かつ、バスバーを２
個から４個まで設置することができるので、バスバー設
計の自由度が増大される効果がある。さらに、半導体装
置の動作特性に関してさらに信頼性を高めることができ
る。As described above, according to the present invention, the LOC with a large number of pins can be realized with the same chip size, the degree of freedom in arranging the bonding pads can be increased, and the length of the wiring up to the pads can be shortened. There is an effect that noise reduction and characteristics of the device can be improved. And two busbars
Since it is possible to install from four to four, there is an effect that the degree of freedom in designing the bus bar is increased. Furthermore, the reliability of the operating characteristics of the semiconductor device can be further improved.
【図１】この発明によるＬＯＣ用リードフレームの望ま
しい一実施例を図示した平面図である。FIG. 1 is a plan view showing a preferred embodiment of a lead frame for LOC according to the present invention.
【図２】従来のＬＯＣ用リードフレームの平面図であ
る。FIG. 2 is a plan view of a conventional LOC lead frame.
４０ 半導体チップ ４２ 内部リード部 ４４ 外部リード ４６ リード ４８ 絶縁体 ５０ 金属ワイヤ ５２ チップボンディングパッド ５４ バスバー ６０ 半導体リードフレーム 40 Semiconductor Chip 42 Internal Lead Part 44 External Lead 46 Lead 48 Insulator 50 Metal Wire 52 Chip Bonding Pad 54 Bus Bar 60 Semiconductor Lead Frame
Claims (4)
れた四角形状の半導体チップと、 内部リード及び内部リードから延長形成された外部リー
ドを持つ複数個のリードと、 上記複数個のリードの周囲に形成されたバスバーと、 電気的に絶縁するために半導体チップと内部リード間に
配置された最小１つの絶縁体と、 上記外部リードと内部リードを電気的に接続するための
金属ワイヤを含む半導体リードフレームであって、 上記外部リードと内部リードを電気的に接続するため多
数個のチップボンディングパッドを十字形に配列形成し
た十字形態のチップボンディングパッドを備えたことを
特徴とする半導体リードフレーム。1. A rectangular semiconductor chip having a circuit and a plurality of external terminals provided on the periphery thereof, a plurality of leads having an inner lead and an outer lead extended from the inner lead, and a plurality of leads of the plurality of leads. A bus bar formed around the semiconductor chip, at least one insulator disposed between the semiconductor chip and the inner lead for electrical insulation, and a metal wire for electrically connecting the outer lead and the inner lead A semiconductor lead frame, comprising: a cross-shaped chip bonding pad in which a large number of chip bonding pads are arranged in a cross shape for electrically connecting the external lead and the internal lead. .
囲で傾斜するように形成されたことを特徴とする請求項
１記載の半導体リードフレーム。2. The semiconductor lead frame according to claim 1, wherein the inner lead is formed so as to be inclined in a range of 30 ° to 60 °.
設けることを特徴とする請求項１記載の半導体リードフ
レーム。3. The semiconductor lead frame according to claim 1, wherein the bus bar is provided in a minimum number of 2 to 4.
きさを最小化するために予定されたチップに対応して適
切な大きさを持つようにしたことを特徴とする請求項１
記載の半導体リードフレーム。4. The bonding pad has an appropriate size corresponding to a chip designed to minimize the size of the chip.
The semiconductor lead frame described.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1992-2797 | 1992-02-24 | ||
| KR1019920002797A KR950003908B1 (en) | 1992-02-24 | 1992-02-24 | Semiconductor lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05283592A true JPH05283592A (en) | 1993-10-29 |
| JP2507855B2 JP2507855B2 (en) | 1996-06-19 |
Family
ID=19329409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4306906A Expired - Fee Related JP2507855B2 (en) | 1992-02-24 | 1992-11-17 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2507855B2 (en) |
| KR (1) | KR950003908B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100708046B1 (en) * | 2001-10-23 | 2007-04-16 | 앰코 테크놀로지 코리아 주식회사 | Substrate for semiconductor package |
-
1992
- 1992-02-24 KR KR1019920002797A patent/KR950003908B1/en not_active IP Right Cessation
- 1992-11-17 JP JP4306906A patent/JP2507855B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR950003908B1 (en) | 1995-04-20 |
| JP2507855B2 (en) | 1996-06-19 |
| KR930018703A (en) | 1993-09-22 |
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