JP2685135B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2685135B2 JP2685135B2 JP1006563A JP656389A JP2685135B2 JP 2685135 B2 JP2685135 B2 JP 2685135B2 JP 1006563 A JP1006563 A JP 1006563A JP 656389 A JP656389 A JP 656389A JP 2685135 B2 JP2685135 B2 JP 2685135B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- power supply
- ground wiring
- ground
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 ［概要］ 半導体集積回路の電源及びグランドの配線構造に関
し、 電源配線及びグランド配線の線幅を大きくすることな
くそれらの経時断線を防止し、かつグリッチによる内部
回路の誤動作を防止することを目的とし、 チップ外周部に沿って多数設けられるパッドに沿って
電源配線及びグランド配線を配設し、その電源配線及び
グランド配線は一部に高抵抗部を介在させて環状に配設
して構成する。The present invention relates to a wiring structure of a power supply and a ground of a semiconductor integrated circuit, prevents the power supply wiring and the ground wiring from being disconnected over time without increasing the line width, and malfunctions of an internal circuit due to glitches. In order to prevent this, the power supply wiring and ground wiring are arranged along a number of pads provided along the outer periphery of the chip, and the power supply wiring and ground wiring are formed in an annular shape with a high resistance part interposed in part. Arrange and configure.
［産業上の利用分野］ この発明は半導体集積回路の電源及びグランドの配線
構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply and ground wiring structure of a semiconductor integrated circuit.
半導体集積回路ではそのチップの周囲にボンディング
ワイヤを接続するための多数のパッドが形成され、その
パッドの外側及び内側に電源配線及びグランド配線が設
けられ、各パッドの近傍に設けられるバッファ回路に各
配線がそれぞれ接続されている。そして、近年の集積回
路の高集積化の要請にともないその電源配線及びグラン
ド配線の線幅を益々細くする必要がある。In a semiconductor integrated circuit, a large number of pads for connecting bonding wires are formed around the chip, power supply wiring and ground wiring are provided on the outside and inside of the pads, and a buffer circuit provided near each pad The wiring is connected respectively. With the recent demand for higher integration of integrated circuits, it is necessary to make the line widths of the power supply wiring and the ground wiring even smaller.
［従来の技術］ 従来、半導体集積回路では第６図に示すようにチップ
１の周囲に多数のパッド２が形成され、そのパッド２の
外側には電源配線３が形成されるとともに内側にはグラ
ンド配線４が形成され、これらの配線はアルミニウムで
形成されている。その電源配線３はパッド部3aから両側
へ各パッド２を取囲むように対称状に延設され、その先
端部は開口部3bを隔てて対向している。また、グランド
配線４は電源配線３の開口部3bにパッド部4aが形成され
るとともに、そのパッド部4aから両側へ各パッド２の内
側に沿って延設され、その先端部は開口部4bを隔てて対
向している。[Prior Art] Conventionally, in a semiconductor integrated circuit, a large number of pads 2 are formed around a chip 1 as shown in FIG. 6, a power supply wiring 3 is formed outside the pads 2, and a ground is formed inside the pads. Wirings 4 are formed, and these wirings are made of aluminum. The power supply wiring 3 is symmetrically extended from the pad portion 3a to both sides so as to surround each pad 2, and the tip ends thereof face each other with an opening 3b therebetween. Further, the ground wiring 4 has a pad portion 4a formed in the opening 3b of the power supply wiring 3 and extends from the pad portion 4a to both sides along the inside of each pad 2, and the tip portion thereof has the opening 4b. Opposite each other.
そして、各パッド２近傍にそれぞれ設けられるバッフ
ァ回路（図示しない）は各配線3,4にそれぞれ接続され
て電源電圧が供給されるとともに、グランド配線４内側
の内部回路５への電源供給は電源配線３のパッド部3aか
らグランド配線４の開口部4bを経て内部回路５に接続さ
れる内部配線3cにより供給される。A buffer circuit (not shown) provided in the vicinity of each pad 2 is connected to each wiring 3 and 4 to be supplied with a power supply voltage, and power is supplied to the internal circuit 5 inside the ground wiring 4 It is supplied by the internal wiring 3c connected to the internal circuit 5 from the pad portion 3a of 3 through the opening 4b of the ground wiring 4.
［発明が解決しようとする課題］ 上記のような構成の半導体集積回路では各パッドに接
続されるバッファ回路のノイズによる干渉を防止するた
めに、電源配線３及びグランド配線４のパッド部3a,4a
を中心として一側に位置するパッド２には入力バッファ
回路を接続し、他側に位置するパッド２には出力バッフ
ァ回路を接続するようにしてる。[Problems to be Solved by the Invention] In the semiconductor integrated circuit configured as described above, in order to prevent interference due to noise of the buffer circuit connected to each pad, the pad portions 3a and 4a of the power supply wiring 3 and the ground wiring 4 are prevented.
The input buffer circuit is connected to the pad 2 located on one side with respect to the center, and the output buffer circuit is connected to the pad 2 located on the other side.
ところが、このような構成では多数の出力バッファ回
路あるいは入力バッファ回路が同時に動作するような場
合にはパッド部3a,4aに対し一側のみの電源配線３及び
グランド配線４の電流密度が高くなり、このような動作
を繰返すと電源配線３及びグランド配線４が経時劣化に
より断線することがある。そこで、このような断線を防
止するために電源配線３及びグランド配線３の線幅を大
きくすると、集積度が低下するという問題点がある。However, in such a configuration, when a large number of output buffer circuits or input buffer circuits operate simultaneously, the current density of the power supply wiring 3 and the ground wiring 4 on only one side with respect to the pad portions 3a, 4a becomes high, If such an operation is repeated, the power supply wiring 3 and the ground wiring 4 may be disconnected due to deterioration over time. Therefore, if the line widths of the power supply wiring 3 and the ground wiring 3 are increased in order to prevent such disconnection, there is a problem that the degree of integration is reduced.
また、多数の出力バッファ回路あるいは入力バッファ
回路が同時に動作して、第４図に鎖線で示すようなピー
ク値の高い負荷電流I2がグランド配線４に流れ込む場合
には、同グランド配線４の電位が一時的に上昇して内部
回路５のグランドにグリッチを発生させ、そのグリッチ
により内部回路５が誤動作することがあった。Further, when a large number of output buffer circuits or input buffer circuits operate simultaneously and a load current I2 having a high peak value as shown by the chain line in FIG. 4 flows into the ground wiring 4, the potential of the ground wiring 4 is There is a case that the internal circuit 5 malfunctions due to the glitch caused by the temporary rise to generate a glitch in the ground of the internal circuit 5.
この発明の目的は、電源配線及びグランド配線の線幅
を大きくすることなくそれらの経時断線を防止し、かつ
グリッチによる内部回路の誤動作を防止可能とする半導
体集積回路を提供するにある。An object of the present invention is to provide a semiconductor integrated circuit capable of preventing the power supply wiring and the ground wiring from being disconnected over time without increasing the line width and preventing malfunction of the internal circuit due to glitches.
［課題を解決するための手段］ 第１図は本発明の原理説明図である。すなわち、電源
配線３及びグランド配線４はチップ１外周部に沿って多
数設けられるパッド２に沿って配設され、その電源配線
３及びグランド配線４は一部に高抵抗部13を介在させて
環状に配設されている。[Means for Solving the Problems] FIG. 1 is an explanatory view of the principle of the present invention. That is, the power supply wiring 3 and the ground wiring 4 are arranged along a large number of pads 2 provided along the outer peripheral portion of the chip 1, and the power supply wiring 3 and the ground wiring 4 are annular with a high resistance portion 13 interposed therebetween. It is installed in.
［作用］ 電源配線３及びグランド配線４に流れる負荷電流は同
配線3,4を環状に流れるため、同配線3,4の電流密度の上
昇が抑制されるとともに、高抵抗部の作用により負荷電
流のピーク値が抑制される。[Operation] Since the load current flowing through the power supply wiring 3 and the ground wiring 4 flows through the wirings 3 and 4 in a ring shape, the increase in the current density of the wirings 3 and 4 is suppressed, and the load current is increased by the action of the high resistance portion. The peak value of is suppressed.
［実施例］ 以下、この発明を具体化した第一の実施例を第２図及
び第３図に従って説明する。なお、前記従来例と同一構
成部分は同一番号を付してその説明を省略する。[Embodiment] A first embodiment of the present invention will be described below with reference to FIGS. 2 and 3. The same components as those in the conventional example are denoted by the same reference numerals, and description thereof is omitted.
電源配線３及びグランド配線４の開口部3b,4bにはポ
リシリコン膜６が形成され、両配線3,4の先端部がその
ポリシリコン膜６で接続されている。すなわち、グラン
ド配線４の開口部4bでは第３図に示すように基板７上に
絶縁膜８を介してグランド配線４が形成され、開口部4b
上部には絶縁膜８を介してポリシリコン膜６が形成さ
れ、グランド配線４端部が絶縁膜８に形成されたスルー
ホール９を介してそのポリシリコン膜６に接続されてい
る。そして、ポリシリコン膜６はアルミニウムで形成さ
れるグランド配線４より電気的抵抗が高いため、同グラ
ンド配線４がポリシリコン膜６による高抵抗部を介して
環状に形成されたことになる。A polysilicon film 6 is formed in the openings 3b and 4b of the power supply wiring 3 and the ground wiring 4, and the tips of both wirings 3 and 4 are connected by the polysilicon film 6. That is, in the opening 4b of the ground wiring 4, the ground wiring 4 is formed on the substrate 7 via the insulating film 8 as shown in FIG.
A polysilicon film 6 is formed on the upper part of the insulating film 8 and an end of the ground wiring 4 is connected to the polysilicon film 6 via a through hole 9 formed in the insulating film 8. Since the polysilicon film 6 has a higher electrical resistance than the ground wiring 4 made of aluminum, the ground wiring 4 is formed in an annular shape via the high resistance portion of the polysilicon film 6.
また、電源配線３の開口部3bにおいても上記と同様な
構成でポリシリコ膜６が形成され、同電源配線３が高抵
抗部を介して環状に形成されている。Further, in the opening 3b of the power supply wiring 3, the poly-silicon film 6 is formed with the same configuration as described above, and the power supply wiring 3 is formed in an annular shape via the high resistance portion.
さて、このような構成のチップ１では電源配線３及び
グランド配線４が環状に形成されているので、各パッド
部3a,4aに対し一側に偏って位置するパッド２近傍のバ
ッファ回路が同時に動作しても、それらのバッファ回路
と各パッド部3a,4aとの間で電流が環状に流れて電流密
度の上昇が抑制されるので、同電源配線３及びグランド
配線４の線幅を大きくする必要はない。そして、電源配
線３及びグランド配線４に介在されるポリシリコン膜６
は抵抗成分及び容量成分を備えているので、第４図に実
線で示すように各配線3,4に流れる負荷電流I1はピーク
値の低いものとなる。従って、グランド配線３に流れる
負荷電流に基く内部回路５のグランドでのグリッチの発
生が防止される。Since the power supply wiring 3 and the ground wiring 4 are formed in an annular shape in the chip 1 having such a configuration, the buffer circuit near the pad 2 which is biased to one side with respect to each pad portion 3a, 4a simultaneously operates. However, since the current flows between the buffer circuits and the pad portions 3a and 4a in an annular shape to suppress the increase of the current density, it is necessary to increase the line widths of the power supply wiring 3 and the ground wiring 4. There is no. Then, the polysilicon film 6 interposed between the power supply wiring 3 and the ground wiring 4
Has a resistance component and a capacitance component, the load current I1 flowing through the wirings 3 and 4 has a low peak value as shown by the solid line in FIG. Therefore, the occurrence of glitches in the ground of the internal circuit 5 due to the load current flowing through the ground wiring 3 is prevented.
また、前記実施例では高抵抗部をポリシリコン膜６で
形成したが、第５図に示すようにグランド配線４の開口
部4bにおいてチップ１の基板７には不純物拡散領域10を
形成し、その不純物拡散領域10上に絶縁膜11を介してグ
ランド配線４を形成し、絶縁膜11に形成されたスルーホ
ール12でグランド配線４先端を不純物拡散領域10に接続
する構成としてもよい。すなわち、この構成ではグラン
ド配線４に対し高抵抗部として作用する不純物拡散領域
10で同グランド配線４が環状に接続され、前記実施例と
同様な作用効果が得られる。Although the high resistance portion is formed of the polysilicon film 6 in the above embodiment, the impurity diffusion region 10 is formed in the substrate 7 of the chip 1 in the opening 4b of the ground wiring 4 as shown in FIG. The ground wiring 4 may be formed on the impurity diffusion region 10 via the insulating film 11, and the tip of the ground wiring 4 may be connected to the impurity diffusion region 10 by the through hole 12 formed in the insulating film 11. That is, in this configuration, the impurity diffusion region that acts as a high resistance portion with respect to the ground wiring 4
At 10, the same ground wiring 4 is connected in a ring shape, and the same effect as that of the above-described embodiment is obtained.
［発明の効果］ 以上詳述したように、この発明は半導体集積回路の電
源配線及びグランド配線の線幅を大きくすることなくそ
れらの経時断線を防止し、かつグランド配線に流れる負
荷電流のピーク値を抑制してグリッチによる内部回路の
誤動作を防止することができる優れた効果を発揮する。[Effects of the Invention] As described in detail above, the present invention prevents the power supply wiring and the ground wiring of a semiconductor integrated circuit from being disconnected over time and increases the peak value of the load current flowing in the ground wiring. It has an excellent effect of suppressing the malfunction of the internal circuit due to glitch.
【図面の簡単な説明】 第１図はこの発明の原理説明図、第２図はこの発明の実
施例のチップを示す正面図、第３図はグランド配線の高
抵抗部を示す断面図、第４図はグランド配線に流れる負
荷電流の波形図、第５図はグランド配線の高抵抗部の別
の実施例を示す断面図、第６図は従来の配線を示すチッ
プ正面図である。 図中、１はチップ、２はパッド、３電源配線、４はグラ
ンド配線、13は高抵抗部である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory view of the principle of the present invention, FIG. 2 is a front view showing a chip of an embodiment of the present invention, FIG. 3 is a sectional view showing a high resistance portion of a ground wiring, and FIG. FIG. 4 is a waveform diagram of a load current flowing in the ground wiring, FIG. 5 is a cross-sectional view showing another embodiment of the high resistance portion of the ground wiring, and FIG. 6 is a chip front view showing the conventional wiring. In the figure, 1 is a chip, 2 is a pad, 3 is power supply wiring, 4 is ground wiring, and 13 is a high resistance portion.
Claims (1)
るパッド（２）に沿って電源配線（３）及びグランド配
線（４）を配設し、その電源配線（３）及びグランド配
線（４）は一部に高抵抗部（13）を介在させて環状に配
設したことを特徴とする半導体集積回路。1. A power supply wiring (3) and a ground wiring (4) are arranged along a large number of pads (2) provided along an outer peripheral portion of a chip (1), and the power supply wiring (3) and the ground wiring ( 4) is a semiconductor integrated circuit characterized in that the high resistance portion (13) is disposed in a part to be annularly arranged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1006563A JP2685135B2 (en) | 1989-01-12 | 1989-01-12 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1006563A JP2685135B2 (en) | 1989-01-12 | 1989-01-12 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02186671A JPH02186671A (en) | 1990-07-20 |
| JP2685135B2 true JP2685135B2 (en) | 1997-12-03 |
Family
ID=11641800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1006563A Expired - Fee Related JP2685135B2 (en) | 1989-01-12 | 1989-01-12 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2685135B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2792795B2 (en) * | 1992-10-29 | 1998-09-03 | 三菱電機株式会社 | Semiconductor integrated device |
| JP2013033775A (en) * | 2009-12-03 | 2013-02-14 | Panasonic Corp | Semiconductor integrated circuit, semiconductor device equipped with the same and electronic apparatus |
| JP6769283B2 (en) * | 2016-12-16 | 2020-10-14 | セイコーエプソン株式会社 | Circuits, oscillators, electronics and mobiles |
| CN110033741B (en) * | 2019-04-19 | 2020-02-18 | 深圳市华星光电半导体显示技术有限公司 | Multiplexing circuit and display device |
| CN110416203A (en) * | 2019-06-20 | 2019-11-05 | 北京聚睿众邦科技有限公司 | A kind of ic core sheet resistance and its manufacturing process |
-
1989
- 1989-01-12 JP JP1006563A patent/JP2685135B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02186671A (en) | 1990-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4955078B2 (en) | Semiconductor device | |
| JP4484400B2 (en) | Semiconductor device | |
| JP4025044B2 (en) | Semiconductor integrated circuit device | |
| JP2685135B2 (en) | Semiconductor integrated circuit | |
| JPH0555380A (en) | Semiconductor integrated circuit device | |
| JP2636804B2 (en) | Semiconductor device | |
| JP3969020B2 (en) | Semiconductor integrated circuit device | |
| EP0394878A2 (en) | Semiconductor device having multi-layered wiring structure | |
| JP3111938B2 (en) | Semiconductor device | |
| US6359313B1 (en) | Electrostatic discharge protection transistor for a semiconductor chip | |
| JP2002057418A (en) | Printed wiring board | |
| JP2890269B2 (en) | Semiconductor device | |
| JP4402944B2 (en) | Semiconductor protection device | |
| JPS613442A (en) | Semiconductor device | |
| JP2003124331A (en) | Semiconductor integrated circuit device | |
| JP2001077230A (en) | Lead frame and semiconductor device mounting body using the same | |
| JP2766490B2 (en) | Semiconductor device | |
| JPS6161448A (en) | Integrated circuit device | |
| JP2005327987A (en) | Semiconductor device | |
| JPS60153135A (en) | Semiconductor device | |
| KR940007381B1 (en) | Lead frame | |
| JP2003124333A (en) | Semiconductor ic chip | |
| JPS6164142A (en) | Semiconductor integrated circuit device | |
| JPH03270067A (en) | Semiconductor integrated device | |
| JPS59215749A (en) | Low noise package for semiconductor integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |