JP4484400B2 - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control an oscillation phenomenon appearing in a potential of a control electrode of a switching element. SOLUTION: The emitter electrodes of a plurality of IGBT 3 which are connected in parallel are connected with each other through a wiring pattern 26 (or 27) not relaying a wiring pattern 22 (or 23) and conductor wires W1, W2, W3 and W4.

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device suitable for controlling a large current, and more particularly to an improvement for suppressing an oscillation phenomenon appearing in a potential of a control electrode of a switching element.
[0002]
[Prior art]
FIG. 28 is a plan sectional view of a base portion of a conventional semiconductor device as the background of the present invention. The semiconductor device 150 is formed as a power module including a plurality of power semiconductor elements. As shown in FIG. 28, the semiconductor device 150 includes a substrate 62 at the bottom thereof. On the main surface of the substrate 62, a plurality of wiring patterns 81 to 85 isolated from each other are arranged in an island shape. Two IGBTs 63 and two diodes 64 belonging to the upper arm 70 are disposed on the wiring pattern 81, and two IGBTs 63 and two diodes belonging to the lower arm 71 are disposed on the wiring pattern 82. A diode 64 is disposed.
[0003]
The four IGBTs 63 and the four diodes 64 are all formed as bare chips. Thereby, the collector electrodes of the two IGBTs 63 belonging to the upper arm 70 and the cathode electrodes of the two diodes 64 are electrically connected to each other through the wiring pattern 81. Similarly, the collector electrodes of the two IGBTs 63 belonging to the lower arm 71 and the cathode electrodes of the two diodes 64 are electrically connected to each other through the wiring pattern 82.
[0004]
The emitter electrodes of the two IGBTs 63 belonging to the upper arm 70 and the wiring pattern 82 are connected to each other by a large number of conductor wires 75. The anode electrodes of the two diodes 64 belonging to the upper arm 70 and the wiring pattern 82 are connected to each other by a large number of conductor wires 76. Similarly, the emitter electrodes of the two IGBTs 63 belonging to the lower arm 71 and the wiring pattern 83 are connected to each other by a large number of conductor wires 75. The anode electrodes of the two diodes 64 belonging to the lower arm 71 and the wiring pattern 83 are connected to each other by a large number of conductor wires 76.
[0005]
In FIG. 28, in order to avoid complications, the conductor wire 75 is not shown for the upper arm 70, and the conductor wire 76 is not shown for the lower arm 71.
[0006]
The wiring pattern 84 and the gate electrodes of the two IGBTs 63 belonging to the upper arm 70 are connected by a conductor wire 77. Similarly, the wiring pattern 85 and the gate electrodes of the two IGBTs 63 belonging to the lower arm 71 are connected by a conductor wire 77.
[0007]
The wiring patterns 81 to 85 include an external terminal CC to which a high power supply potential is supplied, an external terminal EE to which a low power supply potential is supplied, an external terminal OUT to which a load is connected, and an external terminal G1 to which a drive circuit is connected. G2, S1, and S2 are connected. In FIG. 28, the connection portion between each wiring pattern and the external terminal is shown with hatching.
[0008]
As described above, in the semiconductor device 150, the upper arm 70 and the lower arm 71 connected in series are inserted between the high power supply potential and the low power supply potential and input to the external terminal G1 (and G2). In response to the drive signal, the two IGBTs 63 belonging to the upper arm 70 (and the lower arm 71) are turned on / off.
[0009]
[Problems to be solved by the invention]
As shown in the example of the semiconductor device 150, in a power module having a large rated current (for example, 100 A or more), a plurality of power switching elements are connected in parallel so as to share a large current. However, in the power module, when an unexpected short circuit occurs in the load, a short circuit current having a magnitude of about 5 to about 10 times the rated current flows. In a power module including a plurality of power switching elements, when a short-circuit current flows, the potential of the control electrode (gate electrode in IGBT) of each switching element may oscillate. It can be seen that the larger the rated current of the power module, the easier it is to oscillate.
[0010]
In addition, even when only one switching element is provided on each of the upper arm and the lower arm, the main electrode of the switching element has a plurality of bonding pads (IGBT 63 in FIG. 28) separated from each other. In the case of having a plurality of strip-like portions drawn in the inside, there may be a case where the same oscillation occurs when a short-circuit current flows.
[0011]
When oscillation occurs, it may be assumed that the normal operation of the application device using the power module appears, and may be a cause of noise. Furthermore, if the switching element is an IGBT, an influence on the gate insulating film is assumed.
[0012]
The present invention has been made to solve the above-described problems in conventional devices, and an object thereof is to obtain a semiconductor device capable of suppressing an oscillation phenomenon appearing in the potential of a control electrode of a switching element.
[0013]
[Means for Solving the Problems]
An apparatus of a first invention is a semiconductor device, a substrate having a main surface; Electrically isolated from each other First wiring pattern disposed on the main surface And second wiring pattern And a plurality of switching elements in which one main electrode is electrically connected to each other by being disposed on the first wiring pattern, ,in front A plurality of first conductor wires having one end connected to the other main electrode of the plurality of switching elements and the other end connected to the second wiring pattern, and connected to the second wiring pattern, An external terminal that electrically connects the other main electrode and the outside through the second wiring pattern, and the other main electrodes of the plurality of switching elements are electrically connected without relaying the second wiring pattern. And a conductor to be connected.
[0014]
Furthermore, in the apparatus of the first invention, The conductor is Isolated from the first wiring pattern and the second wiring pattern and electrically insulated from the first wiring pattern and the second wiring pattern A plurality of second conductor wires having one end connected to the third wiring pattern disposed on the main surface and the other main electrode of the plurality of switching elements and the other end connected to the third wiring pattern And comprising.
[0015]
Furthermore, in the apparatus of the first invention, The second wiring pattern extends along the arrangement direction of the plurality of switching elements, and the third wiring pattern is on the opposite side of the second wiring pattern across the plurality of switching elements, It extends along the arrangement direction of the plurality of switching elements.
[0016]
Furthermore, in the apparatus of the first invention, The third wiring pattern is adjacent to the plurality of switching elements without sandwiching another wiring pattern.
[0017]
First 2 In the device of the invention, First In the semiconductor device of the invention, the third wiring pattern has a bent portion that repeats.
[0021]
Third The device of the invention of First or second In the semiconductor device of the invention, a plurality of fourth wiring patterns disposed on the main surface and a plurality of switching electrodes connected at one end to the control electrodes of the plurality of switching elements and connected at the other end to the fourth wiring patterns. A fourth conductor wire; and a voltage clamp element having one end connected to the third wiring pattern and the other end connected to the four wiring pattern.
[0027]
4th In the device of the invention, the first to the first Third In the semiconductor device of any one of the inventions, each of the plurality of switching elements is an insulated gate switching element.
[0043]
DETAILED DESCRIPTION OF THE INVENTION
Outline of the embodiment.
As a technique for preventing a phenomenon in which a power module including a plurality of switching elements such as the semiconductor device 150 in FIG. 28 causes oscillation due to a short-circuit current or a technique for reducing the oscillation phenomenon, The following three approaches were assumed. (1) The reference potential of the control electrode (gate electrode in the IGBT example) between the switching elements connected in parallel, that is, the potential of the one main electrode (emitter electrode in the IGBT example) is made uniform. (2) Provide an element that absorbs oscillation when oscillation occurs. (3) Reduce the short circuit current.
[0044]
When a short-circuit current flows, the increase rate (= dI / dt) of the main current (emitter current in the IGBT example) I becomes higher than the increase rate of the main current I under a normal switching operation. Due to the change in the main current, an induced electromotive force V (= −L × dI / dt) is generated by the internal inductance L that is parasitically present inside the power module, and this induced electromotive force V is superimposed on the potential of the control electrode. Is done. This induced electromotive force V is applied in the direction of increasing the potential of the control electrode, that is, in the direction of increasing the main current. When the rate of increase in the potential of the control electrode exceeds a certain limit, vibration occurs in the potential of the control electrode.
[0045]
The induced electromotive force V is applied to each of a plurality of switching elements connected in parallel, and each switching element operates independently in a transient state. For this reason, due to the characteristic difference that exists slightly between the plurality of switching elements, vibration is exchanged between the plurality of switching elements, which acts in the direction of expanding the oscillation. Therefore, in order to suppress the expansion of oscillation, it is effective to make the reference potential uniform among the plurality of switching elements.
[0046]
In order to make the reference potential uniform among a plurality of switching elements, the main electrodes formed on the semiconductor chip of the plurality of switching elements are positioned as close as possible and are affected by the main current. It is an effective means to connect with no conductor. In the power module to which such means is applied, the induced starting force V acting between the switching elements is automatically balanced by the increase rate of the main current (= dI / dt) when the short-circuit current flows, As a result, it is possible to suppress or prevent the oscillation phenomenon. This is the first approach.
[0047]
In the second approach, a voltage clamp element is interposed between the control electrodes of the plurality of switching elements connected in parallel and the one main electrode. Thereby, even if oscillation occurs, the potential of the control electrode can be suppressed to a certain limit or less. That is, the intensity of the oscillation phenomenon can be reduced. In the case where the switching element is an insulated gate type switching element such as an IGBT, it is possible to prevent the influence on the gate insulating film by reducing the intensity of the oscillation phenomenon.
[0048]
In order to suppress the oscillation phenomenon, it is effective to reduce the induction starting force V applied to the control electrode. However, the internal inductance L parasitically present in the power module has already been reduced to the limit level in the current technology including the semiconductor device 150 of FIG. Therefore, in order to reduce the induction starting force V, it is necessary to suppress the current increase rate (= dI / dt). The rate of increase in current (= dI / dt) can be reduced by keeping the potentials of the control electrodes of the plurality of switching elements low.
[0049]
When the load is short-circuited, a large short-circuit current flows through the wiring pattern through which the main current flows. At this time, an inductive starting force is generated in the wiring pattern due to the inductance inherent to that portion. By this induced electromotive force, the potential of the one main electrode is raised, and as a result, the potential of the control electrode with respect to the one main electrode is lowered, and an increase in the main current of each switching element is suppressed. This is the third approach.
[0050]
Further, as described above, even when only one switching element is provided on each of the upper arm and the lower arm, the main electrode of the switching element has a plurality of bonding pads separated from each other. In some cases, oscillation may occur when a short-circuit current flows. In order to suppress this oscillation, the above-described first to third approaches can be assumed by regarding a plurality of bonding pads as main electrodes of a plurality of switching elements.
[0051]
In the following, a preferred embodiment based on these three approaches will be described in detail. Embodiments 1 to 4 and 8 to 15 are based on the first approach, Embodiment 5 is based on the first and second approaches, and Embodiments 6 and 7 are the first and third approaches. Based on the approach. Further, the sixteenth and seventeenth embodiments are based on the third approach.
[0052]
Embodiment 1 FIG.
FIG. 1 is a circuit diagram of a semiconductor device according to the first embodiment. 2 is an external perspective view of the semiconductor device 101 of FIG. 1, and FIG. 3 is a cross-sectional view of the semiconductor device 101 taken along the line XX of FIG.
[0053]
As shown in FIG. 1, the semiconductor device 101 includes an upper arm 10 having two IGBTs 3 and two diodes 4, and a lower arm 11 having two IGBTs 3 and two diodes 4. Yes. A power IGBT is used as the IGBT 3, and a power diode is used as the diode 4. That is, the semiconductor device 101 is formed as a power module including a plurality of power semiconductor elements.
[0054]
In both the upper arm 10 and the lower arm, the emitter electrodes, the collector electrodes, and the gate electrodes are connected between the two IGBTs 3. That is, the two IGBTs 3 are connected in parallel to each other so as to function as one IGBT. The two diodes 4 are connected in parallel with the two IGBTs 3 in such a direction that the forward current circulates so as to function as a freewheel diode. That is, the anode electrode of the diode 4 is connected to the emitter electrode of the IGBT 3, and the cathode electrode is connected to the collector electrode of the IGBT 3.
[0055]
The upper arm 10 and the lower arm 11 are connected in series with each other. The collector electrodes of the two IGBTs 3 of the upper arm 10 are connected to the external terminal CC, the gate electrode is connected to the external terminal G1, and the emitter electrode is connected to the external terminal OUT and the external terminal S1. The collector electrodes of the two IGBTs 3 of the lower arm 11 are connected to the external terminal OUT, the gate electrode is connected to the external terminal G2, and the emitter electrode is connected to the external terminal EE and the external terminal S2.
[0056]
As shown in FIG. 2, these external terminals protrude outward from the upper surface of the case 1, thereby enabling connection to an external device (not shown). Returning to FIG. 1, a high power supply potential (positive power supply potential in the example of FIG. 1) is supplied to the external terminal CC, and a low power supply potential (ground potential in the example of FIG. 1) is supplied to the external terminal EE. Is done. A load 93 is connected to the external terminal OUT.
[0057]
A drive circuit 90 is connected to the external terminal G1 and the external terminal S1. The drive circuit 90 supplies a drive signal based on the potential of the external terminal S1 to the external terminal G1. The IGBT 3 of the upper arm 10 is turned on / off in response to a drive signal input through the external terminal G1. Similarly, the drive circuit 91 is connected to the external terminal G2 and the external terminal S2. The drive circuit 91 supplies a drive signal based on the potential of the external terminal S2 to the external terminal G2. The IGBT 3 of the lower arm 11 is turned on / off in response to a drive signal input through the external terminal G2.
[0058]
As shown in FIG. 3, the semiconductor device 101 includes a substrate 2 at the bottom. A plurality of wiring patterns 21 to 27 isolated from each other are arranged in an island shape on the main surface of the substrate 2. The plurality of wiring patterns 21 to 27 are electrically insulated from each other. For this purpose, for example, the main surface of the substrate 2 may be an insulator. Alternatively, an insulator may be interposed between the wiring patterns 21 to 27 and the substrate 2. Two IGBTs 3 and two diodes 4 belonging to the upper arm 10 are arranged on the wiring pattern 21, and two IGBTs 3 and two pieces belonging to the lower arm 11 are arranged on the wiring pattern 22. A diode 4 is arranged.
[0059]
The four IGBTs 3 and the four diodes 4 are all formed as bare chips. Thereby, the collector electrodes of the two IGBTs 3 belonging to the upper arm 10 and the cathode electrodes of the two diodes 4 are electrically connected to each other through the wiring pattern 21. Similarly, the collector electrodes of the two IGBTs 3 belonging to the lower arm 11 and the cathode electrodes of the two diodes 4 are electrically connected to each other through the wiring pattern 22.
[0060]
Two diodes 4 and two IGBTs 3 connected in parallel with each other are arranged adjacent to each other in a one-to-one relationship. That is, they are arranged so that one diode 4 is adjacent to one IGBT 3. Thereby, the resistance and inductance between the diode 4 and the IGBT 3 are reduced, and the protection function for the IGBT 3 of the diode 4 as a freewheel diode is enhanced.
[0061]
An external terminal CC is connected to the wiring pattern 21. That is, the external terminal CC is electrically connected to the collector electrodes of the two IGBTs 3 belonging to the upper arm 10 and the cathode electrodes of the two diodes 4 through the wiring pattern 21. Similarly, an external terminal OUT is connected to the wiring pattern 22. That is, the external terminal OUT is electrically connected to the collector electrodes of the two IGBTs 3 belonging to the lower arm 10 and the cathode electrodes of the two diodes 4 through the wiring pattern 22. In FIG. 3 (and the following drawings), the connection portions between the wiring patterns and the external terminals are shown with hatching.
[0062]
The emitter electrodes of the two IGBTs 3 belonging to the upper arm 10 and the wiring pattern 22 are connected to each other by a large number of conductor wires 15. Further, the anode electrodes of the two diodes 4 belonging to the upper arm 10 and the wiring pattern 22 are connected to each other by a large number of conductor wires 16. Similarly, the emitter electrodes of the two IGBTs 3 belonging to the lower arm 11 and the wiring pattern 23 are connected to each other by a large number of conductor wires 15. Further, the anode electrodes of the two diodes 4 belonging to the lower arm 11 and the wiring pattern 23 are connected to each other by a large number of conductor wires 16. For example, aluminum wires are used as the conductor wires 15 and 16 and the conductor wires described below.
[0063]
In FIG. 3 (and the following figures), in order to avoid complication, the conductor wire 15 is not shown for the upper arm 10, and the conductor wire 16 is not shown for the lower arm 11.
[0064]
Furthermore, the wiring pattern 22 extends along the arrangement direction of the two IGBTs 3 belonging to the upper arm 10, and the wiring pattern 23 extends along the arrangement direction of the two IGBTs 3 belonging to the lower arm 11. Yes. In each of the upper arm 10 and the lower arm 11, the two IGBTs 3 are arranged so that the conductor wires 15 connecting the emitter electrodes of the two IGBTs 3 connected in parallel and the wiring pattern 22 (or 23) are shortest. Are arranged in a direction substantially perpendicular to the arrangement direction.
[0065]
Similarly, the conductor wire 16 connecting the anode electrode of the two diodes 4 connected in parallel and the wiring pattern 22 (or 23) is in a direction substantially orthogonal to the arrangement direction of the two IGBTs 3 so as to be the shortest. It is arranged. As a result, the emitter electrodes of the two IGBTs 3 and the anode electrodes of the two diodes 4 connected in parallel are connected to the wiring pattern 22 (or 23) through a low resistance and a low inductance.
[0066]
In addition to the external terminal OUT, an external terminal S1 is connected to the wiring pattern 22, and an external terminal EE and an external terminal S2 are connected to the wiring pattern 23. Thereby, the emitter electrodes of the two IGBTs 3 and the anode electrodes of the two diodes 4 belonging to the upper arm 10 are electrically connected to both the external terminal OUT and the external terminal S1 through the conductor wires 15 and 16 and the wiring pattern 22. It is connected to the. Similarly, the emitter electrodes of the two IGBTs 3 and the anode electrodes of the two diodes 4 belonging to the lower arm 11 are electrically connected to both the external terminal EE and the external terminal S2 through the conductor wires 15 and 16 and the wiring pattern 23. It is connected to the.
[0067]
An external terminal G 1 is connected to the wiring pattern 24, and the wiring pattern 24 and the gate electrodes of the two IGBTs 3 belonging to the upper arm 10 are connected by a conductor wire 17. That is, the external terminal G 1 and the gate electrodes of these IGBTs 3 are electrically connected to each other through the conductor wire 17 and the wiring pattern 24. Similarly, an external terminal G <b> 2 is connected to the wiring pattern 25, and the wiring pattern 25 and the gate electrodes of the two IGBTs 3 belonging to the lower arm 11 are connected by a conductor wire 17. That is, the external terminal G 2 and the gate electrodes of these IGBTs 3 are electrically connected to each other through the conductor wire 17 and the wiring pattern 25.
[0068]
The wiring pattern 26 and the emitter electrodes of the two IGBTs 3 belonging to the upper arm 10 are connected by conductor wires W1 and W2. As a result, the emitter electrodes of the two IGBTs 3 belonging to the upper arm 10 are paths that do not relay the wiring pattern 22 and are paths through which the emitter current flowing through the external terminal OUT does not flow, and the conductor wires W1 and W2 and the wiring pattern 26 are electrically connected to each other. As a result, the emitter potentials of the two IGBTs 3 belonging to the upper arm 10 are made uniform, so that even when the load 93 is short-circuited, the oscillation phenomenon at the potentials of the gate electrodes of the two IGBTs 3 is suppressed.
[0069]
Similarly, the wiring pattern 27 and the emitter electrodes of the two IGBTs 3 belonging to the lower arm 11 are connected by conductor wires W3 and W4. As a result, the emitter electrodes of the two IGBTs 3 belonging to the lower arm 11 are paths that do not relay the wiring pattern 23 and are paths through which the emitter current flowing through the external terminal EE does not flow, and the conductor wires W3 and W4 and the wiring pattern 27 are electrically connected to each other. As a result, the emitter potentials of the two IGBTs 3 belonging to the lower arm 11 are made uniform, so that even when the load 93 is short-circuited, the oscillation phenomenon at the potentials of the gate electrodes of the two IGBTs 3 is suppressed.
[0070]
Further, the connection between the emitter electrodes of the two IGBTs 3 for equalizing the emitter potential is to connect each emitter electrode and the wiring pattern 26 (or 27) with the conductor wires W1, W2 (or W3, W4). This is easily achieved. That is, there is an advantage that the manufacturing process is easy. In addition, since one end of the conductor wires W1, W2 (or W3, W4) is connected to the wiring pattern 26 (or 27), in the step of arranging the conductor wires W1, W2 (or W3, W4), wire cutting is performed. Does not need to be performed on the IGBT 3. For this reason, it is possible to easily arrange the conductor wires W1, W2 (or W3, W4) without requiring special measures for preventing the IGBT 3 from being damaged.
[0071]
Furthermore, the wiring pattern 22 extends along the arrangement direction of the two IGBTs 3 belonging to the upper arm 10, and the wiring pattern 26 is also arranged on the opposite side of the wiring pattern 22 across the IGBT 3. Extends along the direction. For this reason, it is possible to easily arrange the conductor wires W1 and W2 without interfering with the conductor wire 15. Furthermore, since the inductive coupling between the conductor wire 15 and the conductor wires W1 and W2 can be reduced, the effect of suppressing oscillation can be enhanced.
[0072]
Similarly, the wiring pattern 23 extends along the arrangement direction of the two IGBTs 3 belonging to the lower arm 11, and the wiring pattern 27 is located on the opposite side of the wiring pattern 23 with the IGBT 3 interposed therebetween. It extends along the arrangement direction. Therefore, the same effect as described above regarding the upper arm can be obtained with respect to the lower arm 11.
[0073]
Further, in each of the upper arm 10 and the lower arm 11, the two diodes 4 are disposed between the two IGBTs 3 and the wiring pattern 22 (or 23), so that the anode electrodes of the two diodes 4 The conductor wires W1, W2 (or W3, W4) can be easily arranged without interfering with the conductor wires 16 connecting the wiring pattern 22 (or 23).
[0074]
Further, the wiring pattern 26 is adjacent to the two IGBTs 3 belonging to the upper arm 10 without sandwiching other wiring patterns. For this reason, it is possible to set the conductor wires W1, W2 short. As a result, the inductance of the path that electrically connects the emitter electrodes of the two IGBTs 3 belonging to the upper arm 10 is reduced, so that the effect of equalizing the potential of the emitter electrode can be further enhanced. Similarly, the wiring pattern 27 is adjacent to the two IGBTs 3 belonging to the lower arm 11 without sandwiching other wiring patterns. Accordingly, the same effect as described above with respect to the upper arm can be obtained with respect to the lower arm 11.
[0075]
1 to 3 show an example in which there are two IGBTs 3 and diodes 4 connected in parallel, but three or more IGBTs 3 and diodes 4 may be connected in parallel.
[0076]
Embodiment 2. FIG.
FIG. 4 is a plan sectional view of the semiconductor device according to the second embodiment. A circuit diagram and an external perspective view of the semiconductor device 102 are the same as those of the first embodiment shown in FIGS. 1 and 2, and FIG. It corresponds to a cross-sectional view along the line. In the following drawings, the same or corresponding parts (parts having the same functions) as those of the semiconductor device 101 shown in FIGS. 1 to 3 are denoted by the same reference numerals and detailed description thereof is omitted.
[0077]
The semiconductor device 102 is characteristically different from the semiconductor device 101 of FIG. 3 in that each of the wiring patterns 26 and 27 has a repeated bent portion. Experiments have shown that there is an optimum value for the suppression of oscillation in the inductance of the path connecting the emitter electrodes of two IGBTs 3 connected in parallel to each other without relaying the wiring pattern 22 (or 23). Has been confirmed. In the semiconductor device 102, since each of the wiring patterns 26 and 27 has a repeated bent portion, the emitter electrodes of the two IGBTs 3 connected in parallel can be electrically connected by changing the connection position of the conductor wires W1 to W4. The inductance of the path to be connected can be freely adjusted. As a result, at the final stage of the manufacturing process of the semiconductor device 102, the inductance of each of the wiring patterns 26 and 27 can be finely adjusted to an optimum value.
[0078]
Although FIG. 4 shows an example in which two IGBTs 3 and two diodes 4 are connected in parallel, three or more IGBTs 3 and four diodes 4 may be connected in parallel.
[0079]
Embodiment 3 FIG.
FIG. 5 is a plan sectional view of the semiconductor device according to the third embodiment. A circuit diagram and an external perspective view of the semiconductor device 103 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 5 is an XX cut line when the semiconductor device 101 of FIG. It corresponds to a cross-sectional view along the line.
[0080]
The semiconductor device 103 is not provided with the wiring patterns 26 and 27 and the conductor wires W1 to W4. Instead, the emitter electrodes of two IGBTs 3 connected in parallel are directly connected by the conductor wire W5 (or W6). 3 is characteristically different from the semiconductor device 101 of FIG. Since the wiring patterns 26 and 27 are not required, the manufacturing process is facilitated, the area of the substrate 2 can be reduced, and the semiconductor device 103 can be downsized.
[0081]
As shown in FIG. 5, in each of the upper arm 10 and the lower arm 11, the conductor wire W5 (or W6) is disposed along the arrangement direction of the two IGBTs 3 connected in parallel. As a result, the conductor wire W5 (or W6) is approximately orthogonal to the conductor wire 15 that connects the two IGBTs 3 connected in parallel and the wiring pattern 22 (or 23). Thereby, the inductive coupling between the conductor wire 15 and the conductor wire W5 (or W6) is suppressed low, and the effect of suppressing oscillation is further enhanced.
[0082]
Furthermore, in each of the upper arm 10 and the lower arm 11, the conductor wire W5 (or W6) is connected to the emitter electrodes of the two IGBTs 3 at a portion farther from the wiring pattern 22 (or 23) than one end of the conductor wire 15. Has been. For this reason, the inductive coupling between the conductor wire 15 and the conductor wire W5 (or W6) is further suppressed, and the effect of suppressing oscillation is further enhanced. Further, the conductor wire 15 and the conductor wire W5 (or W6) can be easily disposed without interfering with each other.
[0083]
FIG. 5 shows an example in which there are two IGBTs 3 and two diodes 4 connected in parallel, but three or more IGBTs 3 and diodes 4 may be connected in parallel. At this time, among a plurality of IGBTs 3 connected in parallel, the emitter electrodes may be individually connected between two adjacent ones with a conductor wire, and three or more places including the middle part of the conductor wire are connected to the emitter electrode. By doing so, the emitter electrodes of three or more IGBTs 3 may be connected by a single conductor wire.
[0084]
Embodiment 4 FIG.
FIG. 6 is a plan sectional view of a semiconductor device according to the fourth embodiment. A circuit diagram and an external perspective view of the semiconductor device 104 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 6 is an XX cut line when the semiconductor device 101 in FIG. It corresponds to a cross-sectional view along the line.
[0085]
The semiconductor device 104 is not provided with the wiring patterns 26 and 27 and the conductor wires W1 to W4. Instead, the emitter electrodes of the two IGBTs 3 connected in parallel are formed by the conductor wires W7 and W8 (or W9 and W10). 3 is characteristically different from the semiconductor device 101 of FIG. 3 in that it is connected to one anode electrode of the two diodes 4 and the wiring pattern 22 (or 23). That is, one end of each of the conductor wires W7, W8 (or W9, W10) is connected to the emitter electrodes of the two IGBTs 3 connected in parallel, and the intermediate part is connected to one anode electrode of the two diodes 4, The other end is connected to the wiring pattern 22 (or 23).
[0086]
Therefore, the emitter electrodes of the two IGBTs 3 connected in parallel do not pass through the wiring pattern 22 (or 23) through which the emitter current flows, and the conductor wire W7 (or W9), the anode electrode of the diode 4, and the conductor wire They are electrically connected to each other through W8 (or W10). As a result, similar to the semiconductor device 101 (FIG. 3), the potentials of the emitter electrodes of the two IGBTs 3 connected in parallel are made uniform, so that an effect of suppressing the oscillation phenomenon is obtained.
[0087]
Furthermore, since the other ends of the conductor wires W7, W8 (or W9, W10) are connected to the second wiring pattern, in the step of arranging the conductor wires W7, W8 (or W9, W10), the wire cut is performed with the IGBT 3 and There is no need to do this on any of the diodes 4. Therefore, no steps for preventing damage to the IGBT 3 and the diode 4 are required in the manufacturing process. That is, there is an advantage that the manufacturing process can be simplified.
[0088]
Although FIG. 6 shows an example in which two IGBTs 3 and two diodes 4 are connected in parallel, three or more IGBTs 3 and diodes 4 may be connected in parallel. At this time, the emitter electrodes of all the IGBTs 3 are electrically connected through the anode electrodes of the single or plural diodes 4 and the plural conductor wires without going through the wiring pattern 22 (or 23). A plurality of conductor wires are provided. Also in this case, one end of each conductor wire is connected to the emitter electrode of the IGBT 3, the middle portion is connected to the anode electrode of the diode 4, and the other end is connected to the wiring pattern 22 (or 23). One end of at least one conductor wire is connected to all of the plurality of IGBTs 3. However, it is also possible to adopt a form in which the middle part of the conductor wire is connected to only a part of the plurality of diodes 4. is there.
[0089]
Embodiment 5 FIG.
FIG. 7 is a plan sectional view of the semiconductor device according to the fifth embodiment. FIG. 8 is a circuit diagram showing a part of the semiconductor device 105. The external perspective view of the semiconductor device 105 is the same as FIG. 2 of the first embodiment, and FIG. 7 corresponds to a cross-sectional view taken along the line XX when the semiconductor device 101 of FIG. To do.
[0090]
In the semiconductor device 105, two Zener diodes 9 connected in series so that the direction of the forward current is reversed are interposed between the wiring pattern 24 (or 25) and the wiring pattern 26 (or 27). 3 is characteristically different from the semiconductor device 101 of FIG. The two Zener diodes 9 are connected to each other via a wiring pattern 31 disposed on the substrate 2. Two Zener diodes 9 connected in series form a voltage clamp element 30.
[0091]
The voltage clamp element 30 prevents the potential difference between the gate electrode and the emitter electrode of the two IGBTs 3 connected in parallel from increasing beyond a certain limit. Therefore, even if oscillation occurs, the amplitude is suppressed so as not to exceed a certain limit.
[0092]
Although FIG. 7 shows an example in which two IGBTs 3 and two diodes 4 are connected in parallel, three or more IGBTs 3 and diodes 4 may be connected in parallel. 7 illustrates an example in which the clamp element 30 is provided in the semiconductor device 101 in FIG. 3, the clamp element 30 may be provided in the semiconductor device 102 in FIG. 4.
[0093]
Further, in FIG. 7, without providing the wiring pattern 26 (or 27) and the conductor wires W1, W2 (or W3, W4), a clamp element is provided between the emitter electrode and the gate electrode of the plurality of IGBTs 3 connected in parallel. 30 may be electrically connected. For example, the clamp element 30 may be connected between the wiring pattern 22 (or 23) and the wiring pattern 24 (or 25). In this form, the occurrence of the oscillation phenomenon cannot be suppressed, but the amplitude of the generated oscillation can be suppressed to a certain limit or less.
[0094]
Embodiment 6 FIG.
FIG. 9 is a plan sectional view of a semiconductor device according to the sixth embodiment. The external perspective view of the semiconductor device 106 is the same as FIG. 2 of the first embodiment, and FIG. 9 is a cross-sectional view taken along the line XX when the semiconductor device 101 of FIG. Equivalent to.
[0095]
The semiconductor device 106 is different from the semiconductor device of FIG. 7 in that a slit 40 (or 41) is formed in the wiring pattern 22 (or 23) extending along the arrangement direction of two IGBTs 3 connected in parallel. 105 is characteristically different. The slit 40 (or 41) extends along the arrangement direction so as to leave a connecting portion on one end side in the arrangement direction and leave no connecting portion on the other end side. That is, the slit 40 (or 41) extends from the other end side toward the one end side so as to leave a connecting portion on the one end side.
[0096]
As schematically shown in FIG. 10 as an example of the wiring pattern 23, the conductor wires 15 (and 16) are closer to the two IGBTs 3 than the slits 40 (or 41) in the wiring pattern 22 (or 23). It is connected to the first portion 23a. The external terminal OUT (or EE) is connected to the connecting portion on the one end side in the wiring pattern 22 (or 23). Further, the external terminal S1 (or S2) is connected to the other end side of the second portion 23b farther from the two IGBTs 3 than the slits 40 (or 41) in the wiring pattern 22 (or 23). . Therefore, the relationship between the two IGBTs 3 connected in parallel, the external terminal OUT (or EE), and the external terminal S1 (or S2) is represented by the circuit diagram of FIG.
[0097]
Since the emitter current passes through the first portion 23a and flows to the external terminal OUT (or EE), if the emitter current increases rapidly due to a short circuit of the load 93 or the like, due to the inductance L1 of the first portion 23a, the IGBT 3 A counter electromotive force is generated between the emitter electrode and the external terminal OUT (or EE). That is, the potential of the emitter electrode of the IGBT 3 with respect to the potential of the external terminal OUT (or EE) increases. However, since the potential of the external terminal S1 (or S2) maintains the same level as the potential of the external terminal OUT (or EE), the gate voltage applied between the gate electrode and the emitter electrode of the IGBT 3 is The emitter electrode is pulled down by the increased amount. As a result, an increase in the emitter current is suppressed, and the effect of suppressing the oscillation phenomenon is further enhanced.
[0098]
Although FIG. 9 shows an example in which two IGBTs 3 and two diodes 4 are connected in parallel, three or more IGBTs 3 and diodes 4 may be connected in parallel. 9 shows an example in which the slits 40 and 41 are formed in the semiconductor device 105 in FIG. 7, the slits 40 and 41 can be provided also in the semiconductor devices 101 to 104. Similarly, the effect of suppressing the oscillation phenomenon can be enhanced.
[0099]
Further, the wiring pattern 26 (or 27) and the conductor wires W1, W2 (or W3, W4) are not provided, and the conductor wires W5, W6 are not provided, and the wiring pattern 22 (or 23) is provided with the slit 40 ( Or 41) may be provided. Even in this embodiment, the effect of suppressing the occurrence of the oscillation phenomenon can be obtained accordingly.
[0100]
Embodiment 7 FIG.
FIG. 12 is a plan sectional view of a semiconductor device according to the seventh embodiment. The external perspective view of the semiconductor device 107 is the same as FIG. 2 of the first embodiment, and FIG. 12 is a cross-sectional view taken along the line XX when the semiconductor device 101 of FIG. Equivalent to.
[0101]
In the semiconductor device 107, the first portion 23 a and the second portion 23 b that are opposed to each other with the slit 40 (or 41) formed in the wiring pattern 22 (or 23) are connected by the conductor wire 50 (or 51). 9 is characteristically different from the semiconductor device 106 of FIG. As schematically shown in FIG. 13 as an example of the wiring pattern 23, the fact that the conductor wire 51 is disposed at a distance a from the opening end of the slit 41 indicates that the potential of the external terminal EE and the potential of the external terminal S2 Is substantially equivalent to the depth b of the slit 41 being changed to the same depth a as the distance a as shown in FIG. The same can be said for the conductor wire 50 installed in the wiring pattern 22. Therefore, when the conductor wire 50 (or 51) is disposed, the relationship between the two IGBTs 3 connected in parallel, the external terminal OUT (or EE), and the external terminal S1 (or S2) is as shown in FIG. It is represented by a circuit diagram.
[0102]
That is, by changing the position where the conductor wire 50 (or 51) is disposed, the potential of the external terminal S1 (or S2) is changed between the potential of the emitter electrode of the IGBT 3 and the potential of the external terminal OUT (or EE). The advantage is that it can be freely adjusted. Thereby, fine adjustment can be performed at the final stage of the manufacturing process so that the characteristics are uniform among the individual semiconductor devices 107 to be mass-produced.
[0103]
Structure of IGBT in each embodiment.
FIG. 16 is a plan view of IGBT 3 provided in each of semiconductor devices 101 to 107 according to the first to seventh embodiments and semiconductor devices 108 to 117 according to the eighth to seventeenth embodiments described below. The IGBT 3 includes a gate wiring 32, a gate pad 33, and a plurality of emitter pads 34 on the upper surface thereof. The gate wiring 32 is connected to the gate pad 33. For example, the conductor wire 17 shown in FIG. 3 is connected to the gate pad 33. That is, the gate pad 33 is a bonding pad for the gate electrode. The plurality of emitter pads 34 are portions to which a conductor wire can be connected among the emitter electrodes that cover most of the upper surface of the IGBT 3. That is, the emitter pad 34 is a bonding pad for the emitter electrode.
[0104]
Inside the IGBT 3 (not shown), a large number (for example, about 100,000) of basic units called unit cells (the smallest unit that itself functions as an IGBT) are connected in parallel to each other. The gate electrode of each unit cell is connected to the gate pad 33 through the gate wiring 32, and the emitter electrode that covers most of the upper surface of the IGBT 3 is connected to all unit cells in common. In the IGBT 3, the gate wiring 32 is arranged in a form branched from the gate pad 33 that receives the gate voltage through the conductor wire 17 (FIG. 3) in order to operate these many unit cells as evenly as possible. The gate wiring 32 is also referred to as a gate finger because of its shape. For this reason, the emitter electrode that covers most of the upper surface of the IGBT 3 is divided into a plurality of regions, that is, a plurality of emitter pads 34 by the gate wiring 32.
[0105]
The plurality of emitter pads 34 are integrally connected to each other through a bridging portion 35 corresponding to a gap between the gate wirings 32 in the emitter electrode. The bridging portion 35 is distinguished from the emitter pad 34 to which the conductor wire can be connected in that the bridging portion 35 is a portion that is too narrow to connect the conductor wire. In the normal operation of the IGBT 3, a conductor wire is evenly connected to each emitter pad 34 so that the emitter current of the IGBT 3 flows individually through each emitter pad 34 and hardly flows through the bridging portion 35. As a result, even though the bridging portion 35 is sufficiently narrow, the potential is kept uniform among the plurality of emitter pads 34 in normal operation.
[0106]
However, when a short-circuit current flows, the magnitude of the current flowing through the bridging portion 35 cannot be ignored, and potential unevenness may occur between the plurality of emitter pads 34. As a result, even in a semiconductor device in which only one IGBT 3 is provided in each of the upper arm 10 and the lower arm 11 (FIG. 1), an oscillation phenomenon may appear in the IGBT 3. In the following eighth to seventeenth embodiments, a semiconductor device capable of suppressing an oscillation phenomenon caused by non-uniform potential between a plurality of emitter pads 34 will be described.
[0107]
Embodiment 8 FIG.
FIG. 17 is a plan sectional view of a semiconductor device according to the eighth embodiment. A circuit diagram and an external perspective view of the semiconductor device 108 are the same as those of the first embodiment shown in FIGS. 1 and 2, and FIG. It corresponds to a cross-sectional view along the line.
[0108]
The wiring patterns 26 and 27 are divided for each corresponding IGBT 3, and all of the plurality of emitter pads 34 of each IGBT 3 and the corresponding wiring pattern 26 or 27 are a plurality of conductor wires W 1 to W 4. The semiconductor device 108 is characteristically different from the semiconductor device 101 according to the first embodiment in that it is connected by any of the above. For example, one end of six conductor wires W1 is individually connected to all six emitter pads 34 provided on one of the two IGBTs 3 belonging to the upper arm 10 (the IGBT 3 located at the left end in FIG. 17). The other end of the conductor wire W1 is connected to the wiring pattern 26.
[0109]
The plurality of conductor wires 15 that connect the emitter electrode of each IGBT 3 and the wiring pattern 22 or 23 are connected to all of the plurality of emitter pads 34 included in each IGBT 3. Therefore, as described above, in the normal operation of the semiconductor device 108, almost no current flows through the bridging portion 35 in FIG. In the example of FIG. 17, one end of two conductor wires 15 is connected to each of the plurality of emitter pads 34 of each IGBT 3, and the other end thereof is connected to the wiring pattern 22 or 23. Each of the plurality of emitter pads 34 of each IGBT 3 is connected to the wiring pattern 22 or 23 through the two conductor wires 15 in the drawings illustrating the semiconductor devices 101 to 107 according to the first to seventh embodiments. The same applies to each figure illustrating semiconductor devices 109 to 115 according to the following ninth to fifteenth embodiments except for the sixteenth and seventeenth embodiments.
[0110]
In the semiconductor device 108, as described above, any of the plurality of emitter pads 34 of each IGBT 3 is any of the conductor wires W1 to W4 that are conductors that do not relay the wiring patterns 22 and 23, that is, conductors that do not flow an emitter current. They are electrically connected to each other through the wiring patterns 26 and 27. For this reason, the potential is made uniform among the plurality of emitter pads 34. As a result, even when the load of the semiconductor device 108 is short-circuited, that is, when an excessive short-circuit current flows through each IGBT 3, the oscillation phenomenon at the potential of the gate electrode of each IGBT 3 is suppressed.
[0111]
In the example of FIG. 17, one of the conductor wires W1 to W4 is connected to each emitter pad 34 of each IGBT 3 one by one, but generally one or more may be connected. However, in the form of FIG. 17 that is connected one by one, the number of conductor wires W1 to W4 is minimized and the connection of the conductor wires W1 to W4 is facilitated, and at the same time, the oscillation of each IGBT 3 can be effectively suppressed. Benefits are gained.
[0112]
Further, in the semiconductor device 108, the emitter pads 34 of the respective IGBTs 3 are arranged along one direction, and the corresponding wiring pattern 22 or 23 and the wiring pattern 26 or 27 are arranged with the corresponding IGBT 3 interposed therebetween. Moreover, it extends along the direction in which the emitter pads 34 are arranged. For this reason, the conductor wire 15 and the conductor wires W1 to W4 can be easily disposed without interfering with each other. Furthermore, the inductive coupling between the conductor wire 15 and the conductor wires W1 to W4 can be reduced, thereby enhancing the effect of suppressing oscillation.
[0113]
In the semiconductor device 108, each of the wiring patterns 26 and 27 is adjacent to the corresponding IGBT 3 without interposing another wiring pattern. For this reason, it is possible to set the conductor wires W1-W4 short. Thereby, since the inductance of the conductor that electrically connects the emitter pads 34 is reduced, the potential can be made more uniform between the emitter pads 34 more effectively. Further, since each of the wiring patterns 26 and 27 is divided for each corresponding IGBT 3, there is an advantage that there are few restrictions on the layout of the IGBT 3.
[0114]
Although the example in which each of the upper arm 10 and the lower arm 11 includes two IGBTs 3 connected in parallel to each other as the semiconductor device 108 is shown, the semiconductor device 108 includes three or more IGBTs 3 connected in parallel to each other. It is also possible to provide only a single IGBT 3. In any case, since all of the plurality of emitter pads 34 of each IGBT 3 are electrically connected to each other through a conductor that does not relay the wiring patterns 22 and 23, the oscillation of the IGBT 3 can be suppressed.
[0115]
Embodiment 9 FIG.
FIG. 18 is a plan sectional view of a semiconductor device according to the ninth embodiment. A circuit diagram and an external perspective view of the semiconductor device 109 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 18 is an XX cut line when the semiconductor device 101 of FIG. It corresponds to a cross-sectional view along the line.
[0116]
The semiconductor device in that the conductor wires W1 to W4 are connected to only two or more (four in the example of FIG. 18) emitter pads 34 that are part of the plurality of emitter pads 34 included in each IGBT 3. 109 is characteristically different from the semiconductor device 108 according to the eighth embodiment. For example, of the six emitter pads 34 provided on one of the two IGBTs 3 belonging to the upper arm 10 (the IGBT 3 located at the left end in FIG. 17), only four of the four emitter pads 34 are provided. One end of each of the conductor wires W <b> 1 is individually connected, and the other end of the conductor wires W <b> 1 is connected to the wiring pattern 26.
[0117]
In the semiconductor device 109, a part of the plurality of emitter pads 34 included in each IGBT 3 (however, two or more emitter pads 34) do not relay the wiring patterns 22 and 23 (ie, any of the conductor wires W1 to W4). And any one of the wiring patterns 26 and 27), the effect of suppressing the oscillation when the IGBT 3 is short-circuited can be obtained accordingly. Moreover, since the space | interval of the conductor wires W1-W4 can be ensured widely, the advantage that the connection of these conductor wires W1-W4 is easy is acquired.
[0118]
The ratio of the emitter pads 34 to which any of the conductor wires W1 to W4 are connected among the plurality of emitter pads 34 included in each IGBT 3 is 1/2 or more (three or more in the example of the IGBT 3 in FIG. 18). It is desirable to be. This is because if the ratio is ½ or more, the effect of suppressing oscillation appears significantly.
[0119]
Embodiment 10 FIG.
FIG. 19 is a plan sectional view of the semiconductor device according to the tenth embodiment. A circuit diagram and an external perspective view of the semiconductor device 110 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 19 is an XX cut line when the semiconductor device 101 of FIG. It corresponds to a cross-sectional view along the line.
[0120]
In each of the upper arm 10 and the lower arm 11, the wiring patterns 26 or 27 corresponding to two or more (two in the example of FIG. 19) IGBTs 3 connected in parallel are not divided for each corresponding IGBT 3 and are integrated. The semiconductor device 110 is characteristically different from the semiconductor device 108 according to the eighth embodiment in that it is connected to. Therefore, in each IGBT 3, the emitter pads 34 are not only connected through any of the conductor wires W1 to W4 and any of the wiring patterns 26 and 27, but also between the IGBTs 3 connected in parallel. The emitter pads 34 are connected to each other through their conductors. As a result, the effect of suppressing the oscillation of each IGBT 3 is further enhanced as compared with the semiconductor device 108 of the eighth embodiment.
[0121]
Further, in the semiconductor device 110, the IGBTs 3 are arranged so that the emitter pads 34 of the IGBTs 3 connected in parallel to each other are arranged in one direction, and the wiring patterns 26 and 27 are arranged in the arrangement of the corresponding emitter pads 34. Extends along the direction. For this reason, the conductor wires W1-W4 can be arrange | positioned easily.
[0122]
Embodiment 11 FIG.
FIG. 20 is a plan sectional view of the semiconductor device according to the eleventh embodiment. A circuit diagram and an external perspective view of the semiconductor device 111 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 20 is an XX cut line when the semiconductor device 101 of FIG. It corresponds to a cross-sectional view along the line.
[0123]
In each of the upper arm 10 and the lower arm 11, the wiring patterns 26 or 27 corresponding to two or more (two in the example of FIG. 19) IGBT3 connected in parallel are not divided for each corresponding IGBT3, and are integrated. However, the semiconductor device 111 is characteristically different from the semiconductor device 109 according to the ninth embodiment. For this reason, in each IGBT3, some emitter pads 34 are not only connected through any of the conductor wires W1 to W4 and any of the wiring patterns 26 and 27, but also of the IGBT3 connected in parallel. In the meantime, some of the emitter pads 34 are connected to each other through their conductors. For this reason, the effect of suppressing the oscillation of each IGBT 3 is further enhanced as compared with the semiconductor device 109 of the ninth embodiment. Further, regarding the point that the ratio of the emitter pads 34 to which any of the conductor wires W1 to W4 are connected among the plurality of emitter pads 34 included in each IGBT 3 is more preferably ½ or more, This is the same as the semiconductor device 109 of Embodiment 9.
[0124]
In the semiconductor device 111, two or more emitter pads 34 to which any one of the conductor wires W1 to W4 is connected among the plurality of emitter pads 34 included in each IGBT 3 are assigned relatively evenly. In the example of FIG. 20, the four emitter pads 34 to which any of the conductor wires W1 to W4 are connected are assigned to both ends and the center. The same applies to the semiconductor device 109 (FIG. 18). As a result, the potential equalization is more effectively achieved among the plurality of emitter pads 34 belonging to each IGBT 3, so that oscillation is more effectively suppressed.
[0125]
On the other hand, as in the semiconductor device 111a shown in FIG. 21, one of the conductor wires W1 to W4 is connected to the emitter pad 34 closest to each other between the IGBTs 3 connected in parallel to each other and adjacent to each other. Also good. In the example of FIG. 21, any one of the conductor wires W1 to W4 is connected to the three emitter pads 34 for each IGBT 3, but in general, any one of the conductor wires W1 to W4 is connected to one emitter pad 34. May be connected. When three or more IGBTs 3 are connected in parallel to each other, the conductor wires W1 to W4 are connected to at least two emitter pads 34 including the emitter pads 34 located at both ends of the IGBTs 3 excluding the IGBTs 3 located at both ends. One of them is connected.
[0126]
Also in the semiconductor device 111a, some of the emitter pads 34 in each IGBT 3 are not only connected through any one of the conductor wires W1 to W4 and any one of the wiring patterns 26 and 27, but are also connected in parallel. Even between the IGBTs 3, some of the emitter pads 34 are connected to each other through their conductors. For this reason, the effect of suppressing the oscillation of the IGBT 3 can be obtained accordingly. In particular, the length of the wiring pattern 26 or 27 along the arrangement direction of the plurality of IGBTs 3 connected in parallel to each other can be kept small. This contributes to miniaturization of the semiconductor device 111a.
[0127]
Also in the semiconductor device 111a, as in the semiconductor devices 109 and 111, among the plurality of emitter pads 34 included in each IGBT 3, the ratio occupied by the emitter pad 34 to which any of the conductor wires W1 to W4 is connected is 1 It is more desirable that it is at least / 2. In the example of FIG. 21, the ratio is set to 1/2.
[0128]
Embodiment 12 FIG.
FIG. 22 is a plan sectional view of a semiconductor device according to the twelfth embodiment. A circuit diagram and an external perspective view of the semiconductor device 112 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 22 is a sectional view taken along line XX when the semiconductor device 101 in FIG. It corresponds to a cross-sectional view along the line.
[0129]
The wiring patterns 26 and 27 are not provided, and a part of the plurality of emitter pads 34 included in each IGBT 3, and two or more (four in the example of FIG. 22) emitter pads 34 are connected to the conductor wires W1 to W4. The semiconductor device 112 is characteristically different from the semiconductor device 109 according to the ninth embodiment in that the semiconductor device 112 is directly connected by any of the above. Also in the semiconductor device 112, as in the semiconductor device 109, a conductor (that is, two or more) of the plurality of emitter pads 34 included in each IGBT 3 does not relay the wiring patterns 22, 23 (that is, two or more emitter pads 34). , Any one of the conductor wires W1 to W4), the effect of suppressing oscillation when the IGBT 3 is short-circuited can be obtained accordingly. As in the semiconductor device 109 of the ninth embodiment, the ratio of the emitter pads 34 to which any of the conductor wires W1 to W4 is connected among the plurality of emitter pads 34 included in each IGBT 3 is 1/2 or more. It is more desirable.
[0130]
Since the semiconductor device 112 does not require the wiring patterns 26 and 27, the manufacturing process is facilitated, the area of the substrate 2 can be reduced, and the semiconductor device 112 can be downsized. Further, since each of the conductor wires W1 to W4 is connected only to a part of the plurality of emitter pads 34 included in each IGBT 3, even when the width of each emitter pad 34 is narrow, the conductor wires W1 to W4 are connected as emitters. It can be easily connected to the pad 34.
[0131]
Moreover, as FIG. 22 shows, each of the conductor wires W1-W4 is arrange | positioned along the sequence direction of the several emitter pad 34 of each IGBT3. As a result, the conductor wires W1 to W4 are approximately orthogonal to the conductor wire 15. Thereby, the inductive coupling between the conductor wire 15 and the conductor wires W1 to W4 is suppressed low, and the effect of suppressing oscillation is further enhanced.
[0132]
Further, for each IGBT 3, the conductor wires W <b> 1 to W <b> 4 are connected to two or more emitter pads 34 at a portion farther from the wiring pattern 22 or 23 than one end of the conductor wire 15. For this reason, the inductive coupling between the conductor wire 15 and the conductor wires W1 to W4 is further suppressed, and thereby the effect of suppressing oscillation is further enhanced. Furthermore, the conductor wire 15 and the conductor wires W1 to W4 can be easily arranged without interfering with each other.
[0133]
Although FIG. 22 shows an example in which two IGBTs 3 are connected in parallel, three or more IGBTs 3 may be connected in parallel. Each of the upper arm 10 and the lower arm 11 may include only a single IGBT 3. In either case, since a part of the plurality of emitter pads 34 of each IGBT 3 is electrically connected to each other through a conductor that does not relay the wiring patterns 22 and 23, the effect of suppressing the oscillation of the IGBT 3 is correspondingly achieved. can get.
[0134]
Embodiment 13 FIG.
FIG. 23 is a plan sectional view of a semiconductor device according to the thirteenth embodiment. A circuit diagram and an external perspective view of the semiconductor device 113 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 23 is a sectional view taken along line XX when the semiconductor device 101 of FIG. It corresponds to a cross-sectional view along the line.
[0135]
The semiconductor device 113 is characteristically different from the semiconductor device 112 according to the twelfth embodiment in that all of the plurality of emitter pads 34 included in each IGBT 3 are connected to each other by any of the conductor wires W1 to W4. . For this reason, in the semiconductor device 113, the oscillation of each IGBT 3 is more effectively suppressed.
[0136]
Embodiment 14 FIG.
FIG. 24 is a plan sectional view of a semiconductor device according to the fourteenth embodiment. A circuit diagram and an external perspective view of the semiconductor device 114 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 24 is a sectional view taken along line XX when the semiconductor device 101 of FIG. It corresponds to a cross-sectional view along the line.
[0137]
All of the plurality of emitter pads 34 included in each IGBT 3 are not only connected to each other by the conductor wire W1 or W3, but also between two or more (two in the example of FIG. 25) IGBTs 3 connected in parallel to each other. The semiconductor device 114 is characteristically different from the semiconductor device 113 according to the thirteenth embodiment in that the emitter pads 34 are connected to each other by conductor wires W1 or W3. Therefore, in semiconductor device 114, the effect of suppressing the oscillation of each IGBT 3 is further enhanced as compared with semiconductor device 113 in the thirteenth embodiment. Further, since all the emitter pads 34 are arranged in one direction between two or more IGBTs 3 connected in parallel to each other, the conductor wires W1 and W3 can be easily arranged along the one direction. .
[0138]
Embodiment 15 FIG.
FIG. 25 is a plan sectional view of a semiconductor device according to the fifteenth embodiment. A circuit diagram and an external perspective view of the semiconductor device 115 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 25 is an XX section line when the semiconductor device 101 of FIG. It corresponds to a cross-sectional view along the line.
[0139]
A part of the plurality of emitter pads 34 included in each IGBT 3 is not only connected by the conductor wire W1 or W3, but also between two or more (two in the example of FIG. 25) IGBTs 3 connected in parallel to each other. The semiconductor device 115 is characteristically different from the semiconductor device 112 according to the twelfth embodiment in that the emitter pads 34 are connected to each other by conductor wires W1 or W3. Therefore, the effect of suppressing the oscillation of each IGBT 3 is further enhanced as compared with the semiconductor device 112 of the twelfth embodiment.
[0140]
Embodiment 16 FIG.
FIG. 26 is a plan sectional view of the semiconductor device according to the sixteenth embodiment. A circuit diagram and an external perspective view of this semiconductor device 116 are the same as those in FIG. 1 and FIG. 2 of the first embodiment, and FIG. 26 is a sectional view taken along line XX when the semiconductor device 101 in FIG. It corresponds to a cross-sectional view along the line.
[0141]
The semiconductor device 116 is characteristically different from the conventional semiconductor device 150 in that each of the plurality of emitter pads 34 included in each IGBT 3 is connected to the wiring pattern 22 or 23 through only one conductor wire 15. ing. For this reason, even when an excessive short circuit current flows through each IGBT 3 due to a short circuit of the load of the semiconductor device 116, the magnitude of the emitter current flowing through each IGBT 3 is limited by the resistance of the conductor wire 15. The oscillation phenomenon at the potential of the gate electrode of each IGBT 3 is suppressed. In addition, since the plurality of emitter pads 34 of each IGBT 3 are arranged along one direction and the corresponding wiring pattern 22 or 23 extends along the one direction, the plurality of conductor wires 15 are connected to each other. It can be easily arranged without interference.
[0142]
Embodiment 17. FIG.
FIG. 27 is a cross-sectional plan view of the semiconductor device according to the seventeenth embodiment. A circuit diagram and an external perspective view of the semiconductor device 117 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 27 is an XX cut line when the semiconductor device 101 of FIG. It corresponds to a cross-sectional view along the line.
[0143]
The semiconductor device 117 is characteristically different from the semiconductor device 116 according to the sixteenth embodiment in that an intermediate portion of each conductor wire 15 connected to each IGBT 3 is connected to the anode electrode of the corresponding diode 4. Yes. For this reason, in the semiconductor device 117, it is not necessary to separately provide a conductor wire for connecting between the corresponding IGBT 3 and the diode 4. That is, the number of conductor wires in the entire semiconductor device 117 can be reduced, and the number of manufacturing steps and manufacturing costs can be reduced.
[0144]
Modified example.
(1) In each of the embodiments described above, an example in which the semiconductor device includes the IGBT 3 has been described. In addition, it can be widely applied to semiconductor devices including a switching element having a control electrode that controls a main current in response thereto. The switching element may be a MOSFET or a bipolar transistor, for example. In a general switching element, the gate wiring 32 is extended to the control electrode wiring, the gate pad 33 is extended to the bonding pad of the control electrode, and the emitter pad 34 is extended to the bonding pad of the main electrode.
[0145]
However, although the semiconductor devices 101 to 117 according to the respective embodiments use the IGBT 3 that is an insulated gate type switching element that originally tends to oscillate, the oscillation can be suppressed and control is easy. By taking advantage of the insulated gate switching element, it can be widely used for application devices that control a large current. In addition, since an insulating gate type switching element has a high necessity for protection of a gate insulating film, the present invention is particularly useful also in that sense.
[0146]
(2) Generally, the emitter electrodes (generally main electrodes) of the plurality of IGBTs 3 (generally a plurality of switching elements) are not relayed between the wiring patterns 22 (or 23) through which the emitter current (generally the main current) flows. If any electrically connected conductor is provided, the uniformity of the potential of the emitter electrode (generally, the main electrode) can be increased similarly to the semiconductor devices 101 to 107, thereby suppressing the oscillation phenomenon. be able to. In semiconductor devices 101 and 102, wiring pattern 26 (or 27) and conductor wires W1, W2 (or W3, W4) correspond to conductors, and in semiconductor device 103, conductor wire W5 (or W6) corresponds to a conductor. To do.
[0147]
【The invention's effect】
In the apparatus of the first invention, the other main electrodes of the plurality of switching elements connected in parallel to each other are electrically connected to each other through a conductor that does not relay the second wiring pattern, that is, a conductor that does not flow a main current. Therefore, the potential of the other main electrode is made uniform among the plurality of switching elements. As a result, even when the loads of the plurality of switching elements are short-circuited, the oscillation phenomenon at the potentials of the control electrodes of the plurality of switching elements is suppressed.
[0148]
In addition, the first In the apparatus of the invention, electrical connection between the other main electrodes of the plurality of switching elements is easily realized through the third wiring pattern and the second conductor wire. In addition, since it is not necessary to cut the wire on the switching element in the step of disposing the second conductor wire, there is no need for a means for preventing the switching element from being damaged.
[0149]
In addition, the first In the apparatus of the invention, the second and third wiring patterns are disposed on opposite sides of the plurality of switching elements and extend along the arrangement direction of the plurality of switching elements. The conductor wire and the second conductor wire can be easily arranged without interfering with each other. Furthermore, the inductive coupling between the first conductor wire and the second conductor wire can be reduced, thereby enhancing the effect of suppressing oscillation.
[0150]
In addition, the first In the apparatus according to the invention, the third wiring pattern is adjacent to the plurality of switching elements without interposing another wiring pattern, so that the second conductor wire can be set short. Thereby, since the inductance of the conductor that electrically connects the other main electrodes of the plurality of switching elements is reduced, the effect of equalizing the potential of the other main electrode can be enhanced.
[0151]
Second In the apparatus of the invention, since the third wiring pattern has a repeated bent portion, the inductance of the conductor that electrically connects the other main electrodes of the plurality of switching elements is set to an optimum value for suppressing oscillation. Can be adjusted.
[0155]
Third In the apparatus of the invention, since the voltage clamp element is interposed between the control electrode of the plurality of switching elements and the third wiring pattern, even if the oscillation phenomenon of the potential of the control electrode occurs, the amplitude can be suppressed low. .
[0161]
4th In the device according to the invention, each of the plurality of switching elements is an insulated gate type switching element that inherently tends to oscillate, but its oscillation is suppressed, so that the control is easy. Taking advantage of the switching element, it can be widely used for application devices that control a large current.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an apparatus according to a first embodiment.
FIG. 2 is an external perspective view of the apparatus according to the first embodiment.
FIG. 3 is a plan sectional view of the apparatus according to the first embodiment.
FIG. 4 is a plan sectional view of the apparatus according to the second embodiment.
FIG. 5 is a plan sectional view of the apparatus according to the third embodiment.
FIG. 6 is a plan sectional view of the apparatus according to the fourth embodiment.
FIG. 7 is a plan sectional view of an apparatus according to a fifth embodiment.
FIG. 8 is a circuit diagram of a part of the apparatus according to the fifth embodiment.
FIG. 9 is a plan sectional view of the apparatus according to the sixth embodiment.
FIG. 10 is a schematic diagram of a part of the apparatus according to the sixth embodiment.
FIG. 11 is a circuit diagram of a part of the apparatus according to the sixth embodiment.
12 is a plan sectional view of an apparatus according to Embodiment 7. FIG.
FIG. 13 is a schematic diagram of a part of the apparatus according to the seventh embodiment.
FIG. 14 is a schematic diagram of a part of the apparatus according to the seventh embodiment.
FIG. 15 is a circuit diagram of a part of the apparatus according to the seventh embodiment.
FIG. 16 is a plan view of the IGBT according to each embodiment;
FIG. 17 is a plan sectional view of an apparatus according to an eighth embodiment.
FIG. 18 is a plan sectional view of an apparatus according to the ninth embodiment.
FIG. 19 is a plan sectional view of the apparatus according to the tenth embodiment.
FIG. 20 is a plan sectional view of the apparatus according to the eleventh embodiment.
FIG. 21 is a plan sectional view of an apparatus according to another example of the eleventh embodiment.
FIG. 22 is a plan sectional view of the apparatus according to the twelfth embodiment.
FIG. 23 is a plan sectional view of the apparatus according to the thirteenth embodiment.
FIG. 24 is a plan sectional view of the apparatus according to the fourteenth embodiment.
FIG. 25 is a plan sectional view of the apparatus according to the fifteenth embodiment.
FIG. 26 is a plan sectional view of the apparatus of the sixteenth embodiment.
FIG. 27 is a plan sectional view of the apparatus according to the seventeenth embodiment.
FIG. 28 is a plan sectional view of a conventional apparatus.
[Explanation of symbols]
2 substrate, 3 IGBT (switching element), 4 diode, 15 conductor wire (first conductor wire), 17 conductor wire (fourth conductor wire), 21 wiring pattern (first wiring pattern), 22 wiring pattern (first wiring) Pattern, second wiring pattern), 23 wiring pattern (second wiring pattern), 23a first portion, 23b second portion, 24, 25 wiring pattern (fourth wiring pattern), 26, 27 wiring pattern (third wiring pattern) ), 30 Voltage clamp element, 32 Gate wiring (control electrode wiring), 34 Emitter pad (bonding pad), 40, 41 Slit, 50, 51 Conductor wire (fifth conductor wire), EE, OUT External terminal, S1, S2 External terminal, W1-W4 conductor wire (second conductor wire), W5-W10 conductor wire (third conductor wire)

Claims (4)

A substrate having a main surface;
A first wiring pattern and a second wiring pattern which are electrically insulated from each other and disposed on the main surface;
A plurality of switching elements in which one main electrode is electrically connected to each other by being disposed on the first wiring pattern ;
Is pre SL one end connected to the other main electrode of the plurality of switching elements, a plurality of first conductor wire whose other end is connected to said second wiring pattern,
An external terminal connected to the second wiring pattern and electrically connecting the other main electrode of the plurality of switching elements and the outside through the second wiring pattern;
The other main electrode each other of the plurality of switching elements, and a conductor which electrically connects without relaying the second wiring pattern, a semiconductor device Ru provided with,
The conductor is
A third wiring pattern isolated from the first wiring pattern and the second wiring pattern, electrically insulated from the first wiring pattern and the second wiring pattern, and disposed on the main surface; ,
A plurality of second conductor wires having one end connected to the other main electrode of the plurality of switching elements and the other end connected to the third wiring pattern;
The second wiring pattern extends along an arrangement direction of the plurality of switching elements;
The third wiring pattern extends along the arrangement direction of the plurality of switching elements on the opposite side of the second wiring pattern across the plurality of switching elements,
Further, the semiconductor device , wherein the third wiring pattern is adjacent to the plurality of switching elements without sandwiching another wiring pattern . It has a bent portion to which the third wiring pattern is repeated, the semiconductor device according to claim 1. A fourth wiring pattern electrically insulated from the first wiring pattern, the second wiring pattern, and the third wiring pattern and disposed on the main surface;
A plurality of fourth conductor wires having one end connected to the control electrodes of the plurality of switching elements and the other end connected to the fourth wiring pattern;
The semiconductor device according to claim 1, further comprising: a voltage clamp element having one end connected to the third wiring pattern and the other end connected to the four wiring patterns . 4. The semiconductor device according to claim 1, wherein each of the plurality of switching elements is an insulated gate switching element . 5.

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