JP7099075B2 - Semiconductor module - Google Patents

Description

The present invention includes a high-potential side semiconductor switching element, a low-potential side switching element, and a drive circuit for driving these switching elements, and the reference potential of the high-potential side semiconductor switching element and the reference potential of the drive circuit are connected. Regarding the semiconductor module of the configuration.

Inverter devices widely used for driving consumer and industrial motors have semiconductor switching elements such as MOSFETs and IGBTs, and drive circuits that drive the semiconductor switching elements. In addition, as a means for miniaturizing equipment and incorporating a protection circuit, the Intelligent Power Module (hereinafter, also referred to as "IPM"), which is a semiconductor module in which the above-mentioned semiconductor switching element and drive circuit are packaged into one, is used. Has been done. Hereinafter, a case where an IGBT is used as the semiconductor switching element will be described.

FIG. 1 is an IPM three-phase inverter circuit. In this figure, IPM1 is a high potential side IGBT 2u, 2v, 2w and a high potential side freewheeling diode (hereinafter, also referred to as “FWD”) 4u, 4v, 4w connected in antiparallel between these collectors and emitters, respectively. , Low potential side IGBT3u, 3v, 3w and low potential side FWD5u, 5v, 5w connected in antiparallel between these collectors and emitters, respectively. Further, the IPM1 is a drive circuit for driving the high potential side IGBTs 2u, 2v, 2w (hereinafter, also referred to as “HVIC”) 6u, 6v, 6w and a drive circuit for driving the low potential side IGBTs 3u, 3v, 3w, respectively (hereinafter, also referred to as “HVIC”). , Also referred to as "LVIC") 7.

In FIG. 1, the emitters (E) serving as the reference potentials of the high potential side IGBTs 2u, 2v, 2w and the reference potentials (Vs) of the HVIC 6u, 6v, 6w are the bonding wires 8u, 8v, 8w as shown in the reference example of FIG. Connected by. Note that FIG. 9 shows the U-phase circuit as a representative of the three-phase circuits. Generally, this bonding wire is wired so that the wire length is short.

In the inverter device of IPM1, power conversion is performed by alternately performing turn-on / turn-off operation of high-potential side IGBT2u, 2v, 2w and low-potential side IGBT3u, 3v, 3w, so that the turn-on / turn-off operation is performed as shown in FIG. Sometimes switching loss occurs. In FIG. 10, FIG. 10A is a waveform of a voltage (VCE) between a collector and an emitter at the time of turn-on and turn-off of a general switching element, and FIG. 10B is a waveform of a collector current (IC) of the IGBT. Represents. At this time, as shown in FIG. 10 (c), a switching loss occurs at the timing when the VCE and the IC overlap at the time of turn-on / turn-off (hatched portion in the same figure).

Generally, in the turn-on / turn-off operation, the IGBT charges and discharges the charge of the parasitic capacitance between the gate and the collector, and a period in which the voltage between the gate and the emitter (gate voltage with respect to the reference potential) becomes flat occurs. Hereinafter, this period is referred to as a "mirror period".

The mirror period is shown in FIG. FIG. 11A is a waveform of the voltage VCE at the turn-off of the IGBT in the conventional circuit, FIG. 11B is a waveform of the current IC at this time, and FIG. 11C is a waveform of the gate voltage VGE. As shown in FIG. 11 (c), the period (t1 to t2) in which the gate voltage VGE is flat is the mirror period.

On the other hand, as shown in FIG. 12, generally, the inductance La between the emitter of the high potential side IGBT 2u, 2v, 2w and the reference potential of the HVIC 6u, 6v, 6w is the reference potential of the emitter of the low potential side IGBT 3u, 3v, 3w and the LVIC 7. It is smaller than the inductance Lb of the wiring between them. Therefore, as shown in FIG. 13B, the time change rate di / dt of the collector current at the turn-off of the high potential side IGBTs 2u, 2v, 2w is steeper than that of the low potential side IGBT3u, 3v, 3w.

Assuming that the DC power supply voltage is VDC and the parasitic inductance of wiring or the like is L, the jump voltage VCE (surge) is generally expressed by the following equation.
VCE (surge) = VDC + L ・ di / dt

Therefore, as shown in FIG. 13A, when the high potential side IGBTs 2u, 2v, 2w are turned off, the jump voltage VCE (surge) applied between the collectors and emitters of the IGBTs 2u, 2v, 2w also becomes large. When this jump voltage VCE (surge) exceeds the withstand capacity of the IGBT, it causes avalanche destruction. In FIG. 13, the waveform of the circuit on the high potential side is shown by a solid line, and the waveform of the circuit on the low potential side is shown by a broken line.

As a method for dealing with the destruction of the avalanche, for example, as shown in Patent Document 1, the resistance value of the gate resistance Rg of the IGBT is increased, the slope of the di / dt is made gentle, and the jumping of the VCE (surge) is suppressed. The method has been known conventionally.

However, when the value of the gate resistance Rg of the IGBT is increased, as shown in FIG. 14, the mirror period in which the voltage between the gate and the emitter becomes flat becomes longer. This causes a problem that the switching loss increases.

Further, in Patent Document 2, in a modular element having a MOS gate type semiconductor chip such as an IGBT inside, an inductance is inserted between the emitter of the semiconductor chip and the emitter terminal of the modular element, and VCE (surge) jumps up. The technology to suppress the above is disclosed. However, Patent Document 2 targets a single semiconductor chip, and does not mention how to suppress the jumping of VCE (surge) in a circuit in which freewheeling diodes are connected in antiparallel connection.

Further, in Patent Document 3, "wiring between the emitter of the high potential side semiconductor switch and the collector of the low potential side semiconductor switch" and "wiring to the gate for driving the low potential side semiconductor switch" are magnetically described. Described is a power conversion device that suppresses a turn-on current by suppressing a gate-emitter voltage Vge of a low-potential side semiconductor switch by coupling to obtain a counter electromotive force. However, Patent Document 3 aims to suppress the turn-on current of the semiconductor switch on the low potential side, and at the time of turn-off, a counter electromotive force is generated so as to increase Vge, so that the slope of −di / dt is steep. There is a problem that VCE (surge) increases.

Japanese Unexamined Patent Publication No. 2002-153043 International Publication No. 98/5546 Pamphlet Japanese Patent No. 6065744

The present invention has been made in view of the above circumstances, and in a semiconductor module having a freewheeling diode, a semiconductor capable of suppressing a jump voltage at turn-off without increasing a switching loss generated during a mirror period. The purpose is to provide a module.

In order to achieve the above object, in the semiconductor module of the present invention, the high potential side switching element (2u, 2v, 2w) and the low potential side switching element (3u, 3v, 3w) forming the upper arm and the lower arm, respectively, Freewheeling diodes (4u, 4v, 4w, 5u, 5v, 5w) connected in antiparallel to each of these switching elements, and a high potential that drives the high potential side switching element and the low potential side switching element on and off. A semiconductor module (1) including a side drive circuit (6u, 6v, 6w) and a low potential side drive circuit (7).
In the upper arm, the anode electrode of the freewheeling diode (4u, 4v, 4w) and the reference potential electrode (Vs) of the high potential side drive circuit (6u, 6v, 6w) are connected to the first wiring (9u, 9v, 9w). ) Directly connected,
The anode electrode of the freewheeling diode (4u, 4v, 4w) is electrically connected to the reference potential electrode of the high potential side switching element via a second wiring (11u, 11v, 11w) having an inductance. It is characterized by that.

In the present invention, in a semiconductor module in which the anode electrode of the freewheeling diode (FWD) and the reference potential electrode of the high potential side switching element are connected by wiring, the anode electrode of the freewheeling diode and the reference potential electrode of the high potential side drive circuit are directly connected. Wire connection.

As a result, the jump voltage at the time of turn-off can be suppressed by utilizing the inductance of the wiring (the second wiring) between the anode of the freewheeling diode and the reference potential of the high potential side switching element.

Here, the "reference potential of the switching element" means a portion that is a reference potential for operating the switching element and has the same potential as the reference potential of the drive circuit for operating the switching element. The term "directly connected" includes not only the case of being directly connected to the terminal of the electrode, but also the case of being pulled out in the vicinity of the terminal and being connected via a circuit pattern having the same potential as the terminal. Further, "electrically connected" means that it is sufficient if the electric conduction is electrically conducted, and the case where the physical connection is directly made is included.

As the inductance of the second wiring, the parasitic inductance of the wiring may be used. Further, by using the bonding wire as the first wiring, it is possible to easily adjust the inductance of the first wiring.

Further, the semiconductor module of the present invention includes a high potential side switching element and a low potential side switching element forming an upper arm and a lower arm, respectively, a freewheeling diode connected in antiparallel to these switching elements, and the high potential side. A semiconductor module including a high-potential side drive circuit and a low-potential side drive circuit for turning on / off a switching element and the low-potential side switching element.
In the upper arm, the anode electrode of the freewheeling diode and the reference potential electrode of the high potential side drive circuit are directly connected by a first wiring having an inductance.
The anode electrode of the freewheeling diode is directly connected to the reference potential electrode of the high potential side switching element via a second wiring having an inductance.
The first wiring and the second wiring are provided so that magnetic coupling occurs between the first wiring and the second wiring when the high potential side switching element is driven on and off. It is characterized by being.

In particular, the present invention is characterized in that the first wiring and the second wiring are arranged so that a current flows in the same phase and a counter electromotive force is generated by magnetic coupling.

In the present invention, the first wiring connecting the anode electrode of the freewheeling diode and the reference potential electrode of the high potential side drive circuit, and the second wiring connecting the anode electrode of the freewheeling diode and the reference potential electrode of the high potential side switching element. Is magnetically coupled to the wiring of the above in phase with the current, and a counter electromotive force is generated on the first wiring side via the second wiring when the high potential side switching element is turned off. Then, the gate drive capability of the high potential side switching element is reduced by utilizing this counter electromotive force, and the effect of suppressing the jump voltage VCE (surge) at the time of turn-off is enhanced.

If the currents of the first wiring and the second wiring are wired so as to flow in the same phase, the first wiring connects the anode electrode of the freewheeling diode and the reference potential electrode of the high potential side drive circuit. Alternatively, the reference potential electrode of the high potential side switching element and the reference potential electrode of the high potential side drive circuit may be connected.

Preferably, the first wiring and the second wiring are wires, and it is preferable to bond them on a wiring pattern having the same potential as the reference potential of the switching element.

According to the semiconductor module of the present invention, in the semiconductor module having a freewheeling diode, it is possible to suppress the jump voltage at the time of turn-off without increasing the switching loss generated during the mirror period.

It is a circuit diagram of the semiconductor module (IPM) by the conventional and the embodiment of this invention. It is the main part connection diagram (FIG. 2 (a)) and the circuit diagram (FIG. 2 (b)) of the main part of the IPM of Example 1 in the 1st Embodiment of this invention. It is a waveform comparison diagram of the voltage VCE, the current IC, and the gate voltage VGE at the time of turn-off of the high potential side IGBT of the IPM according to the reference example and the first embodiment. It is a circuit diagram of the IGBT of Example 2 (comparative example with FIG. 2). 2 is an explanatory diagram of the difference in the effect of the circuit configuration shown in FIGS. 2 and 4, FIG. 5A is a diagram showing a reverse recovery current path in the circuit configuration of FIG. 4, and FIG. 5B is a diagram of FIG. It is a figure which shows the reverse recovery current path at the time of a circuit configuration. It is the main part connection diagram (FIG. 6 (a)) and the circuit diagram (FIG. 6 (b)) of the main part of the IPM of Example 3 in the 2nd Embodiment of this invention. It is explanatory drawing of the action effect of Example 3. FIG. It is a waveform comparison diagram of the voltage VCE, the current IC, and the gate voltage VGE at the time of turn-off of the high potential side IGBT of the IPM according to the reference example, the first embodiment, and the third embodiment. It is the main part connection diagram (FIG. 9 (a)) and the circuit diagram (FIG. 9 (b)) of the main part of IPM by a reference example. It is explanatory drawing of the switching loss at the time of turn-on and turn-off of an IGBT which is a general switching element, FIG. 10A is a waveform diagram of the voltage (VCE) between the collector and emitter of an IGBT, and FIG. The waveform diagram of the collector current (IC) of the above, FIG. 10 (c) is an explanatory diagram of the generation range of the switching loss. 11 (a) is a waveform diagram of the voltage VCE at the turn-off of the IGBT, FIG. 11 (b) is a waveform diagram of the current ICE at this time, and FIG. 11 (c) is a gate voltage VGE. It is a figure which shows the waveform and the mirror period of. It is a conceptual explanatory diagram of the parasitic inductance of the wiring from the emitter of the IGBT. It is a waveform diagram of the voltage VCE at the time of turn-off of the high potential side IGBT and the low potential side IGBT (FIG. 13 (a)), and the waveform diagram of the current IC (FIG. 13 (b)). It is a figure which shows the relationship between the magnitude of a gate resistance Rg, the jump voltage at the time of an IGBT turn-off, and the mirror period.

Hereinafter, the first embodiment of the present invention will be described with reference to the drawings. Since the entire circuit of the semiconductor module (IPM) 1 according to the present embodiment is represented by FIG. 1 as in the conventional case, the description thereof is omitted. Further, since the following description relates to the circuit on the high potential side, the description of high potential / low potential is omitted.

(Example 1)
FIG. 2A shows the wiring configuration inside the module of IPM1 according to the first embodiment, and FIG. 2B shows the circuit configuration. It should be noted that although FIG. 2 shows the U-phase circuit as a representative of the three phases, it goes without saying that the same can be applied to other phases.

As shown in FIG. 2A, the IPM1 arranges the HVIC6u (6v, 6w) and the external terminal U (V, W) on the insulating substrate, and the IGBT 2u (2v, 2w) and the FWD4u (4v, 4w) are arranged between them. ) Are arranged in order from HVIC6u (6v, 6w).

The reference potential Vs of the HVIC 6u (6v, 6w) and the anode of the FWD 4u (4v, 4w) are connected by a bonding wire 9u (9v, 9w). Further, the output OUT of the HVIC 6u (6v, 6w) is connected to the gate of the IGBT 2u (2v, 2w) by a bonding wire 10u (10v, 10w). The emitter of the IGBT 2u (2v, 2w) and the anode of the FWD4u (4v, 4w) are connected by a bonding wire 11u (11v, 11w), and the anode of the FWD4u (4v, 4w) and the external terminal U (V, W) are bonded wires. It is connected by 12u (12v, 12w). Further, the collector of the IGBT 2u (2v, 2w) and the cathode of the FWD4u (4v, 4w) are connected by a circuit pattern 16u (16v, 16w). In FIG. 2A, two bonding wires 11u (11v, 11w) and 12u (12v, 12w) are provided in parallel, but any number of bonding wires can be provided depending on the current capacity of the wires.

Each bonding wire, IGBT element, and FWD element has the inductance shown in FIG. 2 (b). In FIG. 2B, Li and Lf are the internal inductances of the IGBT 2u (2v, 2w) and FWD4u (4v, 4w), respectively, and L2 is between the emitter of the IGBT 2u (2v, 2w) and the anode of the FWD4u (4v, 4w). The wiring inductance of the bonding wire 11u (11v, 11w) and L4 represent the wiring inductance of the bonding wire 12u (12v, 12w) to the external terminal U (V, W) of the IPM1. Further, L1'is the wiring inductance of the bonding wire 9u (9v, 9w) between the FWD4u (4v, 4w) anode and the reference potential of the HVIC6u (6v, 6w).

Next, the action and effect of the connection configuration of the semiconductor module (IPM) 1 will be described with reference to the reference example of FIG.

In the connection configuration of the IPM1 of the present embodiment shown in FIG. 2, the inductance between the emitter E, which is the reference potential of the IGBT 2u (2v, 2w), and the reference potential Vs of the HVIC6u (6v, 6w) is Li + L2 + L1'. On the other hand, in the connection configuration of the reference example shown in FIG. 9, the inductance between the emitter E of the IGBT 2u (2v, 2w) and the reference potential Vs of the HVIC 6u (6v, 6w) is Li + L1. Normally, L1 and L1'are almost the same value, or as shown in FIG. 2A, the IGBT 2u (2v, 2w) is arranged between the HVIC6u (6v, 6w) and the FWD4u (4v, 4w). Below, L1'has a larger value. Therefore, in the formation configuration according to the present embodiment, the inductance between the emitter E of the IGBT 2u (2v, 2w) and the reference potential Vs of the HVIC 6u (6v, 6w) is larger than that of the reference example by at least the inductance L2. That is, in the connection configuration of this embodiment as compared with the reference example, a larger back electromotive force is generated by at least the amount of the inductance L2 due to −di / dt at the time of the IGBT turn-off, and the gate of the IGBT 2u (2v, 2w) is generated. Will be biased. As a result, in this embodiment, the slope of di / dt at the time of IGBT turn-off becomes gentler than that in the reference example, and the effect of suppressing the jump voltage can be enhanced by that amount.

Incidentally, since the electromotive force due to the inductance component L can be calculated by L · di / dt, a bonding wire having a wiring inductance in which the inductance L2 is 5 to 10 nH is used when di / dt = 1000 A / μs. Then, the effect of suppressing the jumping voltage of about 5 to 10 V can be obtained.

FIG. 3 shows the time change waveforms of the voltage VCE, the current IC, and the voltage VGE at the turn-off of the IGBT 2u (2v, 2w) in the connection configuration of this embodiment in comparison with the reference example. In FIG. 3, the solid line is the waveform of this embodiment, and the broken line is the waveform of the reference example. As shown in FIG. 3A, the peak value of the jump voltage VCE (surge) of the circuit according to this embodiment was lower than the peak value of the jump voltage VCE (surge) according to the circuit of the reference example. That is, in the circuit according to this embodiment, the dV / dt from t1 to t2 (mirror period) and thereafter to t3 are the same as those in the reference example, and the subsequent jump voltage VCE (surge) can be suppressed.
Further, as shown in FIG. 3B, the slope of di / dt in this embodiment is gentler than that in the reference example. Further, as shown in FIG. 3C, the mirror periods (t1 to t2) of both circuits are the same.

As described above, according to the connection configuration of the semiconductor module (IPM) according to the present embodiment, the resistance of the gate resistance Rg of the IGBT in the circuit configuration in which the freewheeling diode (FWD) is connected in antiparallel to the switching element (IGBT). Since the inductance component on the emitter side of the IGBT is increased without changing the value, the mirror period does not become long, and the jumping voltage VCE (surge) is suppressed while maintaining the switching loss during the mirror period at the same level as before. can do.

In the connection configuration of FIG. 2, the anode electrode of FWD4u (4v, 4w) and the reference potential electrode of HVIC6u (6v, 6w) can be directly connected by using the bonding wire 9U (9v, 9w). As a result, by using the bonding wire whose inductance value (L1') is adjusted, the inductance Li + L2 + L1'between the emitter of the IGBT 2u (2v, 2w) and the reference potential of the HVIC 6u (6v, 6w) is sufficiently larger than before. As a value, the slope of di / dt at the time of IGBT turn-off can be adjusted to a desired value more gradual than before. The inductance L1'between the anode of the FWD4u (4v, 4w) and the reference potential of the HVIC6u (6v, 6w) may be inserted through an inductor, but the parasitic inductance of the wire can also be used.

In particular, in the configuration in which the IGBT2u (2v, 2w) is arranged between the HVIC6u (6v, 6w) and the FWD4u (4v, 4w) as shown in FIG. 2, the reference potential terminal (Vs) of the HVIC6u (6v, 6w) is arranged. By directly connecting the anode terminal of FWD4u (4v, 4w) with the bonding wire 9U (9v, 9w), the parasitic inductance (L1') of the bonding wire increases, so that the jump voltage VCE (surge) can be easily increased. It can be suppressed.

In addition, by connecting the emitter electrode of the IGBT 2u (2v, 2w) and the anode electrode of the FWD4u (4v, 4w) using a bonding wire, not only the inductance L1'but also the inductance L2 can be adjusted.

(Example 2)
FIG. 2 shows a configuration in which the reference potential electrode of HVIC6u (6v, 6w) and the anode electrode of FWD4u (4v, 4w) are directly wire-bonded. As shown in FIG. 4, the emitter of IGBT2u (2v, 2w) is used. An external inductance Lex can also be inserted between the electrode and the reference potential of HVIC6u (6v, 6w). In the case of the circuit configuration of FIG. 4, the inductance between the emitter E, which is the reference potential of the IGBT 2u (2v, 2w), and the reference potential Vs of the HVIC 6u (6v, 6w) is Li + Lex + L1. That is, the inductance component on the emitter side of the IGBT 2u (2v, 2w) is larger by (Lex) than the circuit configuration according to the reference example shown in FIG. The bias of the IGBT gate becomes larger by that amount, and di / dt can be suppressed.

As described above, even in the wiring configuration shown in FIG. 4, it is possible to increase only the inductance component on the emitter side without changing the resistance value of the gate resistance Rg of the IGBT, as in the wiring configuration of FIG. Therefore, also in this embodiment, it is possible to suppress the jump voltage VCE (surge) at the time of turn-off without increasing the loss generated during the mirror period.

By the way, in the connection configuration of FIG. 4, the reverse recovery current is larger than that of the connection configuration of FIG. Here, the reverse recovery current is a current that flows at the moment when the voltage applied to the freewheeling diode (FWD) is switched from the forward voltage to the reverse voltage, and its magnitude is in the current path of the freewheeling diode (FWD). It depends on the inductance that exists.

The inductance at the time of reverse recovery current according to the circuit configuration of FIG. 4 is Lf + L2 + Lex + L4 as shown in FIG. 5A. On the other hand, the inductance at the time of the reverse recovery current according to the circuit configuration of FIG. 9 is Lf + L4. Therefore, according to the circuit configuration of the reference example shown in FIG. 4, although there is an effect of suppressing the jump voltage VCE (surge) at the time of turn-off, there is a drawback that the jump voltage during the recovery operation of the FWD becomes large.

On the other hand, in the circuit configuration shown in FIG. 2, the inductance at the time of reverse recovery current is Lf + L4 as shown in FIG. 5 (b), which is the same as the reference example in FIG. Therefore, the circuit configuration of FIG. 2 does not have the drawback that the jump voltage during the recovery operation of the FWD becomes larger than that of the reference example.

As described above, according to the semiconductor module according to the present embodiment, by increasing the inductance on the emitter side of the IGBT, the jump voltage VCE (surge) at the time of turn-off is not increased without increasing the loss generated during the mirror period. Can be suppressed. Further, according to the circuit configuration of FIG. 2 in which the anode electrode of the freewheeling diode (FWD) and the reference potential electrode of the drive circuit (HVIC) are directly connected by a bonding wire, the jump voltage during the recovery operation is not increased. This can be achieved and has a great effect in practical use.

Next, a second embodiment of the present invention will be described.
In this embodiment, the bonding wire 9u (9v, 9w) having the inductance L1'and the bonding wire 11u (11v, 11w) having the inductance L2 are arranged close to each other with respect to the connection configuration exemplified in FIG. 2A. Then, due to the magnetic coupling of both inductances L1'and L2, a counter electromotive force is generated in the inductance L1'of the bonding wire 9u (9v, 9w) at the time of turn-off with the IGBT 2u (2v, 2w), and this is used to generate a back electromotive force in the IGBT 2u. The gate drive capability of (2v, 2w) is lowered to suppress the jump voltage VCE (surge) at the time of turn-off.

(Example 3)
FIG. 6A shows the wiring configuration inside the module of IPM1 according to the third embodiment of the present embodiment, and FIG. 6B shows the circuit configuration. In FIG. 6A, the circuit of the U phase among the three phases is described as a representative, but it goes without saying that the same can be applied to the other phases.

The characteristics of the connection configuration according to the present embodiment are specifically that the bonding wire 9u (9v, 9w) is bonded to the substantially center of both terminals of the two bonding wires 11u (11v, 11w) of the FWD4u (4v, 4w). That's what I did. If the connection position of the bonding wire 9u (9v, 9w) on the FWD4u (4v, 4w) is determined in this way, the bonding wire 9u (4v, 4w) from the reference potential Vs of the HVIC6u (6v, 6w) to the FWD4u (4v, 4w) 9v, 9w) can be passed between the two bonding wires 11u (11v, 11w), and the bonding wires 9u (9v, 9w) and 11u (11v, 11w) are wired in parallel at intervals of a certain value or less. It is possible to provide a section (hereinafter referred to as "parallel wiring section"). Further, according to the connection configuration of FIG. 6A, the currents flowing through the bonding wires 9u (9v, 9w) and 11u (11v, 11w) are in phase with each other in the parallel wiring section.

The bonding wires 9u (9v, 9w) and 11u (11v, 11w) have inductances L1'and L2, respectively. This inductance can utilize the parasitic inductance of the wire. In this case, the spacing between the bonding wires 9u (9v, 9w) and 11u (11v, 11w) and the length of the parallel wiring section affect the magnitude of the back electromotive force due to mutual inductance and magnetic coupling. That is, by narrowing the distance between the two bonding wires 9u (9v, 9w) and 11u (11v, 11w) or lengthening the parallel wiring section, both bonding wires 9u (9v, 9w) and 11u (11v, 11w) The mutual inductance of the wire and the counter electromotive force generated by the mutual inductance can be increased.

Next, the operation and effect of the connection configuration of FIG. 6A will be described with reference to FIG. 7. FIG. 7 shows only the components necessary for explaining the magnetic coupling among the components of the IPM1. In this figure, the current (i1) flowing out from the reference potential electrode (Vs) of the HVIC 6u (6v, 6w) and the current (i2) flowing out from the emitter of the IGBT 2u (2v, 2w) via the bonding wire 9u (9v, 9w) are They are in phase as indicated by the arrows in the same direction.

In this circuit configuration, when the IGBT 2u (2v, 2w) is turned off, the current (i2) changes in the decreasing direction. As a result, a counter electromotive force (= mutual inductance value x time change of current i2) is generated in the bonding wire 9u (9v, 9w) magnetically coupled by the mutual inductance with the bonding wire 11u (11v, 11w). By that amount, the potential of the emitter of the IGBT 2u (2v, 2w) rises relatively with respect to the reference potential Vs of the HVIC 6u (6v, 6w). As a result, the gate of the IGBT 2u (2v, 2w) is biased, and the gate drive capability of the HVIC 6u (6v, 6w) is reduced. From a different point of view, in the connection configuration of FIG. 6A, the bonding wires 11u (11v, 11w) and the bonding wires 9u (9v, 9w) are magnetically coupled so as to increase the mutual inductances L2 and L1'. As a result, as shown by the alternate long and short dash line in FIG. 8, the time change rate di / dt of the collector current at the time of turn-off becomes gradual, and as a result, the jumping of VCE (surge) is suppressed.

Practically, the distance between the two bonding wires 9u (9v, 9w) and 11u (11v, 11w) having a normal current capacity is about 3 mm or less (preferably 1.5 mm or less), and the parallel wiring section is 10 mm. The above (preferably 15 mm or more) is desirable.
Under this condition, when di / dt = 1000 A / μs, a Vsurge suppressing effect of about 20 V can be expected as compared with the conventional configuration (reference example).

In FIG. 6, the bonding wire 11u (11v, 11w) is divided into two, and the bonding wire 9u (9v, 9w) is arranged substantially in the center thereof, but the number of divided bonding wires 11u (11v, 11w) is this. Not limited to this, it is divided into an arbitrary number (n) (n is an integer of 2 or more), and (n-1) number of bonding wires 9u (9v, 9w) are divided into each bonding wire 11u (11v, 11w). It may be arranged in between. On the other hand, if the current capacity of the bonding wires 11u (11v, 11w) is sufficient, the number of bonding wires 11u (11v, 11w) may be one. In this case, the bonding wire 9u (9v, 9w) is connected close to the connection position on the connection FWD4u (4v, 4w) of the bonding wire 11u (11v, 11w).

As described above, according to the present embodiment, in addition to the effects of the first embodiment, the following effects are exhibited. That is, in the present embodiment, "wiring between the emitter terminal of the IGBT and the anode terminal of the FWD" and "wiring between the reference potential terminal (Vs) of the HVIC and the anode terminal of the FWD" or "wiring between the anode terminals of the FWD" or The circuit is such that "wiring between the reference potential terminal (Vs) of the HVIC and the emitter terminal of the IGBT" is magnetically coupled. Therefore, the induced electromotive force is generated when the IGBT is turned off, so that the gate drive capability of the IGBT is reduced, and as shown in FIG. 8, −di / dt can be reduced. Therefore, it is possible to suppress VCE (surge) without increasing the switching loss. Further, as compared with the first embodiment, since the same VCE (surge) suppressing effect is obtained with a short wire length, the IPM package can be miniaturized.

The present invention is not limited to the above-described embodiment, and can be realized by various modifications without departing from the gist thereof. For example, in the above description, a circuit in which the emitter terminal is the reference potential electrode of the IGBT is described by taking an NPN type IGBT as an example as a semiconductor switching element, but the collector terminal is set to the reference potential of the IGBT using the PNP type IGBT. Needless to say, the circuit as an electrode can be similarly applied.

Further, it can be similarly applied even when a semiconductor switching element other than the IGBT, for example, a bipolar transistor or a MOSFET is used. When an country is used, the reference potential electrode is a source electrode, and when a polyclonal is used, the reference potential electrode is a drain electrode.

The bonding wire is preferably bonded on a wiring pattern having the same potential as the anode terminal of the FWD, the reference potential terminal of the HVIC, and the reference potential terminal of the IGBT. The switching element, the recirculation diode, or both can be configured by using any one of silicon, silicon carbide, gallium nitride-based material, gallium oxide-based material, and diamond.

1 Semiconductor module (IPM)
2u, 2v, 2w High potential side IGBT (High potential side switching element)
3u, 3v, 3w Low potential side IGBT (Low potential side switching element)
4u, 4v, 4w High potential side freewheeling diode (FWD)
5u, 5v, 5w Low potential side freewheeling diode (FWD)
6u, 6v, 6w High potential side drive circuit (HVIC)
7 Low potential side drive circuit (LVIC)
9u, 9v, 9w bonding wire (first wiring)
11u, 11v, 11w Bonding wire (second wiring)

Claims (4)

The high-potential side switching element and the low-potential side switching element forming the upper arm and the lower arm, respectively, the freewheeling diode connected in antiparallel to these switching elements, and the high-potential side switching element and the low-potential side switching element, respectively. A semiconductor module equipped with a high-potential side drive circuit and a low-potential side drive circuit that drives the diode on and off.
In the upper arm, the anode electrode of the freewheeling diode and the reference potential electrode of the high potential side drive circuit are directly connected by a first wiring having an inductance.
The anode electrode of the freewheeling diode is directly connected to the reference potential electrode of the high potential side switching element via a second wiring having an inductance.
The first wiring and the second wiring are provided so that magnetic coupling occurs between the first wiring and the second wiring when the high potential side switching element is driven on and off. A semiconductor module characterized by being magnetized. The semiconductor module according to claim 1 , wherein the first wiring and the second wiring allow currents to flow in the same phase . The semiconductor module according to claim 1 or 2 , wherein the inductance of the first wiring and the inductance of the second wiring are parasitic inductances of the wiring, respectively. The semiconductor module according to any one of claims 1 to 3, wherein the first wiring is a wire and is bonded to the anode electrode of the freewheeling diode.

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