JP2004242382A - Inverter device and motor drive using the inverter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate loss due to overcurrent passing via a level shift circuit and malfunctions due to overcurrent in an inverter device equipped with the level shift circuit converting a control signal level. <P>SOLUTION: This inverter device comprises the level shift circuit for transmitting control signals with different voltage levels to semiconductor switching devices, which is provided in an arm, having a plurality of semiconductor power switching devices connected between main terminals in series. The level shift circuit has a high-pressure proof MOSFET and a resistor, of which one end is connected to the high-pressure proof MOSFET via a diode. The diode blocks the overcurrent from passing via a parasitic diode of the high-pressure proof MOSFET in the level shift circuit. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an inverter device having an arm having a power switching element connected in series between main terminals, and more particularly to an inverter device having a level shift circuit for transmitting a control signal between a low voltage side circuit and a high voltage side circuit. .
[0002]
[Prior art]
FIG. 5 shows a block diagram of one arm of the conventional inverter device. The high voltage terminal of the main power supply Vdd and the collector of the HIGBT, which is the upper arm IGBT, are connected by a wiring HL1, and the emitter of the HIGBT, which is the upper arm IGBT, and the output terminal are connected by a wiring HL2. The collector and output terminal of the lower arm IGBT LIGBT are connected by a wiring L1, and the ground terminal of the main power supply Vdd and the emitter of the lower arm IGBT LIGBT are connected by a wiring L2. A diode HDIODE is connected in anti-parallel between the collector and the emitter of the HIGBT as the upper arm IGBT, and a diode LDIODE is similarly connected in anti-parallel to the LIGBT as the lower arm IGBT. A load inductance Lload is connected between a high voltage terminal and an output terminal of the main power supply Vdd, and a drive circuit composed of two MOSFETs, an Hn-MOS and an Hp-MOS, is provided at a gate terminal of a HIGBT which is an upper arm IGBT. Is connected.
[0003]
Since the emitter of the upper arm IGBT HIGBT is connected to the output, the upper arm IGBT HIGBT is driven in a floating state with respect to the main power supply ground terminal. Therefore, when the HIGBT of the upper arm IGBT is conducting, the same high voltage as that of the main power supply is applied. Therefore, the drive circuit needs to be insulated from the ground potential.
[0004]
In FIG. 5, a drive signal is transmitted from a lower arm to an upper arm floating in potential through a level shift circuit. The source of the MOSset, which is a high withstand voltage n-MOSFET for transmitting the ON signal of the level shift circuit, is connected to the lower arm ground, the gate is connected to the logic circuit, and the drain is connected to one end of the resistor Rset. The other end of the resistor Rset is connected to the high voltage side of the upper arm drive power supply HVcc. A Zener diode Zdset is connected to both ends of the resistor Rset to prevent overvoltage.
[0005]
The source of the MOS reset, which is a high withstand voltage n-MOSFET for transmitting an off signal, is connected to the lower arm ground, the gate is connected to the logic circuit, and the drain is connected to one end of the resistor Rreset. The other end of the resistor Rreset is connected to the high voltage side of the upper arm driving power supply HVcc. A Zener diode ZDreset is connected to both ends of the resistor Rreset to prevent overvoltage.
[0006]
The logic circuit transmits a pulse-like ON signal to a MOSset, which is a high-breakdown-voltage n-MOSFET for transmitting an ON signal, at the rise of a signal from an upper arm drive signal of a microcomputer or the like (not shown). At the falling edge of the drive signal, a pulse-like off signal is transmitted to a MOS reset, which is a high withstand voltage n-MOSFET for transmitting the off signal.
[0007]
The resistor Rset is connected to the set side of the flip-flop FF, and the resistor Rreset side is connected to the reset side of the FF. The drive signal decomposed into a rising pulse and a falling pulse by the logic circuit is restored to the same pulse width as the drive signal from the microcomputer by the flip-flop FF. The F output of the flip-flop F is inverted by the NOT circuit. When the command from the microcomputer is "H", the output of the flip-flop FF becomes "H", and the output of the NOT circuit becomes "L". -The MOS becomes conductive, a current is supplied from the upper arm driving power supply HVcc, and the HIGBT, which is the upper arm IGBT, becomes conductive.
[0008]
The operation of turning the LIGBT of the lower arm IGBT from on to off and back on will be described with reference to FIG. When the LIGBT of the lower arm IGBT is conducting, a current flows from the high voltage side of the main power supply Vdd to the ground side of the main power supply Vdd through the load inductance Lload, the wiring L1, the lower arm IGBT (LIGBT), and the wiring L2. When the LIGBT of the lower arm IGBT is turned off, a current is regenerated to the load inductance Lload through the wiring HL2, the upper arm diode HDIODE, and the wiring HL1. When the LIGBT of the lower arm IGBT becomes conductive again, in addition to the current flowing from the high voltage side of the main power supply Vdd to the ground side of the main power supply Vdd through the load inductance Lload, the wiring L1, the lower arm IGBT (LIGBT), and the wiring L2, Although it is a short time due to the electric charge accumulated in the diode HDIODE, the high voltage side of the main power supply Vdd passes through the wiring HL1, the upper arm diode HDIODE, the wiring HL2, the wiring L1, the lower arm IGBT (LIGBT), and the wiring L2. A recovery current flows to the ground side of the power supply Vdd.
[0009]
The above prior art inverter device is described in Patent Document 1 below.
[0010]
[Patent Document 1]
JP-A-5-316755
[Problems to be solved by the invention]
FIG. 7 shows a simulation waveform of each part when the lower arm IGBT is turned on again in the prior art shown in FIGS. When the gate voltage of the LIGBT of the lower arm IGBT exceeds the threshold voltage, a current starts to flow through the LIGBT of the lower arm IGBT. At the same time, the voltage between the collector and the emitter of the LIGBT of the lower arm IGBT decreases. Due to the recovery current of the upper arm diode HDIODE, the current flowing through the LIGBT of the lower arm IGBT has a maximum value.
[0012]
The voltage ΔV1 is generated by the time change dI1 / dt from the maximum value to the steady current and the inductance of the wiring L1. Further, a voltage ΔV2 is generated by the recovery current decrease dI2 / dt of the diode HDIODE of the upper arm and the inductance of the wiring L2. The sum of the voltages ΔV1 + ΔV2 is generated between the upper arm ground and the lower arm arm. This voltage is such that the upper arm ground has a negative potential with respect to the lower arm ground. When the generated voltage ΔV1 + ΔV2 is higher than the upper arm power supply voltage HVcc, as shown in FIG. 6, through a parasitic diode of a high voltage n-MOSFET MOSset for transmitting an ON signal and a high voltage n-MOSFET MOSreset for transmitting an OFF signal, as shown in FIG. , An overcurrent flows through the Zener diode. As shown in FIG. 7, this overcurrent flows as high as 100 A at the peak and generates a large circuit loss. Therefore, when this circuit is integrated in an IC, the element is used as a high-breakdown-voltage n-MOSFET MOSset for transmitting an ON signal. Also, the MOS reset which is a high breakdown voltage n-MOSFET for transmitting an off signal cannot withstand an overcurrent.
[0013]
An object of the present invention is to provide an inverter device that does not malfunction with a low loss, and more particularly, an inverter device including a boost level shift circuit that transmits a control signal from a low voltage side circuit to a high voltage side circuit, and from a high voltage side circuit to a low voltage side circuit. An object of the present invention is to provide an inverter device which includes a step-down level shift circuit for transmitting a control signal and does not malfunction with low loss.
[0014]
[Means for Solving the Problems]
The inverter device of the present invention includes a level shift circuit that transmits a control signal having a different voltage level to the semiconductor switching element, on at least one arm including a plurality of semiconductor power switching elements connected in series between main terminals, Since the level shift circuit has a high breakdown voltage MOSFET and a resistor having one end connected to the high breakdown voltage MOSFET via a diode, the diode prevents an overcurrent flowing through a parasitic diode of the high breakdown voltage MOSFET of the level shift circuit. .
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
(Example 1)
FIG. 1 shows one arm of the inverter device of the present embodiment. As shown in FIG. 1, the high voltage terminal of the main power supply 1 and the collector of the upper arm IGBT 4 are connected by a wiring 8, and the emitter of the upper arm IGBT 4 and the output terminal 12 are connected by a wiring 9. The collector of the lower arm IGBT 3 and the output terminal 12 are connected by a wiring 10, and the ground terminal of the main power supply 1 and the emitter of the lower arm IGBT 3 are connected by a wiring 11.
[0017]
A diode 6 is connected in anti-parallel between the collector and the emitter of the upper arm IGBT 4, and a diode 5 is also connected in anti-parallel to the lower arm IGBT 3. A load inductance 7 is connected between the high voltage terminal of the main power supply 1 and the output terminal 12. A drive circuit including an n-MOSFET 28 and a p-MOSFET 29 is connected to the gate terminal of the upper arm IGBT4.
[0018]
The source of the high withstand voltage n-MOSFET 21 for transmitting the ON signal is connected to the lower arm ground 13, and the gate is connected to the logic circuit 15. The cathode of the diode 31 is connected to the drain, and one end of the resistor 24 is connected to the anode of the diode 31. The other end of the resistor 24 is connected to the high voltage side of the power supply 2 for driving the upper arm.
A Zener diode 25 is connected to both ends of the resistor 24 to prevent overvoltage.
[0019]
The source of the high withstand voltage n-MOSFET 20 for transmitting the off signal is connected to the lower arm ground 13, and the gate is connected to the logic circuit 15. The cathode of the diode 30 is connected to the drain of the high-breakdown-voltage n-MOSFET 20 for transmitting the OFF signal, and one end of the resistor 22 is connected to the anode of the diode 30. The other end of the resistor 22 is connected to the high voltage side of the power supply 2 for driving the upper arm. A Zener diode 23 for preventing overvoltage is connected to both ends of the resistor 22.
[0020]
One end of the resistor 24 is connected to the set side of the flip-flop 26, and one end of the resistor 22 is connected to the reset side of the flip-flop 26. A NOT circuit 27 is connected to an output of the flip flip 26, and the NOT circuit 27 is connected to respective gates of an n-MOSFET 28 and a p-MOSFET 29. The source of the n-MOSFET 28 is connected to the upper arm ground 14, and the drain of the n-MOSFET 28 is connected to the gate of the upper arm IGBT4. The source of the p-MOSFET 29 is connected to the high potential side of the upper arm drive power supply 2, and the drain of the p-MOSFET 29 is connected to the gate of the upper arm IGBT 4.
[0021]
The operation of the inverter device according to the present embodiment will be described with reference to FIG. The logic circuit 15 receives a rise of the upper arm drive signal output from the microcomputer or the like, generates a pulse-like ON signal, transmits the pulse-like ON signal to the high breakdown voltage n-MOSFET 21 for transmitting the ON signal, and generates a pulse-like signal at the fall of the drive signal. An off signal is generated and transmitted to the gate of the high breakdown voltage n-MOSFET 20 for transmitting the off signal.
[0022]
First, when the high withstand voltage n-MOSFET 21 for transmitting the ON signal is turned on, a voltage is generated across the resistor 24 terminal, and the output of the flip-flop 26 becomes “H”. This “H” output is inverted by the NOT circuit 27 to become “L”, and the p-MOSFET 29 is turned on. When the p-MOSFET 29 is turned on, a current is supplied from the high voltage side of the main power supply 1 to the upper arm IGBT 4 and the upper arm IGBT 4 is turned on.
[0023]
Next, the logic circuit 15 transmits a pulse-like signal to the gate of the high-breakdown-voltage n-MOSFET 20 for transmitting the OFF signal in response to the fall of the signal. In response to this signal, when the high withstand voltage n-MOSFET 20 for transmitting the off signal is turned on, a voltage is generated across the resistor 22 terminal, and the output of the flip-flop 26 becomes “L”. This “L” output is inverted by the NOT circuit 27 to become “H”, the n-MOSFET 28 is turned on, electric charges are drawn from the gate of the upper arm IGBT4, and the upper arm IGBT4 is turned off. Thus, the drive signal decomposed into the rising pulse and the falling pulse in the logic circuit 15 is restored to the same pulse width as the driving signal output by the microcomputer by the flip-flop 26.
[0024]
The operation of the lower arm IGBT 3 being turned off from on and turned on again will be described with reference to FIG. When the lower arm IGBT 3 is conducting, a current flows from the high voltage side of the main power supply 1 to the ground side of the main power supply 1 through the load inductance 7, the output terminal 12, the wiring 10, the lower arm IGBT 3, and the wiring 11. When the lower arm IGBT 3 is turned off, a current is regenerated to the load inductance 7 through the wiring 9, the upper arm diode 6, and the wiring 8.
[0025]
When the lower arm IGBT 3 conducts again, in addition to the current flowing from the high voltage side of the main power supply 1 through the load inductance 7, the output terminal 12, the wiring 10, the lower arm IGBT 3 and the wiring 11 to the ground side of the main power supply 1, Although it is a short time due to the electric charge accumulated in the diode 6, the high voltage side of the main power supply 1 passes through the wiring 8, the upper arm diode 6, the wiring 9, the wiring 10, the lower arm IGBT 3, and the wiring 11, and the ground of the main power supply 1 Recovery current flows to the side.
[0026]
The current flowing through the lower arm IGBT 3 due to the recovery current of the diode 6 of the upper arm has a maximum value. The voltage ΔV1 is generated by the time change dI1 / dt from the maximum value to the steady current and the inductance of the wiring 10. Further, a voltage ΔV2 is also generated by the recovery current decrease dI2 / dt of the diode in the upper arm and the inductance of the wiring 9. The sum ΔV1 + ΔV2 of this voltage is generated between the upper arm ground and the lower arm arm. This voltage is such that the upper arm ground has a negative potential with respect to the lower arm ground. When the generated voltage ΔV1 + ΔV2 is higher than the upper arm power supply voltage 2, the current flows from the lower arm ground 13 to the upper arm ground through the parasitic diode of the high breakdown voltage n-MOSFET 21 for transmitting the ON signal and the high breakdown voltage n-MOSFET 20 for transmitting the OFF signal. 14, the current flow is blocked by diodes 30 and 31.
[0027]
As described above, in the present embodiment, since the current flowing through the parasitic diodes of the high withstand voltage n-MOSFET 21 for transmitting the ON signal and the high withstand voltage n-MOSFET 20 for transmitting the OFF signal is suppressed, it is possible to reduce the occurrence of loss in the circuit. . Further, in this embodiment, since no current flows through both ends of the resistors 22 and 24 at the time of upper arm recovery, an ON signal is not input at the same time when the flip-flop 26 is set and reset, so that there is no malfunction of the circuit.
[0028]
When the high voltage n-MOSFET 21 for transmitting the ON signal and the high voltage n-MOSFET 20 for transmitting the OFF signal are turned on, the diodes 30 and 31 are charged to accumulate electric current. At this time, if the upper arm ground is lower than the lower arm ground by the recovery current of the upper arm IGBT 8 and lower than the upper arm power supply voltage 2, a recovery current flows and a loss occurs. Therefore, the diodes 30 and 31 preferably have a small recovery current. Most preferred are Schottky diodes.
[0029]
Here, the smaller the barrier of the Schottky junction is, the smaller the loss of the current flowing when the high withstand voltage n-MOSFET 21 for transmitting the ON signal and the high withstand voltage n-MOSFET 20 for transmitting the OFF signal are turned on. Generally, the Schottky barrier between aluminum and n-type silicon used in a silicon semiconductor process is 0.7 V, but is lower than 0.5 V for titanium and n-type silicon. However, since titanium is poor in workability and is unsuitable for fine processes such as LSI, in order to reduce the loss of the inverter device, a Schottky diode and a material with a small barrier, for example, titanium, are used. It is even more desirable to have individual components.
[0030]
FIG. 2 is a mounting diagram of the inverter device of the present embodiment. FIG. 2 shows an example in which a portion surrounded by a dotted line shown in FIG. 1 is integrated in the same package. In FIG. 2, resistors 22, 24, Zener diodes 23, 25, flip-flop 26, NOT circuit 27, n-MOSFET 28, and p-MOSFET 29 are integrated on the same semiconductor chip 40, and a high withstand voltage n-MOSFET 21 for transmitting an ON signal. , The high breakdown voltage n-MOSFET 20 for transmitting the off signal is an individual semiconductor component chip, and the diodes 30 and 31 are also individual semiconductor component chips. The logic circuit 15 is integrated on the semiconductor chip 41. On an insulating substrate 49, these semiconductor chips 40, 41, high-breakdown-voltage n-MOSFETs 20, 21, and diodes 30, 31 are arranged.
[0031]
The semiconductor chip 40 is connected to an upper arm power supply high voltage side terminal 55 by a wire bonding 50 and connected to an upper arm ground terminal 56 by a wire bonding 51. Further, the semiconductor chip 40 is connected to a connection terminal 57 to a gate of the upper arm IGBT 4 by a wire bonding 52.
[0032]
The semiconductor chip 41 is connected to the lower arm power supply high voltage side terminal 61 by wire bonding 58 and connected to the lower arm ground terminal 62 by wire bonding 59.
Further, the semiconductor chip 41 is connected to a connection terminal 63 to a gate of the lower arm IGBT 3 by a wire bonding 60.
[0033]
The gate of the high-breakdown-voltage n-MOSFET 20 for transmitting the off signal is connected to the semiconductor chip 41 by wire bonding 64, and the source is connected to the semiconductor chip 41 by wire bonding 65. Further, the drain of the high-breakdown-voltage n-MOSFET 20 for transmitting the off signal is connected to the cathode of the diode 30 at the electrode 68, and the anode of the diode 30 is connected to the semiconductor chip 40 via the electrode 70 and the wire bonding 54.
[0034]
The gate of the high-breakdown-voltage n-MOSFET 21 for transmitting the ON signal is connected to the semiconductor chip 41 by wire bonding 66, and the source is connected to the semiconductor chip 41 by wire bonding 67. Further, the drain of the high-breakdown-voltage n-MOSFET 21 for transmitting the ON signal is connected to the cathode of the diode 31 via the electrode 69, and the anode of the diode 31 is connected to the semiconductor chip 40 via the electrode 71 and the wire bonding 53. As described above, in this embodiment, the Schottky diode and the MOSFET, which are individual components, are arranged and wired on the insulating substrate, and can be integrated in the same package.
[0035]
(Example 2)
FIG. 3 shows this embodiment. This embodiment is different from the first embodiment in that a level down circuit is provided for transmitting an abnormality to the logic circuit 15 when an abnormality such as an overcurrent, an overtemperature, a lower power supply voltage on the upper arm, or a main power supply overvoltage occurs. Are different. The level shift circuit, the n-MOSFET, and the p-MOSFET of the first embodiment are collectively shown as an upper arm drive circuit 32 in FIG.
[0036]
In this embodiment, the source of the high breakdown voltage p-MOSFET 34 is connected to the high potential side of the power supply 2 for driving the upper arm. An anode of a diode 35 is connected to the drain of the high-withstand-voltage p-MOSFET 34, and an abnormality detection circuit 33 for detecting an abnormality such as overcurrent, overtemperature, lowering of the upper arm side power supply voltage, and main power supply overvoltage is connected to the gate. I have. One end of a resistor 36 is connected to the cathode of the diode 35, the other end of the resistor 36 is connected to the lower arm ground 13, and a Zener diode 37 is connected to both ends of the resistor 36. The potential of the resistor 36 is input to the logic circuit 15.
[0037]
This embodiment operates as follows. When an abnormality such as overcurrent, overheating, lowering of the upper arm side power supply voltage, or overvoltage of the main power supply occurs, an ON signal is input from the abnormality detection circuit 33 to the gate of the high withstand voltage p-MOSFET 34, and the high withstand voltage p-MOSFET 34 is turned on to supply current. Flows. At this time, a voltage is generated across the resistor 36, an abnormal signal is transmitted to the logic circuit 15, and the logic circuit 15 performs the protection operation of the upper arm IGBT4 and the lower arm IGBT3.
[0038]
In this embodiment, as in the first embodiment, even if the upper arm ground drops further below the upper arm driving power supply voltage than the lower arm ground due to the voltage generated at the time of recovery of the upper arm diode 6, the high breakdown voltage p- Since no current flows through the parasitic diode of the MOSFET 34, loss can be suppressed and malfunction can be prevented.
[0039]
(Example 3)
FIG. 4 is an embodiment of a drive circuit for a three-phase motor using the inverter device according to the first embodiment of the present invention. The portions of the drive circuits 40U, 40V, 40W surrounded by the dotted lines are incorporated in the same package. The lower arm drive power supply is common to the U, V, and W phases. The upper arm drive power supplies 2U, 2V, and 2W are independent of the U, V, and W phases because the potentials of the upper arm grounds 14U, 14V, and 14W are undefined. The voltage of the main power supply 1 is common to the U, V, and W phases. The logic circuits 15U, 15V, and 15W turn on and off the power semiconductor switching elements of each of the U, V, and W phases according to a command from the microcomputer 100, whereby the motor 200 rotates. According to the present embodiment, it is possible to realize a motor drive device that has low loss and does not cause malfunction such as simultaneous conduction of the IGBTs of the upper and lower arms.
[0040]
In this embodiment, the inverter device shown in the second embodiment may be used, and the switching element driven by the level shift circuit is not limited to the IGBT, but may be an insulated gate power semiconductor element such as a power MOSFET or the like. , A bipolar transistor or a GTO (Gate Turn-off Thyristor).
[0041]
【The invention's effect】
In the inverter device according to the present invention, since an overcurrent can be prevented from flowing through the parasitic diode of the high-breakdown-voltage n-MOSFET of the level shift circuit, the loss of the inverter device and the malfunction prevention can be realized.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of an inverter device according to a first embodiment.
FIG. 2 is an explanatory diagram of mounting of the inverter device according to the first embodiment.
FIG. 3 is an explanatory diagram of an inverter device according to a second embodiment.
FIG. 4 is an explanatory diagram of a three-phase motor drive circuit according to a third embodiment.
FIG. 5 is an explanatory diagram of a conventional inverter device.
FIG. 6 is an explanatory diagram of an operation of a conventional inverter device.
FIG. 7 is an explanatory diagram of operation waveforms of a conventional inverter device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Main power supply, 2 ... Upper arm drive power supply, 3 ... Lower arm IGBT, 4 ... Upper arm IGBT, 5, 6, 30, 31, 35 ... Diode, 7 ... Load inductance, 8, 9, 10, 11 ... Wiring, 12: output terminal, 13: lower arm ground, 14: upper arm ground, 15: logic circuit, 20, 21: high withstand voltage n-MOSFET, 22, 24, 36: resistor, 23, 25, 37: Zener diode , 26: flip-flop, 27: NOT circuit, 28: n-MOSFET, 29: p-MOSFET, 32: upper arm drive circuit, 33: abnormality detection circuit, 34: high withstand voltage p-MOSFET, 40, 41: semiconductor chip , 49: insulating substrate, 50, 51, 52, 53, 54, 58, 59, 60, 64, 65, 66, 67: wire bonding, 55: upper arm power supply high voltage side end , 56 ... upper-arm grounding terminal, 57 and 63 ... connection terminal, 61 ... lower arm power high-voltage side terminal, 62 ... lower-arm grounding terminal, 68 to 71 ... electrode, 100 ... microcomputer, 200 ... motor.

Claims (13)

At least one arm having a plurality of semiconductor power switching elements connected in series between main terminals, and a boost level shift circuit for transmitting a control signal of the semiconductor power switching elements from a low voltage side circuit to a high voltage side circuit. In the inverter device,
The boost level shift circuit includes a high-breakdown-voltage n-MOSFET and a resistor having one end connected to the high-breakdown-voltage n-MOSFET via a diode;
An inverter device, wherein a cathode of the diode is connected to a drain of a high withstand voltage n-MOSFET of the boost level shift circuit, and an anode of the diode is connected to the resistor. At least one arm having a plurality of semiconductor power switching elements connected in series between main terminals, and a step-down level shift circuit for transmitting a control signal of the semiconductor power switching elements from a high voltage side circuit to a low voltage side circuit. In the inverter device,
The step-down level shift circuit includes a high-breakdown-voltage p-MOSFET and a resistor having one end connected to the high-breakdown-voltage p-MOSFET via a diode;
An inverter device, wherein an anode of the diode is connected to a drain of a high withstand voltage p-MOSFET of the step-down level shift circuit, and a cathode of the diode is connected to the resistor. 2. The inverter device according to claim 1, wherein the diode is a Schottky diode. 4. The inverter device according to claim 3, wherein the diode is an individual component. 3. The inverter device according to claim 2, wherein the diode is a Schottky diode. The inverter device according to claim 5, wherein the diode is an individual component. 2. The inverter device according to claim 1, wherein the diode and the boost level shift circuit are housed in the same package. 3. The inverter device according to claim 2, wherein the diode and the boost level shift circuit are housed in the same package. In a motor drive device that drives a motor by converting DC power to AC power,
The motor driving device includes at least one arm including a plurality of semiconductor power switching elements connected in series between main terminals, and a boost level shift circuit that transmits a control signal of the semiconductor switching elements from a low voltage side circuit to a high voltage side circuit. A high-voltage n-MOSFET and a resistor having one end connected to the high-voltage n-MOSFET via a diode. A motor driving device, wherein a cathode is connected to a drain of a high-withstand voltage n-MOSFET of the boost level shift circuit, and an anode of the diode is connected to the resistor. The motor drive device according to claim 9, further comprising three inverter devices, wherein the motor drive device converts DC power into three-phase AC power to drive the motor. 11. The motor drive device according to claim 10, wherein the inverter device houses the diode and the boost level shift circuit in the same package. 10. The motor driving device according to claim 9, wherein the semiconductor power switching element is an IGBT. 10. The motor driving device according to claim 9, wherein the semiconductor power switching element is a power MOSFET.

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