JP2019037119A - Semiconductor module - Google Patents

Abstract

To inhibit voltage overshoot at the time of turn-off without increasing switching loss occurring during a mirror period.SOLUTION: In an upper arm of a semiconductor module comprising a high potential side switching element and a low potential side switching element which form the upper arm and a lower arm, respectively, free wheeling diodes connected to the switching elements in a reverse parallel manner, respectively and a high potential side drive circuit and a low potential side drive circuit which switch on or off the high potential side switching element and the low potential side switching element, an anode electrode of the free wheeling diode and a reference potential electrode of the high potential side drive circuit are directly connected by a first wire, and the anode electrode of the free wheeling diode is connected with a reference potential electrode of the high potential side switching element via a second wire having inductance.SELECTED DRAWING: Figure 2

Description

  The present invention includes a high-potential-side semiconductor switching element, a low-potential-side switching element, and a drive circuit that drives these switching elements, and the reference potential of the high-potential-side semiconductor switching element is connected to the reference potential of the drive circuit. The present invention relates to a semiconductor module having a configuration.

  Inverter devices widely used for driving motors for consumer and industrial use have semiconductor switching elements such as MOSFETs and IGBTs and drive circuits for driving the semiconductor switching elements. As a means for downsizing the device and incorporating a protection circuit, an intelligent power module (hereinafter also referred to as “IPM”), which is a semiconductor module in which the semiconductor switching element and the drive circuit are packaged together, is used. It has been. Hereinafter, a case where an IGBT is used as the semiconductor switching element will be described.

  FIG. 1 shows an IPM three-phase inverter circuit. In this figure, IPM 1 is a high-potential side free-wheeling diode (hereinafter also referred to as “FWD”) 4 u, 4 v, 4 w connected in reverse parallel between the high-potential side IGBTs 2 u, 2 v, 2 w and these collectors and emitters, respectively. , Low potential side IGBTs 3u, 3v, 3w and low potential side FWDs 5u, 5v, 5w respectively connected in reverse parallel between these collectors and emitters. The IPM 1 is a drive circuit (hereinafter also referred to as “HVIC”) 6 u, 6 v, 6 w for driving the high potential side IGBTs 2 u, 2 v, 2 w and a drive circuit for driving the low potential side IGBTs 3 u, 3 v, 3 w (hereinafter referred to as “HVIC”). , Also referred to as “LVIC”) 7.

  In FIG. 1, the reference potential (Vs) of the emitter (E) and the HVICs 6u, 6v, 6w, which are the reference potentials of the high potential side IGBTs 2u, 2v, 2w, are the bonding wires 8u, 8v, 8w as shown in the reference example of FIG. Connected by. In FIG. 9, a U-phase circuit among the three phases is shown as a representative. Generally, this bonding wire is wired so that the wire length becomes short.

  In the inverter apparatus of IPM1, power conversion is performed by alternately turning on and turning off the high potential side IGBTs 2u, 2v, and 2w and the low potential side IGBTs 3u, 3v, and 3w. Therefore, as illustrated in FIG. Sometimes switching losses occur. 10A is a waveform (VCE) between the collector and the emitter at the turn-on and turn-off of an IGBT which is a general switching element, and FIG. 10B is a waveform of the collector current (IC) of the IGBT. Represents. At this time, as shown in FIG. 10C, switching loss occurs at the timing (shaded portion in the figure) where VCE and IC overlap at the time of turn-on and turn-off.

  In general, the IGBT charges and discharges the charge of the parasitic capacitance between the gate and the collector in the turn-on / turn-off operation, and a period in which the voltage between the gate and the emitter (gate voltage with respect to the reference potential) is flat occurs. Hereinafter, this period is referred to as a “mirror period”.

  The mirror period is shown in FIG. 11A shows the voltage VCE when the IGBT is turned off in the conventional circuit, FIG. 11B shows the current IC at this time, and FIG. 11C shows the waveform of the gate voltage VGE. As shown in FIG. 11C, a period (t1 to t2) in which the gate voltage VGE is flat is a mirror period.

  On the other hand, as shown in FIG. 12, in general, the inductance La between the emitters of the high potential side IGBTs 2u, 2v, 2w and the reference potential of the HVICs 6u, 6v, 6w is the emitter potential of the low potential side IGBTs 3u, 3v, 3w and the reference potential of the LVIC7. It is smaller than the inductance Lb of the wiring between them. For this reason, as shown in FIG. 13B, the time change rate di / dt of the collector current at the time of turn-off of the high potential side IGBTs 2u, 2v, 2w becomes steeper than that of the low potential side IGBTs 3u, 3v, 3w.

When the direct-current power supply voltage is VDC and the parasitic inductance of wiring or the like is L, the jumping voltage VCE (surge) is generally expressed by the following equation.
VCE (surge) = VDC + L · di / dt

  Therefore, as shown in FIG. 13A, when the high potential side IGBTs 2u, 2v, 2w are turned off, the jump voltage VCE (surge) applied between the collectors and emitters of the IGBTs 2u, 2v, 2w also increases. When the jump voltage VCE (surge) exceeds the withstand capability of the IGBT, avalanche breakdown is caused. In FIG. 13, the waveform of the circuit on the high potential side is indicated by a solid line, and the waveform of the circuit on the low potential side is indicated by a broken line.

  As a method for coping with avalanche breakdown, for example, as shown in Patent Document 1, the resistance value of the IGBT gate resistance Rg is increased, the slope of di / dt is moderated, and the jump of VCE (surge) is suppressed. This method is conventionally known.

  However, if the value of the gate resistance Rg of the IGBT is increased, the mirror period during which the gate-emitter voltage is flattened becomes longer as shown in FIG. As a result, there is a problem that switching loss increases.

  Further, in Patent Document 2, in a module type element having a MOS gate type semiconductor chip such as an IGBT therein, an inductance is inserted between the emitter of the semiconductor chip and the emitter terminal of the module type element, and VCE (surge) jumps up. A technique for suppressing the above is disclosed. However, Patent Document 2 is intended for a single semiconductor chip, and does not mention how to suppress the jump of VCE (surge) in a circuit in which freewheeling diodes are connected in antiparallel.

  In Patent Document 3, “wiring between the emitter of the high potential side semiconductor switch and the collector of the low potential side semiconductor switch” and “wiring to the gate for driving the low potential side semiconductor switch” are magnetically described. There is described a power conversion device that suppresses a turn-on current by suppressing a gate-emitter voltage Vge of a low-potential-side semiconductor switch by combining them to obtain a counter electromotive force. However, Patent Document 3 is intended to suppress the turn-on current of the semiconductor switch on the low potential side. Since the back electromotive force is generated so as to increase Vge at the time of turn-off, the slope of −di / dt is steep. There is a problem that VCE (surge) increases.

JP 2002-153043 A International Publication No. 98/53546 Pamphlet Japanese Patent No. 6065744

  The present invention has been made in view of the above-described circumstances, and in a semiconductor module having a freewheeling diode, a semiconductor capable of suppressing a jumping voltage at turn-off without increasing a switching loss generated in a mirror period. The purpose is to provide modules.

In order to achieve the above object, in the semiconductor module of the present invention, a high potential side switching element (2u, 2v, 2w) and a low potential side switching element (3u, 3v, 3w) forming the upper arm and the lower arm, respectively. Freewheeling diodes (4u, 4v, 4w, 5u, 5v, 5w) connected to these switching elements in antiparallel, and a high potential for driving the high potential side switching element and the low potential side switching element on / off. A semiconductor module (1) comprising a side drive circuit (6u, 6v, 6w) and a low potential side drive circuit (7),
In the upper arm, the anode electrode of the reflux diode (4u, 4v, 4w) and the reference potential electrode (Vs) of the high potential side drive circuit (6u, 6v, 6w) are the first wiring (9u, 9v, 9w). ) Directly connected,
The anode electrode of the freewheeling diode (4u, 4v, 4w) is electrically connected to the reference potential electrode of the high potential side switching element via the second wiring (11u, 11v, 11w) having inductance. It is characterized by that.

  In the present invention, in the semiconductor module having a configuration in which the anode electrode of the freewheeling diode (FWD) and the reference potential electrode of the high potential side switching element are connected by wiring, the anode electrode of the freewheeling diode and the reference potential electrode of the high potential side driving circuit are directly connected. Connect the wiring.

  Thereby, the jumping voltage at the time of turn-off can be suppressed by using the inductance of the wiring (second wiring) between the anode of the free-wheeling diode and the reference potential of the high-potential side switching element.

  Here, the “reference potential of the switching element” is a reference potential for operating the switching element, and means a portion having the same potential as the reference potential of the drive circuit that operates the switching element. “Directly connected” includes not only the case of being directly connected to the terminal of the electrode but also the case of being connected via a circuit pattern that is drawn out in the vicinity of the terminal and has the same potential as the terminal. Further, “electrically connected” means that it is sufficient if it is electrically connected and includes a case where it is physically connected directly.

  Note that the parasitic inductance of the second wiring may be used as the inductance of the second wiring. In addition, by using the first wiring as a bonding wire, it is possible to easily adjust the inductance of the first wiring.

Further, the semiconductor module of the present invention includes a high-potential side switching element and a low-potential side switching element that respectively form an upper arm and a lower arm, a free-wheeling diode connected in antiparallel to these switching elements, and the high-potential side switching element. A semiconductor module comprising a switching element and a high-potential side driving circuit for driving on / off the low-potential side switching element and a low-potential side driving circuit,
In the upper arm, the anode electrode of the freewheeling diode and the reference potential electrode of the high potential side drive circuit are directly connected by a first wiring having inductance,
The anode electrode of the freewheeling diode is directly connected to the reference potential electrode of the high potential side switching element through a second wiring having inductance,
The first wiring and the second wiring are provided so that magnetic coupling occurs between the first wiring and the second wiring when the high potential side switching element is driven on and off. It is characterized by being.

  In particular, the present invention is characterized in that the first wiring and the second wiring are arranged such that a current flows in the same phase and a back electromotive force is generated by magnetic coupling.

  In the present invention, the first wiring for connecting the anode electrode of the freewheeling diode and the reference potential electrode of the high potential side drive circuit, and the second wiring for connecting the anode electrode of the freewheeling diode and the reference potential electrode of the high potential side switching element. Are electrically coupled in phase with each other to generate back electromotive force on the first wiring side via the second wiring when the high potential side switching element is turned off. And the gate drive capability of a high potential side switching element is reduced using this back electromotive force, and the suppression effect of the jump voltage VCE (surge) at the time of turn-off is improved.

  If wiring is performed so that the currents of the first wiring and the second wiring flow in the same phase, the first wiring connects the anode electrode of the freewheeling diode and the reference potential electrode of the high potential side driving circuit. Instead, the reference potential electrode of the high potential side switching element and the reference potential electrode of the high potential side drive circuit may be connected.

  Preferably, the first wiring and the second wiring are wires, and are bonded to a wiring pattern having the same potential as the reference potential of the switching element.

  According to the semiconductor module of the present invention, the jumping voltage at the turn-off time can be suppressed without increasing the switching loss generated in the mirror period in the semiconductor module having the freewheeling diode.

1 is a circuit diagram of a conventional semiconductor module (IPM) according to an embodiment of the present invention. FIG. It is the principal part wiring diagram (FIG.2 (a)) of IPM of Example 1 in the 1st Embodiment of this invention, and its circuit diagram (FIG.2 (b)). 6 is a waveform comparison diagram of a voltage VCE, a current IC, and a gate voltage VGE when the high potential side IGBT of the IPM according to the reference example and Example 1 is turned off. FIG. It is a circuit diagram of IGBT of Example 2 (comparative example with FIG. 2). FIG. 5A is a diagram illustrating a difference in effect between the circuit configurations illustrated in FIG. 2 and FIG. 4, FIG. 5A is a diagram illustrating a reverse recovery current path in the circuit configuration illustrated in FIG. 4, and FIG. It is a figure which shows the reverse recovery current path | route at the time of a circuit structure. FIG. 6 is a connection diagram (FIG. 6 (a)) and a circuit diagram (FIG. 6 (b)) of an IPM of Example 3 according to the second embodiment of the present invention. It is explanatory drawing of the effect of Example 3. FIG. It is a waveform comparison figure of voltage VCE at the time of turn-off of high potential side IGBT of IPM by a reference example, Example 1, and Example 3, current IC, and gate voltage VGE. FIG. 9 is a main part connection diagram (FIG. 9A) and a circuit diagram (FIG. 9B) of an IPM according to a reference example. It is explanatory drawing of the switching loss at the time of turn-on and turn-off of IGBT which is a general switching element, Fig.10 (a) is a waveform diagram of the collector-emitter voltage (VCE) of IGBT, FIG.10 (b) is IGBT. FIG. 10C is a diagram for explaining the generation range of the switching loss. FIG. 11A is a waveform diagram of the voltage VCE when the IGBT is turned off, FIG. 11B is a waveform diagram of the current ICE at this time, and FIG. 11C is a gate voltage VGE. It is a figure which shows these waveforms and a mirror period. It is a conceptual explanatory drawing of the parasitic inductance of the wiring from the emitter of IGBT. FIG. 13 is a waveform diagram (FIG. 13A) of the voltage VCE at the time of turn-off of the high potential side IGBT and the low potential side IGBT, and a waveform diagram of the current IC (FIG. 13B). It is a figure which shows the relationship between the magnitude | size of gate resistance Rg, the jumping voltage at the time of IGBT turn-off, and a mirror period.

  A first embodiment of the present invention will be described below with reference to the drawings. Note that the entire circuit of the semiconductor module (IPM) 1 according to the present embodiment is represented by FIG. Further, since the following description relates to a circuit on the high potential side, description of high potential / low potential is omitted.

Example 1
FIG. 2A shows a connection configuration inside the module of the IPM 1 according to the first embodiment, and FIG. 2B shows a circuit configuration thereof. In FIG. 2, the U-phase circuit among the three phases is shown as a representative, but it goes without saying that the same applies to other phases.

  As shown in FIG. 2A, the IPM 1 has an HVIC 6u (6v, 6w) and an external terminal U (V, W) arranged on an insulating substrate, and an IGBT 2u (2v, 2w) and an FWD 4u (4v, 4w) between them. ) Are arranged in order from the HVIC 6u (6v, 6w).

  The reference potential Vs of the HVIC 6u (6v, 6w) and the anode of the FWD 4u (4v, 4w) are connected by a bonding wire 9u (9v, 9w). The output OUT of the HVIC 6u (6v, 6w) is connected to the gate of the IGBT 2u (2v, 2w) by the bonding wire 10u (10v, 10w). The emitter of IGBT 2u (2v, 2w) and the anode of FWD 4u (4v, 4w) are connected by bonding wire 11u (11v, 11w), and the anode of FWD 4u (4v, 4w) and external terminal U (V, W) are bonding wires. 12u (12v, 12w) is connected. The collector of the IGBT 2u (2v, 2w) and the cathode of the FWD 4u (4v, 4w) are connected by a circuit pattern 16u (16v, 16w). In FIG. 2A, two bonding wires 11u (11v, 11w) and 12u (12v, 12w) are provided in parallel, but any number can be provided depending on the current capacity of the wires.

  Each bonding wire, IGBT element, or FWD element has an inductance shown in FIG. In FIG. 2B, Li and Lf are the internal inductances of the IGBT 2u (2v and 2w) and FWD 4u (4v and 4w), respectively, and L2 is between the emitter of the IGBT 2u (2v and 2w) and the anode of the FWD 4u (4v and 4w). Wiring inductance of the bonding wire 11u (11v, 11w), L4 represents the wiring inductance of the bonding wire 12u (12v, 12w) to the external terminal U (V, W) of the IPM1. L1 'is the wiring inductance of the bonding wire 9u (9v, 9w) between the anode of the FWD 4u (4v, 4w) and the reference potential of the HVIC 6u (6v, 6w).

  Next, the effect of the connection configuration of the semiconductor module (IPM) 1 will be described in comparison with the reference example of FIG.

  In the connection configuration of the IPM 1 of this embodiment shown in FIG. 2, the inductance between the emitter E, which is the reference potential of the IGBT 2u (2v, 2w), and the reference potential Vs of the HVIC 6u (6v, 6w) is Li + L2 + L1 ′. On the other hand, in the connection configuration of the reference example shown in FIG. 9, the inductance between the emitter E of the IGBT 2u (2v, 2w) and the reference potential Vs of the HVIC 6u (6v, 6w) is Li + L1. Normally, L1 and L1 ′ are substantially the same value, or, as shown in FIG. 2A, IGBT 2u (2v, 2w) is arranged between HVIC 6u (6v, 6w) and FWD 4u (4v, 4w). Below, L1 'becomes a larger value. For this reason, the configuration according to the present embodiment increases the inductance between the emitter E of the IGBT 2u (2v, 2w) and the reference potential Vs of the HVIC 6u (6v, 6w) by at least the inductance L2 as compared with the reference example. That is, compared with the reference example, the connection configuration of this embodiment generates a large back electromotive force at least by the inductance L2 due to -di / dt at the time of IGBT turn-off, and the gate of the IGBT 2u (2v, 2w). Will be biased. Thereby, compared with the reference example, the present example has a gentler slope of di / dt when the IGBT is turned off, and the effect of suppressing the jumping voltage can be increased accordingly.

  Incidentally, since the electromotive force due to the inductance component L can be calculated by L · di / dt, when di / dt = 1000 A / μs, a bonding wire having a wiring inductance with the inductance L2 of 5 to 10 nH is used. Thus, the effect of suppressing the jumping voltage of about 5 to 10 V is obtained.

FIG. 3 shows time-varying waveforms of the voltage VCE, the current IC, and the voltage VGE at the time of turn-off of the IGBT 2u (2v, 2w) in the connection configuration of this embodiment in comparison with the reference example. In FIG. 3, the solid line is the waveform of this embodiment, and the broken line is the waveform of the reference example. As shown in FIG. 3A, the peak value of the jump voltage VCE (surge) of the circuit according to this example is lower than the peak value of the jump voltage VCE (surge) of the circuit of the reference example. That is, in the circuit according to the present embodiment, dV / dt from t1 to t2 (mirror period) and thereafter to t3 is equal to that of the reference example, and the subsequent jump voltage VCE (surge) can be suppressed.
Further, as shown in FIG. 3B, the slope of di / dt is gentler in this embodiment than in the reference example. Moreover, as shown in FIG.3 (c), the mirror period (t1-t2) of both circuits is equivalent.

  As described above, according to the connection configuration of the semiconductor module (IPM) according to the present embodiment, the resistance of the gate resistance Rg of the IGBT in the circuit configuration in which the free-wheeling diode (FWD) is connected in antiparallel to the switching element (IGBT). Since the inductance component on the emitter side of the IGBT is increased without changing the value, the mirror period is not lengthened, and the jumping voltage VCE (surge) is suppressed while the switching loss during the mirror period is maintained at the same level as before. can do.

  In the connection configuration of FIG. 2, the anode electrode of the FWD 4u (4v, 4w) and the reference potential electrode of the HVIC 6u (6v, 6w) can be directly connected using the bonding wire 9U (9v, 9w). As a result, by using a bonding wire whose inductance value (L1 ′) is adjusted, the inductance Li + L2 + L1 ′ between the emitter of the IGBT 2u (2v, 2w) and the reference potential of the HVIC 6u (6v, 6w) is sufficiently larger than the conventional one. The slope of di / dt at the time of IGBT turn-off can be adjusted to a desired value that is gentler than the conventional value. An inductance L1 'between the anode of the FWD 4u (4v, 4w) and the reference potential of the HVIC 6u (6v, 6w) may be inserted, but a parasitic inductance of a wire can also be used.

  In particular, in the configuration in which the IGBT 2u (2v, 2w) is arranged between the HVIC 6u (6v, 6w) and the FWD 4u (4v, 4w) as shown in FIG. 2, the reference potential terminal (Vs) of the HVIC 6u (6v, 6w). Since the parasitic inductance (L1 ′) of the bonding wire is increased by directly connecting the FWD 4u (4v, 4w) and the anode terminal of the FWD 4u (4v, 4w) by the bonding wire 9U (9v, 9w), the jumping voltage VCE (surge) can be easily obtained. Can be suppressed.

  In addition, by connecting the emitter electrode of the IGBT 2u (2v, 2w) and the anode electrode of the FWD 4u (4v, 4w) using a bonding wire, not only the inductance L1 'but also the inductance L2 can be adjusted.

(Example 2)
FIG. 2 shows a configuration in which a reference potential electrode of HVIC 6u (6v, 6w) and an anode electrode of FWD 4u (4v, 4w) are directly wire-bonded. As shown in FIG. 4, the emitter of IGBT 2u (2v, 2w) An external inductance Lex can be inserted between the electrode and the reference potential of the HVIC 6u (6v, 6w). In the case of the circuit configuration of FIG. 4, the inductance between the emitter E, which is the reference potential of the IGBT 2u (2v, 2w), and the reference potential Vs of the HVIC 6u (6v, 6w) is Li + Lex + L1. That is, compared to the circuit configuration according to the reference example shown in FIG. 9, the inductance component on the emitter side of the IGBT 2u (2v, 2w) is increased by (Lex). Accordingly, the bias of the IGBT gate is increased, and di / dt can be suppressed.

  4 can increase only the inductance component on the emitter side without changing the resistance value of the gate resistance Rg of the IGBT as in the connection configuration of FIG. Therefore, also in this embodiment, the jump voltage VCE (surge) at the turn-off time can be suppressed without increasing the loss generated in the mirror period.

  By the way, the reverse recovery current of the connection configuration of FIG. 4 is larger than that of the connection configuration of FIG. Here, the reverse recovery current is a current that flows at the moment when the voltage applied to the freewheeling diode (FWD) is switched from the forward voltage to the reverse voltage, and its magnitude is in the current path of the freewheeling diode (FWD). It depends on the inductance present.

  The inductance at the time of reverse recovery current according to the circuit configuration of FIG. 4 is Lf + L2 + Lex + L4, as shown in FIG. 5A. On the other hand, the inductance at the time of reverse recovery current according to the circuit configuration of FIG. 9 is Lf + L4. Therefore, according to the circuit configuration of the reference example shown in FIG. 4, although there is an effect of suppressing the jump voltage VCE (surge) at turn-off, there is a drawback that the jump voltage at the time of the FWD recovery operation becomes large.

  On the other hand, in the circuit configuration shown in FIG. 2, the inductance at the time of reverse recovery current is Lf + L4 as shown in FIG. 5B, and is not different from the reference example of FIG. Therefore, the circuit configuration of FIG. 2 does not have the drawback that the jump voltage during the FWD recovery operation is larger than that of the reference example.

  As described above, according to the semiconductor module according to the present embodiment, by increasing the inductance on the emitter side of the IGBT, the jump voltage VCE (surge) at the turn-off time is increased without increasing the loss generated in the mirror period. Can be suppressed. Furthermore, according to the circuit configuration of FIG. 2 in which the anode electrode of the freewheeling diode (FWD) and the reference potential electrode of the drive circuit (HVIC) are directly connected by a bonding wire, the jumping voltage during the recovery operation is not increased. This can be realized and has a great practical effect.

Next, a second embodiment of the present invention will be described.
In the present embodiment, a bonding wire 9u (9v, 9w) having an inductance L1 ′ and a bonding wire 11u (11v, 11w) having an inductance L2 are disposed close to the connection configuration illustrated in FIG. Then, due to the magnetic coupling of both the inductances L1 ′ and L2, a back electromotive force is generated in the inductance L1 ′ of the bonding wire 9u (9v, 9w) at the time of turn-off with the IGBT 2u (2v, 2w), and this is used to generate the IGBT 2u. The gate drive capability of (2v, 2w) is reduced to suppress the jump voltage VCE (surge) at the turn-off time.

(Example 3)
FIG. 6A shows a connection configuration inside the module of the IPM 1 according to Example 3 of the present embodiment, and FIG. 6B shows its circuit configuration. In FIG. 6A, the U-phase circuit among the three phases is shown as a representative, but it goes without saying that the same applies to other phases.

  Specifically, the connection configuration according to the present embodiment is characterized in that the bonding wire 9u (9v, 9w) is bonded to approximately the center of both terminals of the two bonding wires 11u (11v, 11w) of the FWD 4u (4v, 4w). It is that. If the connection position of the bonding wire 9u (9v, 9w) on the FWD 4u (4v, 4w) is determined in this manner, the bonding wire 9u (from the reference potential Vs of the HVIC 6u (6v, 6w) to the FWD 4u (4v, 4w) is obtained. 9v, 9w) can be passed between the two bonding wires 11u (11v, 11w), and the bonding wires 9u (9v, 9w), 11u (11v, 11w) are wired in parallel at intervals of a predetermined value or less. Sections (hereinafter referred to as “parallel wiring sections”) can be provided. Further, according to the connection configuration of FIG. 6A, in the parallel wiring section, the currents flowing through the bonding wires 9u (9v, 9w) and 11u (11v, 11w) are in phase.

  The bonding wires 9u (9v, 9w) and 11u (11v, 11w) have inductances L1 'and L2, respectively. As this inductance, the parasitic inductance of the wire can be used. In this case, the interval between the bonding wires 9u (9v, 9w) and 11u (11v, 11w) and the length of the parallel wiring section affect the magnitude of the counter electromotive force due to mutual inductance and magnetic coupling. That is, the bonding wires 9u (9v, 9w) and 11u (11v, 11w) are narrowed by narrowing the interval between the bonding wires 9u (9v, 9w) and 11u (11v, 11w) or lengthening the parallel wiring section. The mutual inductance and the back electromotive force generated thereby can be increased.

  Next, the effect of the connection configuration of FIG. 6A will be described with reference to FIG. FIG. 7 shows only elements necessary for explaining the magnetic coupling among the constituent elements of the IPM 1. In this figure, the current (i1) flowing out from the reference potential electrode (Vs) of the HVIC 6u (6v, 6w) and the current (i2) flowing out from the emitter of the IGBT 2u (2v, 2w) through the bonding wires 9u (9v, 9w) They are in phase as indicated by the arrows in the same direction.

  In this circuit configuration, when the IGBT 2u (2v, 2w) is turned off, the current (i2) changes in a decreasing direction. As a result, back electromotive force (= value of mutual inductance × time change of current i2) is generated in the bonding wire 9u (9v, 9w) magnetically coupled by the mutual inductance with the bonding wire 11u (11v, 11w). Accordingly, the potential of the emitter of the IGBT 2u (2v, 2w) is relatively increased with respect to the reference potential Vs of the HVIC 6u (6v, 6w). As a result, the gate of the IGBT 2u (2v, 2w) is biased, and the gate drive capability of the HVIC 6u (6v, 6w) is reduced. In other words, in the connection configuration of FIG. 6A, the bonding wires 11u (11v, 11w) and the bonding wires 9u (9v, 9w) are magnetically coupled so as to increase their inductances L2, L1 '. As a result, as indicated by the one-dot chain line in FIG. 8, the time change rate di / dt of the collector current at the time of turn-off becomes moderate, and as a result, the jump of VCE (surge) is suppressed.

Practically, the distance between the bonding wires 9u (9v, 9w), 11u (11v, 11w) having a normal current capacity is about 3 mm or less (preferably 1.5 mm or less), and the parallel wiring section is 10 mm. The above is preferable (preferably 15 mm or more).
Under this condition, when di / dt = 1000 A / μs, a Vsurge suppression effect of about 20 V can be expected as compared with the conventional configuration (reference example).

  In FIG. 6, the bonding wire 11u (11v, 11w) is divided into two pieces, and the bonding wire 9u (9v, 9w) is arranged at the approximate center, but the number of the bonding wires 11u (11v, 11w) is divided. The number of bonding wires 9u (9v, 9w) is divided into an arbitrary number (n) (n is an integer of 2 or more), and each of the bonding wires 11u (11v, 11w) It may be arranged between them. On the other hand, if the current capacity of the bonding wires 11u (11v, 11w) is sufficient, the number may be one. In this case, the bonding wire 9u (9v, 9w) is connected in proximity to the connection position on the connection FWD 4u (4v, 4w) of the bonding wire 11u (11v, 11w).

  As described above, according to the present embodiment, in addition to the effects of the first embodiment, the following effects can be obtained. That is, in this embodiment, without changing the gate resistance value, “wiring between the emitter terminal of the IGBT and the anode terminal of the FWD” and “wiring between the reference potential terminal (Vs) of the HVIC and the anode terminal of the FWD” or A circuit that magnetically couples “wiring between the reference potential terminal (Vs) of the HVIC and the emitter terminal of the IGBT”. For this reason, when the induced electromotive force is generated when the IGBT is turned off, the gate drive capability of the IGBT is lowered, and −di / dt can be reduced as shown in FIG. 8. For this reason, VCE (surge) can be suppressed without increasing the switching loss. In addition, compared with the first embodiment, an equivalent VCE (surge) suppression effect is achieved with a short wire length, and thus the IPM package can be downsized.

  The present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the scope of the invention. For example, in the above description, an NPN type IGBT is used as an example of a semiconductor switching element, and a circuit in which an emitter terminal is an IGBT reference potential electrode has been described. However, a PNP type IGBT is used to connect a collector terminal to an IGBT reference potential. Needless to say, the present invention can also be applied to a circuit using electrodes.

  Further, the present invention can be similarly applied even when a semiconductor switching element other than the IGBT, for example, a bipolar transistor or a MOSFET is used. When using NMOS, the reference potential electrode is a source electrode, and when using PMOS, the reference potential electrode is a drain electrode.

  Bonding wires are preferably bonded on wiring patterns that have the same potential as the anode terminal of the FWD, the reference potential terminal of the HVIC, and the reference potential terminal of the IGBT. The switching element and / or the reflux diode can be formed using any of silicon, silicon carbide, a gallium nitride material, a gallium oxide material, and diamond.

1 Semiconductor module (IPM)
2u, 2v, 2w High potential side IGBT (High potential side switching element)
3u, 3v, 3w Low potential side IGBT (Low potential side switching element)
4u, 4v, 4w High-potential-side reflux diode (FWD)
5u, 5v, 5w Low-potential-side reflux diode (FWD)
6u, 6v, 6w High potential side drive circuit (HVIC)
7 Low-potential side drive circuit (LVIC)
9u, 9v, 9w Bonding wire (first wiring)
11u, 11v, 11w Bonding wire (second wiring)

Claims (7)

A high-potential side switching element and a low-potential side switching element that respectively form an upper arm and a lower arm, freewheeling diodes connected in antiparallel to these switching elements, and the high-potential side switching element and the low-potential side switching element A high-potential side drive circuit for driving on / off and a low-potential side drive circuit,
In the upper arm, the anode electrode of the reflux diode and the reference potential electrode of the high potential side drive circuit are directly connected by a first wiring,
The semiconductor module according to claim 1, wherein an anode electrode of the freewheeling diode is electrically connected to a reference potential electrode of the high potential side switching element through a second wiring having inductance.   The semiconductor module according to claim 1, wherein the inductance of the second wiring is a parasitic inductance of the wiring.   The semiconductor module according to claim 1, wherein the first wiring is a wire and is bonded to an anode electrode of the free-wheeling diode. The first wiring has an inductance;
The first wiring and the second wiring are provided so that magnetic coupling occurs between the first wiring and the second wiring when the high potential side switching element is driven on and off. The semiconductor module according to claim 1, wherein the semiconductor module is provided. A high-potential side switching element and a low-potential side switching element that respectively form an upper arm and a lower arm, freewheeling diodes connected in antiparallel to these switching elements, and the high-potential side switching element and the low-potential side switching element A high-potential side drive circuit for driving on / off and a low-potential side drive circuit,
In the upper arm, the anode electrode of the freewheeling diode and the reference potential electrode of the high potential side drive circuit are directly connected by a first wiring having inductance,
The anode electrode of the freewheeling diode is directly connected to the reference potential electrode of the high potential side switching element through a second wiring having inductance,
The first wiring and the second wiring are provided so that magnetic coupling occurs between the first wiring and the second wiring when the high potential side switching element is driven on and off. The semiconductor module characterized by the above-mentioned.   The semiconductor module according to claim 5, wherein the first wiring and the second wiring are arranged so as to have an in-phase current.   7. The semiconductor module according to claim 5, wherein the inductance of the first wiring and the inductance of the second wiring are parasitic inductances of the wiring, respectively.

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