JP2020191349A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2020191349A
JP2020191349A JP2019095061A JP2019095061A JP2020191349A JP 2020191349 A JP2020191349 A JP 2020191349A JP 2019095061 A JP2019095061 A JP 2019095061A JP 2019095061 A JP2019095061 A JP 2019095061A JP 2020191349 A JP2020191349 A JP 2020191349A
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Japan
Prior art keywords
switching element
conductive pattern
igbt
reference potential
wiring
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JP2019095061A
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Japanese (ja)
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JP7138596B2 (en
Inventor
中村　宏之
Hiroyuki Nakamura
宏之 中村
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2019095061A priority Critical patent/JP7138596B2/en
Priority to US16/793,111 priority patent/US11522533B2/en
Priority to DE102020112338.8A priority patent/DE102020112338B4/en
Priority to CN202010412371.6A priority patent/CN111987091A/en
Publication of JP2020191349A publication Critical patent/JP2020191349A/en
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Publication of JP7138596B2 publication Critical patent/JP7138596B2/en
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    • H01—ELECTRIC ELEMENTS
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
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Abstract

To provide a semiconductor device such that a package can be suppressed from increasing in size, and a negative feedback quantity can be adjusted.SOLUTION: A power module as a semiconductor device comprises an IGBT 10 as a switching element and a free-wheel diode (FWD) 20 connected in parallel with the switching element. The IGBT 10 has, on its surface, an emitter electrode 11 and a gate electrode 12 of the IGBT 10, and a conductive pattern 13 insulated therefrom. The FWD 20 has, on its surface, an anode electrode 21 of the FWD 20 and a conductive pattern 22 insulated therefrom.SELECTED DRAWING: Figure 1

Description

本発明は、半導体装置、特に電力用半導体装置に関するものである。 The present invention relates to semiconductor devices, particularly power semiconductor devices.

例えばＩＧＢＴ（Insulated Gate Bipolar Transistor）等のスイッチング素子を備える電力用半導体装置において、接続された負荷が短絡した際にコレクタ−エミッタ間を流れる電流を抑制することでスイッチング素子を過電流から保護する技術が知られている。 For example, in a power semiconductor device equipped with a switching element such as an IGBT (Insulated Gate Bipolar Transistor), a technique for protecting the switching element from overcurrent by suppressing the current flowing between the collector and the emitter when the connected load is short-circuited. It has been known.

例えば下記の特許文献１には、ＩＧＢＴのエミッタ配線に電流が流れることで生じる電圧降下を、当該ＩＧＢＴのゲートに帰還させる「負帰還回路」を備える半導体装置が開示されている。特許文献１の半導体装置では、ＩＧＢＴを制御する駆動回路の基準電位配線をエミッタ配線に接続させることで負帰還回路が構成されている。また、特許文献１の半導体装置には、エミッタ配線の複数箇所に、駆動回路の基準電位配線を接続するための端子が設けられており、基準電位配線を接続する端子を選択することで負帰還量の調整がなされる。 For example, Patent Document 1 below discloses a semiconductor device including a "negative feedback circuit" that feeds back a voltage drop caused by a current flowing through an emitter wiring of an IGBT to the gate of the IGBT. In the semiconductor device of Patent Document 1, a negative feedback circuit is configured by connecting the reference potential wiring of the drive circuit that controls the IGBT to the emitter wiring. Further, the semiconductor device of Patent Document 1 is provided with terminals for connecting the reference potential wiring of the drive circuit at a plurality of places of the emitter wiring, and negative feedback is provided by selecting the terminal for connecting the reference potential wiring. The amount is adjusted.

一方、トランスファーモールド型の半導体装置（パワーモジュール）では、負帰還回路を構成するために駆動回路の基準電位配線のワイヤをフリーホイールダイオード（ＦＷＤ）に接続させると、基準電位配線がＩＧＢＴの主電流を流すワイヤと干渉する恐れがある。このようなワイヤ同士の干渉を防止するために、基準電位配線を接続させるためのリードフレームや配線基板を別途設けてもよいが、パワーモジュールのパッケージが大型化する問題が生じる。 On the other hand, in a transfer mold type semiconductor device (power module), when the wire of the reference potential wiring of the drive circuit is connected to the free wheel diode (FWD) in order to form a negative feedback circuit, the reference potential wiring becomes the main current of the IGBT. There is a risk of interfering with the wire that flows through. In order to prevent such interference between the wires, a lead frame and a wiring board for connecting the reference potential wiring may be separately provided, but there arises a problem that the package of the power module becomes large.

例えば下記の特許文献２には、ワイヤ同士の干渉を防止する技術として、複数のスイッチング素子のチップを備える半導体装置において、各チップの表面にゲート配線用の電極を設け、駆動回路から離れた位置のチップへの配線を、他のチップ上のゲート配線を経由して行う技術が開示されている。 For example, in Patent Document 2 below, as a technique for preventing interference between wires, in a semiconductor device including chips of a plurality of switching elements, electrodes for gate wiring are provided on the surface of each chip, and a position away from the drive circuit is provided. A technique is disclosed in which wiring to a chip is performed via a gate wiring on another chip.

特開２０１４−１２０５６３号公報Japanese Unexamined Patent Publication No. 2014-120563 特開２０１３−１２５８０６号公報Japanese Unexamined Patent Publication No. 2013-125806

上述のように、トランスファーモールド型のパワーモジュールに負帰還回路を搭載させる場合、パッケージの大型化の抑制、ならびに、所望の負帰還機能を得るための負帰還量の調整が課題となる。 As described above, when the transfer mold type power module is equipped with the negative feedback circuit, it is necessary to suppress the increase in size of the package and adjust the amount of negative feedback to obtain the desired negative feedback function.

本発明は以上のような課題を解決するためになされたものであり、パッケージの大型化を抑制でき、且つ、負帰還量の調整が可能な半導体装置を提供することを目的とする。 The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of suppressing an increase in size of a package and adjusting a negative feedback amount.

本発明に係る半導体装置は、スイッチング素子と、前記スイッチング素子に並列接続されたフリーホイールダイオードと、を備え、前記スイッチング素子は、その表面上に、前記スイッチング素子の主電極および制御電極から絶縁された第１の導電性パターンを有し、前記フリーホイールダイオードは、その表面上に、前記フリーホイールダイオードの主電極から絶縁された第２の導電性パターンを有する。 The semiconductor device according to the present invention includes a switching element and a free wheel diode connected in parallel to the switching element, and the switching element is insulated from the main electrode and the control electrode of the switching element on its surface. The freewheel diode has a first conductive pattern, and the freewheel diode has a second conductive pattern on its surface, which is insulated from the main electrode of the freewheel diode.

本発明に係る半導体装置によれば、負帰還量を調整（負帰還効果の強弱の調整）するために駆動ＩＣの基準電位配線の接続先をフリーホイールダイオードの主電極や、外部接続端子に接続させる場合に、その接続を第１の導電性パターンおよび第２の導電性パターンを通して行うことで、基準電位配線のワイヤと他のワイヤとが干渉することを防止できる。よって、ワイヤ同士の干渉を防止するためのリードフレーム等を別途も受ける必要がなく、半導体装置の大型化を抑制できる。 According to the semiconductor device according to the present invention, in order to adjust the amount of negative feedback (adjustment of the strength of the negative feedback effect), the connection destination of the reference potential wiring of the drive IC is connected to the main electrode of the free wheel diode or the external connection terminal. By making the connection through the first conductive pattern and the second conductive pattern, it is possible to prevent the wire of the reference potential wiring from interfering with the other wires. Therefore, it is not necessary to separately receive a lead frame or the like for preventing interference between the wires, and it is possible to suppress an increase in the size of the semiconductor device.

実施の形態１に係るパワーモジュールの構成例を示す図である。It is a figure which shows the structural example of the power module which concerns on Embodiment 1. FIG. 実施の形態１に係るパワーモジュールの構成例を示す図である。It is a figure which shows the structural example of the power module which concerns on Embodiment 1. FIG. 実施の形態１に係るパワーモジュールの構成例を示す図である。It is a figure which shows the structural example of the power module which concerns on Embodiment 1. FIG. 実施の形態１に係るパワーモジュールの構成例を示す図である。It is a figure which shows the structural example of the power module which concerns on Embodiment 1. FIG. 実施の形態２に係るパワーモジュールの構成例を示す図である。It is a figure which shows the structural example of the power module which concerns on Embodiment 2.

＜実施の形態１＞
図１は、実施の形態１に係る半導体装置であるパワーモジュールの構成例を示す図であり、図１（ａ）は当該パワーモジュールの内部構造を示す平面図、図１（ｂ）は当該パワーモジュールの内部構造を示す側面図、図１（ｃ）は当該パワーモジュールの回路構成を示す回路図である。図１には、パワーモジュールの一部（１アーム分）を代表的に示しているが、実際のパワーモジュールは、図１に示す構成を１つまたは複数個備えている。 <Embodiment 1>
1A and 1B are diagrams showing a configuration example of a power module which is a semiconductor device according to the first embodiment, FIG. 1A is a plan view showing an internal structure of the power module, and FIG. 1B is the power. A side view showing the internal structure of the module, FIG. 1C is a circuit diagram showing the circuit configuration of the power module. Although a part of the power module (for one arm) is typically shown in FIG. 1, the actual power module has one or a plurality of configurations shown in FIG.

図１（ａ）および図１（ｂ）のように、実施の形態１のパワーモジュールは、薄板状の金属製のリードフレーム３１，３２と、リードフレーム３１に搭載されたＩＧＢＴ１０およびＦＷＤ２０の各チップとがモールド樹脂３０によって封止された構造を持つトランスファーモールド型のパワーモジュールである。 As shown in FIGS. 1 (a) and 1 (b), the power module of the first embodiment includes thin metal lead frames 31 and 32 and chips of the IGBT 10 and FWD 20 mounted on the lead frame 31. Is a transfer mold type power module having a structure sealed by a mold resin 30.

ＩＧＢＴ１０は、主電流のオン（導通）、オフ（遮断）を切り替えるスイッチング素子である。ＩＧＢＴ１０の上面には、第１の主電極であるエミッタ電極１１と制御電極であるゲート電極１２とが形成されており、ＩＧＢＴ１０の下面（リードフレーム３１と接する面）には、第２の主電極であるコレクタ電極（不図示）が形成されている。さらに、本実施の形態のＩＧＢＴ１０の上面には、エミッタ電極１１およびゲート電極１２から絶縁された導電性パターン１３（第１の導電性パターン）が形成されている。 The IGBT 10 is a switching element that switches the main current on (conducting) and off (blocking). An emitter electrode 11 which is a first main electrode and a gate electrode 12 which is a control electrode are formed on the upper surface of the IGBT 10, and a second main electrode is formed on the lower surface of the IGBT 10 (the surface in contact with the lead frame 31). A collector electrode (not shown) is formed. Further, a conductive pattern 13 (first conductive pattern) insulated from the emitter electrode 11 and the gate electrode 12 is formed on the upper surface of the IGBT 10 of the present embodiment.

ＦＷＤ２０は、ＩＧＢＴ１０のターンオフ時に生じる還流電流を流すダイオード素子である。ＦＷＤ２０の上面には、第１の主電極であるアノード電極２１が形成されており、ＦＷＤ２０の下面（リードフレーム３１と接する面）には、第２の主電極であるカソード電極（不図示）が形成されている。さらに、本実施の形態のＦＷＤ２０の上面には、アノード電極２１から絶縁された導電性パターン２２（第２の導電性パターン）が形成されている。 The FWD 20 is a diode element that carries a reflux current generated at the turn-off of the IGBT 10. An anode electrode 21 which is a first main electrode is formed on the upper surface of the FWD 20, and a cathode electrode (not shown) which is a second main electrode is formed on the lower surface of the FWD 20 (the surface in contact with the lead frame 31). It is formed. Further, a conductive pattern 22 (second conductive pattern) insulated from the anode electrode 21 is formed on the upper surface of the FWD 20 of the present embodiment.

ＩＧＢＴ１０のエミッタ電極１１は、ワイヤ４１を通してＦＷＤ２０のアノード電極２１と接続されており、ＩＧＢＴ１０のコレクタ電極は、リードフレーム３１を通してＦＷＤ２０のカソード電極と接続されている。よって、ＩＧＢＴ１０およびＦＷＤ２０は、それらが互いに並列に接続した並列回路を構成している。また、ＦＷＤ２０のアノード電極２１は、ワイヤ４２を通してリードフレーム３２と接続されている。ワイヤ４１，４２は、ＩＧＢＴ１０がオンしたときに主電流が流れる経路となる。以下、ワイヤ４１，４２を「主電流ワイヤ」と称す。 The emitter electrode 11 of the IGBT 10 is connected to the anode electrode 21 of the FWD 20 through a wire 41, and the collector electrode of the IGBT 10 is connected to the cathode electrode of the FWD 20 through a lead frame 31. Therefore, the IGBT 10 and the FWD 20 form a parallel circuit in which they are connected in parallel to each other. Further, the anode electrode 21 of the FWD 20 is connected to the lead frame 32 through the wire 42. The wires 41 and 42 serve as a path through which the main current flows when the IGBT 10 is turned on. Hereinafter, the wires 41 and 42 will be referred to as "main current wires".

リードフレーム３１は、ＩＧＢＴ１０およびＦＷＤ２０を搭載するダイパッドであるとともに、一部がモールド樹脂３０から突出することでＩＧＢＴ１０のコレクタ側の外部接続端子としても機能する。リードフレーム３２は、一部がモールド樹脂３０から突出することでＩＧＢＴ１０のエミッタ側の外部接続端子として機能する。 The lead frame 31 is a die pad on which the IGBT 10 and FWD 20 are mounted, and also functions as an external connection terminal on the collector side of the IGBT 10 by partially projecting from the mold resin 30. The lead frame 32 functions as an external connection terminal on the emitter side of the IGBT 10 by partially projecting from the mold resin 30.

本実施の形態のパワーモジュールには、ＩＧＢＴ１０の駆動回路である駆動ＩＣ５０が生成する制御電圧をＩＧＢＴ１０のゲート電極１２に入力するための駆動電圧配線５１と、駆動ＩＣ５０に基準電位を供給するための基準電位配線５２とが設けられている。なお、駆動ＩＣ５０は、パワーモジュールに内蔵されてもよいし、パワーモジュールに外付けされてもよい。駆動電圧配線５１は、ＩＧＢＴ１０のゲート電極１２に接続される。基準電位配線５２は、ＩＧＢＴ１０のエミッタ配線の電圧降下をゲートに帰還させる負帰還量に応じてその接続先が変更される。 The power module of the present embodiment includes a drive voltage wiring 51 for inputting a control voltage generated by the drive IC 50, which is a drive circuit of the IGBT 10, to the gate electrode 12 of the IGBT 10, and a drive voltage wiring 51 for supplying a reference potential to the drive IC 50. A reference potential wiring 52 is provided. The drive IC 50 may be built in the power module or externally attached to the power module. The drive voltage wiring 51 is connected to the gate electrode 12 of the IGBT 10. The connection destination of the reference potential wiring 52 is changed according to the amount of negative feedback that feeds back the voltage drop of the emitter wiring of the IGBT 10 to the gate.

図１（ａ）の例では、基準電位配線５２は、ＩＧＢＴ１０の導電性パターン１３に接続されている。また、導電性パターン１３は、ワイヤ６１を通してＦＷＤ２０の導電性パターン２２に接続され、導電性パターン２２は、ワイヤ６２を通してリードフレーム３２に接続されている。すなわち、基準電位配線５２は、直列接続された導電性パターン１３および導電性パターン２２を通して、エミッタ側の外部接続端子であるリードフレーム３２に接続されている。 In the example of FIG. 1A, the reference potential wiring 52 is connected to the conductive pattern 13 of the IGBT 10. Further, the conductive pattern 13 is connected to the conductive pattern 22 of the FWD 20 through the wire 61, and the conductive pattern 22 is connected to the lead frame 32 through the wire 62. That is, the reference potential wiring 52 is connected to the lead frame 32, which is an external connection terminal on the emitter side, through the conductive pattern 13 and the conductive pattern 22 connected in series.

よって、図１（ａ）の構成では、図１（ｃ）の回路図のように、ＩＧＢＴ１０のエミッタと基準電位配線５２との間に、直列接続された主電流ワイヤ４１および主電流ワイヤ４２が介在する回路構成となる。そのため、図１（ａ）の構成によれば、主電流ワイヤ４１の配線インピーダンスＺ４１および主電流ワイヤ４２の配線インピーダンスＺ４２による電圧降下を利用した負帰還効果を得ることができる。 Therefore, in the configuration of FIG. 1A, as shown in the circuit diagram of FIG. 1C, the main current wire 41 and the main current wire 42 connected in series between the emitter of the IGBT 10 and the reference potential wiring 52 are provided. It has an intervening circuit configuration. Therefore, according to the configuration of FIG. 1A, a negative feedback effect can be obtained by utilizing the voltage drop due to the wiring impedance Z 41 of the main current wire 41 and the wiring impedance Z 42 of the main current wire 42.

ここで、基準電位配線５２は、必要とされる負帰還量に応じて、導電性パターン１３ではなく、エミッタ電極１１に接続される場合や、パワーモジュールに外付けされる外部配線に接続される場合もある。また、ワイヤ６１は、導電性パターン１３と導電性パターン２２とを接続するのではなく、導電性パターン１３とアノード電極２１とを接続する場合もある。そのため、エミッタ電極１１には、主電流ワイヤ４１の接続領域とは別に、基準電位配線５２を接続可能な領域が確保されており、アノード電極２１には、主電流ワイヤ４１，４２の接続領域とは別に、ワイヤ６１を接続可能な領域が確保されている。 Here, the reference potential wiring 52 is connected to the emitter electrode 11 instead of the conductive pattern 13 or to an external wiring externally attached to the power module, depending on the amount of negative feedback required. In some cases. Further, the wire 61 may not connect the conductive pattern 13 and the conductive pattern 22, but may connect the conductive pattern 13 and the anode electrode 21. Therefore, the emitter electrode 11 has a region to which the reference potential wiring 52 can be connected, in addition to the connection region of the main current wire 41, and the anode electrode 21 has a connection region of the main current wires 41 and 42. Separately, an area to which the wire 61 can be connected is secured.

実施の形態１のパワーモジュールにおいて、主電流ワイヤ４１の配線インピーダンスＺ４１による電圧降下のみを利用した負帰還効果を得る場合の例を、図２に示す。図２（ａ）はパワーモジュールの内部構造を示す平面図、図２（ｂ）はパワーモジュールの内部構造を示す側面図、図２（ｃ）はパワーモジュールの回路構成を示す回路図である。この場合、基準電位配線５２は、ＩＧＢＴ１０の導電性パターン１３に接続され、導電性パターン１３は、ワイヤ６１を通してＦＷＤ２０のアノード電極２１に接続される（ワイヤ６２は不要）。それにより、図２（ｃ）の回路図のように、ＩＧＢＴ１０のエミッタと基準電位配線５２との間に、主電流ワイヤ４１（配線インピーダンスＺ４１）が介在する回路構成となる。 FIG. 2 shows an example of obtaining a negative feedback effect using only the voltage drop due to the wiring impedance Z 41 of the main current wire 41 in the power module of the first embodiment. FIG. 2A is a plan view showing the internal structure of the power module, FIG. 2B is a side view showing the internal structure of the power module, and FIG. 2C is a circuit diagram showing the circuit configuration of the power module. In this case, the reference potential wiring 52 is connected to the conductive pattern 13 of the IGBT 10, and the conductive pattern 13 is connected to the anode electrode 21 of the FWD 20 through the wire 61 (the wire 62 is unnecessary). As a result, as shown in the circuit diagram of FIG. 2C, the circuit configuration is such that the main current wire 41 (wiring impedance Z 41 ) is interposed between the emitter of the IGBT 10 and the reference potential wiring 52.

また、実施の形態１のパワーモジュールにおいて、負帰還効果を利用しない場合の例を、図３に示す。図３（ａ）はパワーモジュールの内部構造を示す平面図、図３（ｂ）はパワーモジュールの内部構造を示す側面図、図３（ｃ）はパワーモジュールの回路構成を示す回路図である。この場合、基準電位配線５２は、ＩＧＢＴ１０のエミッタ電極１１に接続される（ワイヤ６１，６２は不要）。それにより、図３（ｃ）の回路図のように、ＩＧＢＴ１０のエミッタに基準電位配線５２が直接接続する回路構成となる。 Further, FIG. 3 shows an example in which the negative feedback effect is not used in the power module of the first embodiment. FIG. 3A is a plan view showing the internal structure of the power module, FIG. 3B is a side view showing the internal structure of the power module, and FIG. 3C is a circuit diagram showing the circuit configuration of the power module. In this case, the reference potential wiring 52 is connected to the emitter electrode 11 of the IGBT 10 (wires 61 and 62 are unnecessary). As a result, as shown in the circuit diagram of FIG. 3C, the circuit configuration is such that the reference potential wiring 52 is directly connected to the emitter of the IGBT 10.

このように実施の形態１に係るパワーモジュールでは、パワーモジュールの製造時に基準電位配線５２の接続先を選択することによって、エミッタ配線の配線インピーダンスを用いた負帰還機能の強弱を調整することができる。 As described above, in the power module according to the first embodiment, the strength of the negative feedback function using the wiring impedance of the emitter wiring can be adjusted by selecting the connection destination of the reference potential wiring 52 at the time of manufacturing the power module. ..

また、図１（ａ）のように基準電位配線５２をリードフレーム３２に接続させる場合、その接続を導電性パターン１３，２２を通して行うことで、当該接続に必要なワイヤ６１，６２の長さは短くて済む。同様に、図２（ａ）のように基準電位配線５２をＦＷＤ２０のアノード電極２１に接続させる場合、その接続を導電性パターン１３を通して行うことで、当該接続に必要なワイヤ６１の長さは短くて済む。これにより、ワイヤ６１，６２が主電流ワイヤ４１，４２と干渉することが防止されるため、ワイヤ同士の干渉を防止するためのリードフレーム等を別途も受ける必要がない。よって、パワーモジュールのパッケージの小型化に寄与できる。 Further, when the reference potential wiring 52 is connected to the lead frame 32 as shown in FIG. 1A, the lengths of the wires 61 and 62 required for the connection can be reduced by connecting the reference potential wiring 52 through the conductive patterns 13 and 22. It can be short. Similarly, when the reference potential wiring 52 is connected to the anode electrode 21 of the FWD 20 as shown in FIG. 2A, the length of the wire 61 required for the connection is shortened by making the connection through the conductive pattern 13. It's done. As a result, the wires 61 and 62 are prevented from interfering with the main current wires 41 and 42, so that it is not necessary to separately receive a lead frame or the like for preventing interference between the wires. Therefore, it can contribute to the miniaturization of the power module package.

なお、図１の例のように、主電流ワイヤ４１の配線インピーダンスＺ４１および主電流ワイヤ４２の配線インピーダンスＺ４２による電圧降下を利用した負帰還効果を得る場合、例えば図４のように、パワーモジュールに外付けされる外部配線７０を通して、基準電位配線５２を外部接続端子としてのリードフレーム３２に接続させてもよい。図４の構成では、導電性パターン１３と導電性パターン２２は不使用となるが、回路構成は図１（ｃ）と同じになる。 When a negative feedback effect is obtained by utilizing the voltage drop due to the wiring impedance Z 41 of the main current wire 41 and the wiring impedance Z 42 of the main current wire 42 as in the example of FIG. 1, for example, as shown in FIG. 4, the power The reference potential wiring 52 may be connected to the lead frame 32 as the external connection terminal through the external wiring 70 externally attached to the module. In the configuration of FIG. 4, the conductive pattern 13 and the conductive pattern 22 are not used, but the circuit configuration is the same as that of FIG. 1 (c).

＜実施の形態２＞
実施の形態２では、パワーモジュールに、ＩＧＢＴとＦＷＤとの並列回路からなるアームが複数備えられた構成を示す。図５にその構成例を示す。図５（ａ）はパワーモジュールの内部構造を示す平面図、図５（ｂ）はパワーモジュールの回路構成を示す回路図である。図５には、パワーモジュールの２アーム分（上アームと下アーム）の構成を示しているが、パワーモジュールが備えるアームの数は３以上でもよい。 <Embodiment 2>
In the second embodiment, the power module is provided with a plurality of arms including a parallel circuit of an IGBT and an FWD. FIG. 5 shows an example of the configuration. FIG. 5A is a plan view showing the internal structure of the power module, and FIG. 5B is a circuit diagram showing the circuit configuration of the power module. Although FIG. 5 shows the configuration of two arms of the power module (upper arm and lower arm), the number of arms included in the power module may be three or more.

図５（ａ）のように、実施の形態２のパワーモジュールは、リードフレーム３１，３２，３３と、リードフレーム３１に搭載され下アームを構成するＩＧＢＴ１０ａおよびＦＷＤ２０ａと、リードフレーム３３に搭載され上アームを構成するＩＧＢＴ１０ｂおよびＦＷＤ２０ｂとがモールド樹脂３０によって封止された構造を持つトランスファーモールド型のパワーモジュールである。 As shown in FIG. 5A, the power module of the second embodiment is mounted on the lead frames 31, 32, 33, the IGBTs 10a and FWD 20a mounted on the lead frame 31 and forming the lower arm, and mounted on the lead frame 33. This is a transfer mold type power module having a structure in which the IGBT 10b and the FWD 20b constituting the arm are sealed with the mold resin 30.

ＩＧＢＴ１０ａの上面には、エミッタ電極１１ａおよびゲート電極１２ａと、それらから絶縁された導電性パターン１３ａとが形成されており、ＩＧＢＴ１０ａの下面（リードフレーム３１と接する面）にはコレクタ電極（不図示）が形成されている。 An emitter electrode 11a and a gate electrode 12a and a conductive pattern 13a insulated from them are formed on the upper surface of the IGBT 10a, and a collector electrode (not shown) is formed on the lower surface (the surface in contact with the lead frame 31) of the IGBT 10a. Is formed.

ＦＷＤ２０ａの上面には、アノード電極２１ａとそれから絶縁された導電性パターン２２ａとが形成されており、ＦＷＤ２０ａの下面（リードフレーム３１と接する面）にはカソード電極（不図示）が形成されている。 An anode electrode 21a and a conductive pattern 22a insulated from the anode electrode 21a are formed on the upper surface of the FWD 20a, and a cathode electrode (not shown) is formed on the lower surface (the surface in contact with the lead frame 31) of the FWD 20a.

ＩＧＢＴ１０ａのエミッタ電極１１ａは、主電流ワイヤ４１ａを通してＦＷＤ２０ａのアノード電極２１ａと接続されており、ＩＧＢＴ１０ａのコレクタ電極は、リードフレーム３１を通してＦＷＤ２０ａのカソード電極と接続されている。よって、ＩＧＢＴ１０ａおよびＦＷＤ２０ａは、それらが互いに並列に接続した並列回路を構成している。また、ＦＷＤ２０ａのアノード電極２１ａは、主電流ワイヤ４２ａを通してリードフレーム３２に接続されている。 The emitter electrode 11a of the IGBT 10a is connected to the anode electrode 21a of the FWD 20a through the main current wire 41a, and the collector electrode of the IGBT 10a is connected to the cathode electrode of the FWD 20a through the lead frame 31. Therefore, the IGBT 10a and the FWD 20a form a parallel circuit in which they are connected in parallel to each other. Further, the anode electrode 21a of the FWD 20a is connected to the lead frame 32 through the main current wire 42a.

ＩＧＢＴ１０ｂの上面には、エミッタ電極１１ｂおよびゲート電極１２ｂと、それらから絶縁された導電性パターン１３ｂとが形成されており、ＩＧＢＴ１０ｂの下面（リードフレーム３３と接する面）にはコレクタ電極（不図示）が形成されている。 An emitter electrode 11b and a gate electrode 12b and a conductive pattern 13b insulated from them are formed on the upper surface of the IGBT 10b, and a collector electrode (not shown) is formed on the lower surface of the IGBT 10b (the surface in contact with the lead frame 33). Is formed.

ＦＷＤ２０ｂの上面には、アノード電極２１ｂとそれから絶縁された導電性パターン２２ｂとが形成されており、ＦＷＤ２０ｂの下面（リードフレーム３３と接する面）にはカソード電極（不図示）が形成されている。 An anode electrode 21b and a conductive pattern 22b insulated from the anode electrode 21b are formed on the upper surface of the FWD 20b, and a cathode electrode (not shown) is formed on the lower surface (the surface in contact with the lead frame 33) of the FWD 20b.

ＩＧＢＴ１０ｂのエミッタ電極１１ｂは、主電流ワイヤ４１ｂを通してＦＷＤ２０ｂのアノード電極２１ｂと接続されており、ＩＧＢＴ１０ｂのコレクタ電極は、リードフレーム３１を通してＦＷＤ２０ｂのカソード電極と接続されている。よって、ＩＧＢＴ１０ｂおよびＦＷＤ２０ｂは、それらが互いに並列に接続した並列回路を構成している。また、ＦＷＤ２０ｂのアノード電極２１ｂは、主電流ワイヤ４２ｂを通してリードフレーム３１に接続されている。 The emitter electrode 11b of the IGBT 10b is connected to the anode electrode 21b of the FWD 20b through the main current wire 41b, and the collector electrode of the IGBT 10b is connected to the cathode electrode of the FWD 20b through the lead frame 31. Therefore, the IGBT 10b and the FWD 20b form a parallel circuit in which they are connected in parallel to each other. Further, the anode electrode 21b of the FWD 20b is connected to the lead frame 31 through the main current wire 42b.

本実施の形態のパワーモジュールには、下アーム用の駆動ＩＣ５０ａが生成する制御電圧をＩＧＢＴ１０ａのゲート電極１２ａに入力するための駆動電圧配線５１ａと、駆動ＩＣ５０ａに基準電位を供給するための基準電位配線５２ａと、上アーム用の駆動ＩＣ５０ｂが生成する制御電圧をＩＧＢＴ１０ｂのゲート電極１２ｂに入力するための駆動電圧配線５１ｂと、駆動ＩＣ５０ｂに基準電位を供給するための基準電位配線５２ｂとが設けられている。なお、駆動ＩＣ５０ａ，５０ｂは、パワーモジュールに内蔵されてもよいし、パワーモジュールに外付けされてもよい。 In the power module of the present embodiment, the drive voltage wiring 51a for inputting the control voltage generated by the drive IC 50a for the lower arm to the gate electrode 12a of the IGBT 10a and the reference voltage for supplying the reference voltage to the drive IC 50a The wiring 52a, the drive voltage wiring 51b for inputting the control voltage generated by the drive IC 50b for the upper arm to the gate electrode 12b of the IGBT 10b, and the reference potential wiring 52b for supplying the reference potential to the drive IC 50b are provided. ing. The drive ICs 50a and 50b may be built in the power module or externally attached to the power module.

駆動電圧配線５１ａは、ＩＧＢＴ１０ａのゲート電極１２ａに接続され、駆動電圧配線５１ｂは、ＩＧＢＴ１０ｂのゲート電極１２ｂに接続される。基準電位配線５２ａは、ＩＧＢＴ１０ａのエミッタ配線の電圧降下をＩＧＢＴ１０ａのゲートに帰還させる負帰還量に応じてその接続先が変更される。同様に、基準電位配線５２ｂは、ＩＧＢＴ１０ｂのエミッタ配線の電圧降下をＩＧＢＴ１０ｂのゲートに帰還させる負帰還量に応じてその接続先が変更される。 The drive voltage wiring 51a is connected to the gate electrode 12a of the IGBT 10a, and the drive voltage wiring 51b is connected to the gate electrode 12b of the IGBT 10b. The connection destination of the reference potential wiring 52a is changed according to the amount of negative feedback that returns the voltage drop of the emitter wiring of the IGBT 10a to the gate of the IGBT 10a. Similarly, the connection destination of the reference potential wiring 52b is changed according to the amount of negative feedback that returns the voltage drop of the emitter wiring of the IGBT 10b to the gate of the IGBT 10b.

実施の形態２のパワーモジュールでは、負帰還量の調整をアーム（ＩＧＢＴとＦＷＤとの並列回路）ごとに行うことができる。すなわち、複数のアームのそれぞれにおいて、基準電位配線は、
（ａ）ＩＧＢＴのエミッタ電極に直接接続
（ｂ）ＩＧＢＴ上の導電性パターン（第１の導電性パターン）を通してＦＷＤのアノード電極に接続
（ｃ）ＩＧＢＴ上の導電性パターン（第１の導電性パターン）およびＦＷＤ上の導電性パターン（第２の導電性パターン）を通して外部接続端子に接続
（ｄ）外部配線を通して外部接続端子に接続
のうちの何れかの方法で、ＩＧＢＴのエミッタ電極と電気的に接続されればよい。 In the power module of the second embodiment, the negative feedback amount can be adjusted for each arm (parallel circuit of the IGBT and FWD). That is, in each of the plurality of arms, the reference potential wiring is
(A) Directly connected to the emitter electrode of the IGBT (b) Connected to the anode electrode of the FWD through the conductive pattern (first conductive pattern) on the IGBT (c) Conductive pattern on the IGBT (first conductive pattern) ) And connect to the external connection terminal through the conductive pattern (second conductive pattern) on the FWD (d) Connect to the external connection terminal through the external wiring, electrically with the emitter electrode of the IGBT by either method. All you have to do is connect.

図５の例では、下アームにおいて、駆動ＩＣ５０ａの基準電位配線５２ａを、外部配線７０ａを通してリードフレーム３２に接続させることで、主電流ワイヤ４１ａの配線インピーダンスＺ４１ａおよび主電流ワイヤ４２の配線インピーダンスＺ４２ａによる電圧降下を利用した負帰還効果を得ている。また、上アームにおいては、駆動ＩＣ５０ｂの基準電位配線５２ｂを、導電性パターン１３ｂ，２２ｂおよびワイヤ６１ｂ，６２ｂを通してリードフレーム３１に接続させることで、主電流ワイヤ４１ｂの配線インピーダンスＺ４１ｂおよび主電流ワイヤ４２ｂの配線インピーダンスＺ４２ｂによる電圧降下を利用した負帰還効果を得ている。 In the example of FIG. 5, in the lower arm, the reference potential wiring 52a of the drive IC 50a is connected to the lead frame 32 through the external wiring 70a, so that the wiring impedance Z 41a of the main current wire 41a and the wiring impedance Z of the main current wire 42 A negative feedback effect is obtained by utilizing the voltage drop due to 42a . Further, in the upper arm, the reference potential wiring 52b of the drive IC 50b is connected to the lead frame 31 through the conductive patterns 13b and 22b and the wires 61b and 62b, so that the wiring impedance Z 41b of the main current wire 41b and the main current wire are connected. A negative feedback effect is obtained by utilizing the voltage drop due to the wiring impedance Z 42b of 42b .

以上の実施の形態では、スイッチング素子をしてＩＧＢＴが用いられた例を示したが、スイッチング素子はこれに限られず、例えばＭＯＳＦＥＴでもよい。また、スイッチング素子およびＦＷＤの材料としては、シリコン（Ｓｉ）の他、例えばＳｉＣやＧａＮなどのワイドギャップ半導体が用いられてもよい。ワイドギャップ半導体によって構成されるスイッチング素子やダイオード素子は、耐電圧性が高く、許容電流密度も高い。そのため、スイッチング素子およびＦＷＤをワイドギャップ半導体により構成することで、パワーモジュールのより一層の小型化に寄与できる。 In the above embodiment, an example in which the IGBT is used as the switching element is shown, but the switching element is not limited to this, and for example, a MOSFET may be used. Further, as the material of the switching element and the FWD, in addition to silicon (Si), a wide-gap semiconductor such as SiC or GaN may be used. Switching elements and diode elements made of wide-gap semiconductors have high withstand voltage resistance and high allowable current density. Therefore, by configuring the switching element and the FWD with a wide-gap semiconductor, it is possible to contribute to further miniaturization of the power module.

なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略したりすることが可能である。 In the present invention, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted within the scope of the invention.

１０ ＩＧＢＴ、１１，１１ａ，１１ｂ エミッタ電極、１２，１２ａ，１２ｂ ゲート電極、１３，１３ａ，１３ｂ 導電性パターン、２０，２０ａ，２０ｂ ＦＷＤ、２１，２１ａ，２１ｂ アノード電極、２２，２２ａ，２２ｂ 導電性パターン、３０ モールド樹脂、３１，３２，３３ リードフレーム、４１，４２，４１ａ，４２ａ，４１ｂ，４２ｂ 主電流ワイヤ、５０，５０ａ，５０ｂ 駆動ＩＣ、５１，５１ａ，５１ｂ 駆動電圧配線、５２，５２ａ，５２ｂ 基準電位配線、６１，６２，６１ｂ，６２ｂ ワイヤ、７０，７０ａ 外部配線。 10 IGBT, 11, 11a, 11b Emitter electrode, 12, 12a, 12b Gate electrode, 13, 13a, 13b Conductive pattern, 20, 20a, 20b FWD, 21, 21, 21a, 21b Anode electrode, 22, 22a, 22b Conductivity Pattern, 30 mold resin, 31, 32, 33 lead frame, 41, 42, 41a, 42a, 41b, 42b main current wire, 50, 50a, 50b drive IC, 51, 51a, 51b drive voltage wiring, 52, 52a, 52b reference potential wiring, 61, 62, 61b, 62b wire, 70, 70a external wiring.

Claims (8)

スイッチング素子と、
前記スイッチング素子に並列接続されたフリーホイールダイオードと、
を備え、
前記スイッチング素子は、その表面上に、前記スイッチング素子の主電極および制御電極から絶縁された第１の導電性パターンを有し、
前記フリーホイールダイオードは、その表面上に、前記フリーホイールダイオードの主電極から絶縁された第２の導電性パターンを有する、
半導体装置。 Switching element and
A freewheel diode connected in parallel to the switching element,
With
The switching element has a first conductive pattern on its surface that is insulated from the main electrode and the control electrode of the switching element.
The freewheel diode has a second conductive pattern on its surface that is insulated from the main electrode of the freewheel diode.
Semiconductor device. 前記スイッチング素子の前記主電極と前記フリーホイールダイオードの前記主電極とを接続する第１のワイヤと、
前記フリーホイールダイオードの前記主電極と外部接続端子とを接続する第２のワイヤと、
前記スイッチング素子の前記制御電極に制御電圧を入力する駆動回路に基準電位を供給するための基準電位配線と、
をさらに備える、
請求項１に記載の半導体装置。 A first wire connecting the main electrode of the switching element and the main electrode of the freewheel diode, and
A second wire connecting the main electrode of the freewheel diode and the external connection terminal,
A reference potential wiring for supplying a reference potential to a drive circuit that inputs a control voltage to the control electrode of the switching element, and
Further prepare
The semiconductor device according to claim 1. 前記基準電位配線は、前記第１の導電性パターンを通して、前記フリーホイールダイオードの前記主電極に接続されている、
請求項２に記載の半導体装置。 The reference potential wiring is connected to the main electrode of the freewheel diode through the first conductive pattern.
The semiconductor device according to claim 2. 前記基準電位配線は、直列接続された前記第１の導電性パターンおよび前記第２の導電性パターンを通して、前記外部接続端子に接続されている、
請求項２に記載の半導体装置。 The reference potential wiring is connected to the external connection terminal through the first conductive pattern and the second conductive pattern connected in series.
The semiconductor device according to claim 2. 前記スイッチング素子と前記フリーホイールダイオードとの並列回路を複数備え、
複数の前記並列回路のそれぞれが、
前記スイッチング素子の前記主電極と前記フリーホイールダイオードの前記主電極とを接続する第１のワイヤと、
前記フリーホイールダイオードの前記主電極と外部接続端子とを接続する第２のワイヤと、
前記スイッチング素子の前記制御電極に制御電圧を入力する駆動回路に基準電位を供給するための基準電位配線と、
を備え、
複数の前記並列回路のそれぞれにおいて、前記基準電位配線は、
（ａ）前記スイッチング素子の前記主電極に直接接続
（ｂ）前記第１の導電性パターンを通して前記フリーホイールダイオードの前記主電極に接続
（ｃ）前記第１の導電性パターンおよび前記第２の導電性パターンを通して前記外部接続端子に接続
（ｄ）外部配線を通して前記外部接続端子に接続
のうちの何れかの方法で、前記スイッチング素子の前記主電極と電気的に接続されている、
請求項１に記載の半導体装置。 A plurality of parallel circuits of the switching element and the freewheel diode are provided.
Each of the plurality of parallel circuits
A first wire connecting the main electrode of the switching element and the main electrode of the freewheel diode, and
A second wire connecting the main electrode of the freewheel diode and the external connection terminal,
A reference potential wiring for supplying a reference potential to a drive circuit that inputs a control voltage to the control electrode of the switching element, and
With
In each of the plurality of parallel circuits, the reference potential wiring is
(A) Directly connected to the main electrode of the switching element (b) Connected to the main electrode of the freewheel diode through the first conductive pattern (c) The first conductive pattern and the second conductive pattern Connected to the external connection terminal through the sex pattern (d) Electrically connected to the main electrode of the switching element by any of the methods of connecting to the external connection terminal through external wiring.
The semiconductor device according to claim 1. トランスファーモールド型のパッケージを有する、
請求項１から請求項５のいずれか一項に記載の半導体装置。 Has a transfer mold type package,
The semiconductor device according to any one of claims 1 to 5. 前記スイッチング素子は、ワイドギャップ半導体を用いて形成されている、
請求項１から請求項６のいずれか一項に記載の半導体装置。 The switching element is formed by using a wide-gap semiconductor.
The semiconductor device according to any one of claims 1 to 6. 前記スイッチング素子は、ＩＧＢＴまたはＭＯＳＦＥＴである、
請求項１から請求項７のいずれか一項に記載の半導体装置。 The switching element is an IGBT or MOSFET.
The semiconductor device according to any one of claims 1 to 7.
JP2019095061A 2019-05-21 2019-05-21 semiconductor equipment Active JP7138596B2 (en)

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