CN216928587U - Semiconductor module - Google Patents
Semiconductor module Download PDFInfo
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- CN216928587U CN216928587U CN202220679936.1U CN202220679936U CN216928587U CN 216928587 U CN216928587 U CN 216928587U CN 202220679936 U CN202220679936 U CN 202220679936U CN 216928587 U CN216928587 U CN 216928587U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides a semiconductor module which contributes to reduction of components mounted on a circuit board. The semiconductor module of the present invention is characterized by comprising a lead frame having conductivity and comprising a die pad and an external terminal, a power chip, a control chip and a rectifier chip being mounted on the die pad and resin-molded, the control chip having a GND electrode on a back surface thereof, the rectifier chip having a cathode electrode on a back surface thereof, the control chip and the rectifier chip being mounted on a common die pad, the GND electrode of the control chip and the cathode electrode of the rectifier chip being electrically connected to the die pad, the die pad being electrically connected to a source electrode of the power chip, and the semiconductor module comprising an external terminal led out from the die pad.
Description
Technical Field
The present invention relates to a semiconductor module, and more particularly, to a semiconductor module which contributes to reduction of components mounted on a circuit board.
Background
A general semiconductor Module is called an Intelligent Power Module (IPM), and is formed by integrating various drive circuits, control circuits, protection circuits, and the like using Power chips (Power elements). The semiconductor module is mounted on a substrate of an electrical appliance product such as an air conditioner.
For example, patent document 1 discloses a circuit in which a 2 nd switching unit and a 1 st switching unit that is controlled synchronously are integrated into a MOSFET including an internal diode and a schottky barrier diode connected in parallel to the internal diode, and a semiconductor device is mounted on a wiring substrate.
Patent document 1: japanese patent No. 3291441
Patent document 2: chinese utility model No. 209266395U gazette
However, the prior art is a non-insulated flyback (chopper) circuit for low voltage input voltages. Therefore, the GND of the control circuit can be commonly connected to the output voltage GND. However, when a high-voltage input voltage is converted to a low voltage and output, as shown in fig. 1, it is necessary to change the PNP transistor, which increases the driving power when a high voltage is input, to a high-withstand-voltage N-type MOSFET. Therefore, the GND of the control circuit is connected to the source terminal of the MOSFET so that the control circuit drives the high-withstand-voltage N-type MOSFET.
Here, the GND of the control circuit is separated from the GND of the output Vout, and therefore the voltage of the output Vout cannot be detected. Thus, instead, the control circuit detects the voltage of the auxiliary winding of reactor L1 in proportion to the output Vout. Thus, the control circuit controls the high-voltage N-type MOSFET to be turned on and off so that the voltage of the auxiliary winding is constant, thereby performing constant voltage control on the output Vout voltage.
Further, the related art package structure may separate the power side external terminal from the control side external terminal, but in such a configuration, since it is a structure in which the GND terminal of the IC is separated from the cathode terminal of the diode, the wiring grows. That is, there is a problem that voltage fluctuation due to GND wiring of the IC occurs and the operation of the IC becomes unstable.
SUMMERY OF THE UTILITY MODEL
The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor module structure in which a diode is incorporated in a semiconductor module, an IC and the diode are mounted on the same die pad, and a common external terminal is led out from the die pad, thereby reducing circuit components of a non-insulated chopper.
In order to solve the above problem, the present invention adopts the following configuration.
The semiconductor module of the present invention is characterized in that,
the semiconductor module includes a lead frame having conductivity and including a die pad and an external terminal,
the power chip, the control chip and the rectifier chip are mounted on the bare chip bonding pad, resin molding is carried out,
the control chip has a GND electrode on the back side,
the rectifying chip has a cathode electrode on the back surface,
the control chip and the rectifying chip are mounted on the common bare chip bonding pad,
electrically connecting a GND electrode of the control chip and a cathode electrode of the rectifier chip with the die pad,
the die pad is electrically connected with a source electrode of the power chip,
the semiconductor module includes the external terminal led out from the die pad.
In the semiconductor module, the GND of the common die pad is a GND whose potential changes to a floating potential of a high voltage or a constant voltage according to an on/off operation of the power chip.
In the semiconductor module, the external terminal is arranged so that a GND terminal connected to the cathode electrode of the rectifier chip and a power source GND terminal connected to the anode electrode of the rectifier chip are led out from one side of the resin mold to the same row, thereby ensuring an insulation distance between the terminals.
In the semiconductor module, the external terminal is disposed so that a GND terminal connected to the cathode electrode of the rectifier chip and a power source GND terminal connected to the anode electrode of the rectifier chip are led out from the respective sides of the resin mold facing each other, and an insulation distance between the terminals is secured.
In the semiconductor module, a power supply GND terminal connected to the anode electrode of the rectifier chip is drawn out from one side of the resin mold and is disposed at one end portion.
In the semiconductor module, the power chip is an N-type MOSFET,
the control chip is an IC and is,
the rectifying chip is a high-voltage freewheeling diode.
According to the present invention, since the GND electrode of the control chip, the cathode electrode of the rectifier chip, and the source electrode of the power chip are electrically connected to each other and a common external terminal can be drawn out, a semiconductor module in which voltage variation due to wiring is suppressed and control operation is stable can be provided. Further, since circuit components can be reduced by incorporating the rectifier chip in the semiconductor module, the circuit board on which the semiconductor module is mounted can be reduced in size.
Drawings
Fig. 1 is a circuit diagram showing an example of use of a conventional semiconductor module.
Fig. 2 is a circuit diagram showing an example of use of the semiconductor module according to embodiment 1 of the present invention.
Fig. 3 is a top view of the internal structure of the semiconductor module according to embodiment 1 of the present invention.
Fig. 4 is a plan view of the internal structure of a semiconductor module according to modification 1 of embodiment 1 of the present invention.
Fig. 5 is a top view of the internal structure of a semiconductor module according to embodiment 2 of the present invention.
Fig. 6 is a plan view of the internal structure of a semiconductor module according to modification 1 of example 2 of the present invention.
Fig. 7 is a top view of the internal structure of a semiconductor module according to embodiment 3 of the present invention.
Fig. 8 is a plan view of the internal structure of a semiconductor module according to modification 1 of embodiment 3 of the present invention.
Description of the reference symbols
1: a lead frame; 2: a power chip; 3: a control chip; 4: a rectifying chip; 5: a wire; 6: resin moldings (resin mold); 10: a semiconductor module (8-pin); 11. 12, 13, 14, 15: a die pad; 20: an external terminal; 21-28: an external terminal (8-pin); 30: a semiconductor module (16 pin); 31-46: external terminals (16 pins).
Detailed Description
Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description.
[ example 1]
A semiconductor module according to embodiment 1 of the present invention will be described. Fig. 1 is a circuit diagram showing an example of use of a conventional semiconductor module. Fig. 2 is a circuit diagram showing an example of use of the semiconductor module according to embodiment 1 of the present invention. In the conventional use example, it is understood that the wiring distance between the diode (D1) and the ic (gnd) is long. In the present invention, the diode (D1) is incorporated in the package to shorten the wiring distance to the IC (GND).
Fig. 3 is a plan view showing an internal structure of a general DIP (Dual Inline Package) type Package. Fig. 3 is a schematic diagram for explaining the present invention.
The semiconductor module 10 shown in fig. 3 is an 8-pin package, and the power chip 2, the control chip 3, and the rectifier chip 4 are mounted on the die pad 11 of the lead frame 1 via a conductive bonding material or the like (not shown). The electrodes on the upper surfaces of the respective chips and the terminals are electrically connected by wires 5. These components are covered with a resin mold 6, and external terminals 20(21 to 28) are led out from the resin mold 6.
The lead frame 1 is made of a conductive material and includes a die pad 11 and external terminals 20(21 to 28). For example, the material is a flat metal of copper alloy.
The power chip 2 is an N-type semiconductor element including a MOSFET, an IGBT, a bipolar transistor, and the like. The control chip 3 is an IC chip.
The power chip 2 and the control chip 3 in fig. 3 are of an integrated one-chip type. The back of the chip is a common electrode, which is a source electrode of the power chip and a GND electrode of the control chip. The back surface is bonded to the die pad 11 via a conductive bonding material. For example, the conductive bonding material is solder. Each electrode on the front surface (upper surface) of the chip is electrically connected to an external terminal through a wire 5. For example, the wire 5 is a gold wire.
The rectifier chip 4 is a diode chip composed of SBD, FRD, MPS, SiC, or the like. The chip back surface is a cathode electrode, and the back surface is bonded to the die pad 11 via a conductive bonding material. The front surface (upper surface) of the chip is an anode electrode and is electrically connected to an external terminal via a wire 5.
Regarding the respective terminal functions, the external terminal 21 is the control power supply voltage Vcc, the external terminal 22 is the feedback FB, the external terminal 24 is the D/ST, the external terminal 25 is the power supply GND (anode), and the external terminal 27 is GND/source/cathode.
In addition, the external terminals 23 and 26 are not formed as empty pins. This ensures creepage distances between the leads from the external terminal 22 to the external terminal 24 and between the leads from the external terminal 25 to the external terminal 27.
The die pad 11 on which each chip is mounted and a part of the external terminals are covered with the resin mold 6. The resin mold 6 is, for example, an epoxy resin. Each external terminal 20 is partially covered by the resin mold 6, and the other end thereof protrudes to the outside.
By providing a single package for the power chip, the control chip, and the rectifier chip, a semiconductor module can be provided in which the circuit board is miniaturized, the switching loop is short, and noise can be reduced.
Further, since the chip is mounted on the common die pad in this manner, the GND external terminal of the control chip and the cathode external terminal of the rectifier chip can be set to the common terminal (the wiring is shortest), the wiring can be shortest, voltage fluctuation due to the wiring can be suppressed, and the operation of the control chip can be stabilized.
In addition, the number of wirings (L component) of the source electrode of the power chip and the cathode of the diode is reduced. Therefore, the switching loop is shortened with respect to the rectifying chip located outside the package, and noise generation can be suppressed.
The common die pad 11 is GND having a floating potential whose potential changes to a high voltage or a low voltage due to the on/off operation of the power chip 2. Since the source of the power chip 2, the GND of the control chip 3, and the cathode of the rectifier chip 4 can be connected at 1 point, the GND potential of the control chip 3 can be stabilized even if there is a change in the current flowing through the power chip 2 and the rectifier chip 4.
In the case of using a single chip product constituted by one die (chip) composed of a control chip and a power chip, the lead frame structure can be realized by a common die pad, and therefore the package design can be easily performed.
With this configuration, the package temperature rises due to heat generation of the power chip, the voltage drop of the output line due to the increase in the on-resistance of the power chip increases, and the output voltage drops. On the other hand, since the Vf characteristic of the rectifier chip decreases and the output voltage increases (there is a trade-off relationship), the load regulation can be automatically corrected (the output variation can be suppressed by canceling) by using this characteristic.
The GND terminal (external terminal 27) of the control chip connected to the cathode electrode of the rectifier chip and the power GND terminal (external terminal 25) connected to the anode electrode of the rectifier chip are drawn out from one side of the resin mold 6 on the same row, but since the external terminal 26 is a hollow pin, it is possible to arrange the terminals so that an insulation distance is secured.
Since the insulation distance is thus secured, a short-circuit test (an abnormal test ) between the GND external terminal and the power supply GND external terminal is not necessary.
This is because, in the high-voltage power supply product, in the safety standard (UL) drafted by the U.S. insurance company, it is necessary to perform a short-circuit test on main components of the power supply to confirm that ignition and burning are not caused. A single component or an adjacent lead terminal of an IC is targeted. However, the product is not intended to be drawn between the leads and between the leads on opposite sides of the double line.
The power supply GND terminal connected to the anode electrode of the rectifier chip is led out from one end of the resin mold 6. That is, by setting the package corner terminal to the power supply GND, the pattern design of the circuit board on which the semiconductor module is mounted can be easily performed.
Fig. 4 shows a semiconductor module according to modification 1 of embodiment 1 of the present invention. Here, the function of the external terminal 21 is shared between the control power supply voltage Vcc and the feedback FB. This can further increase the creepage distance between the leads from the external terminal 21 to the external terminal 24.
Next, a semiconductor module according to embodiment 2 of the present invention will be described. The power chip 2, the control chip 3, and the rectifier chip 4 in fig. 5 are each a separate chip type.
The die pad of the lead frame 1 is divided into two parts, i.e., a die pad 12 on which the power chip 2 is mounted, and a die pad 13 on which the control chip 3 and the rectifier chip 4 are mounted. This point is different from embodiment 1.
In the die pad 12, a drain electrode as a back surface of the power chip 3 is bonded via a conductive bonding material. External terminals 24 are led out from the die pad 12.
In the die pad 13, the GND electrode of the control chip 3 and the anode electrode of the rectifier chip 4 are bonded via a conductive bonding material. External terminals 27 and 28 are led out from the die pad 13.
The source electrode of the power chip 2 is electrically connected to the electrode of the control chip 3 via a wire 5. And is electrically connected from the electrode to the die pad 13 via a wire. That is, the die pad 13 is the same electrode as the GND electrode of the control chip 3.
Each external terminal functions in the same manner as in embodiment 1.
The back surface potential of the control chip 2 and the back surface potential of the rectifier chip 4 are constituted by the same die pad 13, separately from the back surface potential of the power chip 2. Thus, heat generated by the power chip can be prevented from being transmitted to the control chip and the rectifier chip through the die pad. Further, since the power chip 2 and the rectifier chip 4 are mounted in adjacent positions, mutual thermal interference is largely maintained, and variation in output voltage accompanying an increase in package temperature can be eliminated.
Fig. 6 is a semiconductor module according to modification 1 of embodiment 2 of the present invention. Here, the function of the external terminal 21 is shared between the control power supply voltage Vcc and the feedback FB, as in the semiconductor module of modification 1 of embodiment 1. This can further increase the creepage distance from the lead of the external terminal 21 to the lead of the external terminal 24.
Next, a semiconductor module according to embodiment 3 of the present invention will be described.
The semiconductor module 30 in fig. 7 is a DIP package of a 16-pin type.
The power chip 2, the control chip 3, and the rectification chip 4 are each a separate chip type.
The die pad is divided into two parts, i.e., a die pad 14 on which the power chip 2 is mounted and a die pad 15 on which the control chip 3 and the rectifier chip 4 are mounted.
In the die pad 14, a drain electrode as a back surface of the power chip 2 is bonded via a conductive bonding material. The leads of the external terminals 37 and 38, the leads of the external terminals 39 and 40, and the leads of the external terminals 41 and 42 are drawn from the die pad 14 as external terminals having a large width.
In the die pad 15, the GND electrode of the control chip 3 and the anode electrode of the rectifier chip 4 are bonded via a conductive bonding material. The leads as the external terminals 31 and 32 are drawn from the die pad 15 as external terminals having a large width.
In addition, the source electrode of the power chip is electrically connected to the electrode of the control chip via a wire. And is electrically connected from the electrode to the die pad 15 via a wire. That is, the die pad 15 is the same electrode as the GND electrode of the control chip 3. Thus, the source electrode of the power chip 2, the GND electrode of the control chip 3, and the anode electrode of the rectifier chip 4 are connected to the die pad 15 at 1 point, and the same effects as those of the above embodiment can be obtained.
Regarding each external terminal function, the external terminals 31 and 32 are the GND of the control chip 2/the cathode of the rectifier chip 4, the external terminal 33 is the feedback FB, the external terminal 34 is the control power supply voltage Vcc, the external terminal 5 is the OPC, the external terminals 37 and 38 are the D/ST, the external terminals 39 and 40 are the D/ST, the external terminals 41 and 42 are the D/ST, and the external terminal 46 is the power supply GND (anode).
Further, the external terminals 36, 43, 44, and 45 are not formed as empty pins. This ensures creepage distances between the lead of the external terminal 35 and the lead of the external terminal 37 and between the lead of the external terminal 42 and the lead of the external terminal 46.
The external terminals 31 and 32 (GND/cathode) and the external terminal 46 (power GND/anode) are a GND terminal connected to the cathode electrode of the rectifier chip and a power GND terminal connected to the anode electrode of the rectifier chip, and are drawn out from the respective sides of the resin mold facing each other, and therefore, the insulating distance between the terminals is secured.
Since the insulation distance is secured in this way, a short-circuit test (an abnormal test ) between the GND external terminal of the control chip and the GND external terminal of the power supply is not necessary.
Further, the external terminals 31, 32, the external terminals 37, 38, the external terminals 39, 40, and the external terminals 41, 42 are wide terminals in the form of two pins joined together. By using a wide terminal of the drain terminal/ground terminal, heat dissipation can be improved.
The resin molding 60 is the same as in example 1.
Fig. 8 shows a semiconductor module according to modification 1 of embodiment 3 of the present invention. Here, the function of the external terminal 33 is shared by Vcc and FB, as in the semiconductor module of modification 1 of embodiment 1. This can further increase the creepage distance from the lead of the external terminal 33 to the lead of the external terminal 35.
[ other examples ]
As described above, the embodiments for carrying out the present invention have been described, but it will be apparent to those skilled in the art from this disclosure that various alternative embodiments and examples can be realized.
Particularly in a non-insulated flyback (chopper) circuit, the power chip may be an N-type MOSFET, the control chip may be an IC, and the rectifying chip may be a high-voltage freewheeling diode (flyback diode). Thus, by incorporating the high-voltage flywheel diode into the semiconductor module package, it is possible to reduce the number of components of the non-insulated flyback circuit, and it is possible to provide a semiconductor module in which the pin arrangement can be made in consideration of simplification of the circuit board pattern layout and countermeasures against abnormality.
The package is of a DIP type, but may be of an SOP type, and the like, and the effect is the same.
The lead frame may also be surface treated by plating or the like to protect the surface. The back surface of the die pad of the lead frame may be exposed from the back surface of the resin mold of the semiconductor module, and may function as a heat sink.
Claims (6)
1. A semiconductor module is characterized in that a semiconductor chip is mounted on a substrate,
the semiconductor module includes a lead frame having conductivity and including a die pad and an external terminal,
the power chip, the control chip and the rectifier chip are mounted on the bare chip bonding pad, resin molding is carried out,
the control chip has a GND electrode on the back side,
the rectifying chip has a cathode electrode on the back surface,
the control chip and the rectifying chip are mounted on the common bare chip bonding pad,
electrically connecting a GND electrode of the control chip and a cathode electrode of the rectifier chip with the die pad,
the die pad is electrically connected with a source electrode of the power chip,
the semiconductor module includes the external terminal drawn out from the die pad.
2. The semiconductor module of claim 1,
the GND of the common die pad is a GND of a floating potential whose potential changes to a high voltage or a constant voltage according to an on/off action of the power chip.
3. The semiconductor module according to claim 1 or 2,
the external terminal is arranged to lead out a GND terminal connected to the cathode electrode of the rectifier chip and a power source GND terminal connected to the anode electrode of the rectifier chip from one side of the resin mold to the same row, thereby ensuring an insulation distance between the terminals.
4. The semiconductor module according to claim 1 or 2,
the external terminal is arranged such that a GND terminal connected to the cathode electrode of the rectifier chip and a power source GND terminal connected to the anode electrode of the rectifier chip are led out from the respective sides of the resin mold facing each other, and an insulation distance between the terminals is secured.
5. The semiconductor module according to claim 1 or 2,
the power supply GND terminal connected to the anode electrode of the rectifier chip is drawn out from one side of the resin mold and is disposed at one end portion.
6. The semiconductor module according to claim 1 or 2,
the power chip is an N-type MOSFET,
the control chip is an IC and is,
the rectifying chip is a high-voltage freewheeling diode.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220679936.1U CN216928587U (en) | 2022-03-25 | 2022-03-25 | Semiconductor module |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220679936.1U CN216928587U (en) | 2022-03-25 | 2022-03-25 | Semiconductor module |
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| CN216928587U true CN216928587U (en) | 2022-07-08 |
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| CN202220679936.1U Active CN216928587U (en) | 2022-03-25 | 2022-03-25 | Semiconductor module |
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