US7145224B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
US7145224B2
US7145224B2 US11041200 US4120005A US7145224B2 US 7145224 B2 US7145224 B2 US 7145224B2 US 11041200 US11041200 US 11041200 US 4120005 A US4120005 A US 4120005A US 7145224 B2 US7145224 B2 US 7145224B2
Authority
US
Grant status
Grant
Patent type
Prior art keywords
semiconductor
plate
chip
terminal
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US11041200
Other versions
US20050161785A1 (en )
Inventor
Tetsuya Kawashima
Akira Mishima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/29294Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247Connecting the strap to a bond pad of the item
    • H01L2224/40249Connecting the strap to a bond pad of the item the bond pad protruding from the surface of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73219Layer and TAB connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73221Strap and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/8485Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Abstract

In the semiconductor device, a control power MOSFET chip 2 is disposed on the input-side plate-like lead 5, and the drain terminal DT1 is formed on the rear surface of the chip 2, and the source terminal ST1 and gate terminal GT1 are formed on the principal surface of the chip 2, and the source terminal ST1 is connected to the plate-like lead for source 12. Furthermore, a synchronous power MOSFET chip 3 is disposed on the output-side plate-like lead 6, and the drain terminal DT2 is formed on the rear surface of the chip 3 and the output-side plate-like lead 6 is connected to the drain terminal DT2. Furthermore, source terminal ST2 and gate terminal GT2 are formed on the principal surface of the synchronous power MOSFET chip 3, and the source terminal ST2 is connected to the plate-like lead for source 13. The plate-like leads for source 12 and 13 are exposed, and therefore, it is possible to increase the heat dissipation capability of the MCM 1.

Description

CLAIM OF PRIORITY

Claim of priority the present application claims priority from Japanese application serial no. 2004-020474, filed on Jan. 28, 2004, the content of which is hereby incorporated by reference into this application.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device, and specifically to a technology which effectively applies to a semiconductor device in which a plurality of semiconductor chips are encapsulated in a sealed body.

In a conventional semiconductor device, the rear surface of a heat sink (first conductive member) is soldered on the upper surface of each semiconductor chip, and the upper surface of a second conductive member is soldered on the rear surface of each semiconductor chip. Furthermore, the rear surface of a third conductive member is soldered on the upper surface of the heat sink, and the land of the prescribed semiconductor chip has an electrical connection to a control terminal via a bonding wire. The semiconductor chips, heat sink, upper surface of the second conductive member, rear surface of the third conductive member, and a part of the bonding wire and control terminal are encapsulated within resin. Japanese Application Patent Laid-open Publication No. 2002-110893, FIG. 1.

In the above semiconductor device, an external cooling member abuts on the rear surface of the second conductive member with a plate-like insulating member interposed in order to accelerate the heat dissipation. See Japanese Application Patent Laid-open Publication No. 2003-46036, FIG. 1.

SUMMARY OF THE INVENTION

Recently, semiconductor devices have been highly integrated and the size of the device has been reduced. Especially, a semiconductor device in which a plurality of semiconductor chips are encapsulated within an insulating material is called a multi-chip-module (MCM) and is widely developed.

One application of the above-mentioned MCM is a switching circuit used for a power-supply circuit. Among those, an insulated DC/DC converter is widely used for information devices such as personal computers. Such products are required to be highly efficient and small because central processing units (CPU) are using larger current and higher frequency.

A DC/DC converter consists of two power MOSFETS (Metal Oxide Semiconductor Field Effect Transistor), one for control and one for synchronization, a driver IC (integrated circuit) for turning the MOSFETS on and off, and other components such as a choke coil and capacitor. Generally, in an MCM for a DC/DC converter, two power MOSFETS and one driver IC are encapsulated in one package.

The objective of encapsulating a plurality of semiconductor chips in one package (sealed body) is to reduce the package area as well as reduce parasitic components such as parasitic inductances and resistances located on the circuit.

Moreover, because a power-supply circuit uses large current and high frequency, parasitic components cause significant power loss. To prevent that problem, it is necessary to shorten the wiring patterns between chips, between the driver IC and MOSFETS, and between the output terminal and a load. In a power-supply MCM, a driver IC and MOSFETS are located near each other and encapsulated together, and semiconductor elements constituting a power-supply circuit are integrated in one package. This configuration allows the MCM to be mounted extremely close to the load. Therefore, it is expected that the MCM will be the most commonly used power-supply device.

That is, when compared to a conventional packaging method in which individually-packaged elements are arrayed on a printed board, in the above-mentioned MCM, the wiring distance is shorter and parasitic inductances and resistances are significantly reduced, thereby enabling a low-loss circuit.

Although, in an MCM, encapsulating a plurality of semiconductor chips in one package reduces the package area, there is a problem in that the heat dissipation capability is reduced.

Furthermore, as shown in a comparative example in FIG. 16 which the inventor of the present invention has been studying, in an MCM, wires are used for major current paths between the chips and frame to enable electrical connections. Therefore, wires make up a significant portion of all the parasitic components. As a result, there is a problem in that parasitic components such as parasitic resistances and inductances in those wires increase.

An objective of the present invention is to provide a semiconductor device which is capable of improving the electrical characteristics.

Furthermore, another objective of the present invention is to provide a semiconductor device which is capable of improving the capability of dissipating heat.

The above-mentioned and other objectives, and novel features will become more apparent as the description in this specification proceeds with reference to the accompanying drawings.

Major embodiments of the present invention disclosed in this application are briefly described as shown below:

That is, a semiconductor device according to the present invention comprises

a plurality of semiconductor chips, each of which has a terminal on its principal surface,

a plate-like conductive member which has electrical connections to at least two semiconductor chips' terminals among the plurality of semiconductor chips,

a sealed body which encapsulates the plurality of semiconductor chips, and

a plurality of external connection terminals which have individual electrical connections to the plurality of semiconductor chips, wherein

the at least two semiconductor chips which are connected by the plate-like conductive member have an individual transistor circuit, and the plate-like conductive member is exposed outside the sealed body.

Furthermore, a semiconductor device according to the present invention comprises

a plurality of semiconductor chips, each of which has a terminal on its principal surface,

a plate-like conductive member which has electrical connections to at least two semiconductor chips' terminals among the plurality of semiconductor chips,

a sealed body which encapsulates the plurality of semiconductor chips by resin, and

a plurality of external connection terminals which have individual electrical connections to the plurality of semiconductor chips, wherein

the plate-like conductive member is exposed outside the sealed body, and

the connecting portion of the plate-like conductive member at which the plate-like conductive member is connected to one semiconductor chip is joined to the connecting portion at which the plate-like conductive member is connected to the other semiconductor chip, on either the principal or rear surface of the sealed body, or on the outside of the semiconductor chips inside the sealed body.

Furthermore, a semiconductor device according to the present invention comprises

a plurality of semiconductor chips, each of which has a terminal on its principal surface,

a plate-like conductive member which has electrical connections to at least two semiconductor chips' terminals among the plurality of semiconductor chips,

a sealed body which encapsulates the plurality of semiconductor chips by resin, and

a plurality of external connection terminals which have individual electrical connections to the plurality of semiconductor chips and are disposed on the peripheral edge of the rear surface of the sealed body, wherein

the plate-like conductive member is exposed on the at least either principal or rear surface of the sealed body.

Furthermore, in a semiconductor device according to the present invention, a plurality of semiconductor chips are encapsulated, wherein

major current paths between elements or between terminals and elements have electrical connections made possible by a plate-like conductor, and

at least three conductors having different potentials are partially exposed on either the upper or rear surface of the semiconductor device, or on both surfaces.

Furthermore, in a semiconductor device according to the present invention,

a plurality of semiconductor chips are connected in series by a plate-like conductor, and a plurality of semiconductor chips are connected to the same surface of the conductor, wherein

among a plurality of semiconductor chips consisting of the semiconductor device,

one or more semiconductor chips are disposed upside down and encapsulated.

For an example, in an MCM for a DC/DC converter,

the control power MOSFET chip's drain terminal has an electrical connection to the input terminal, which is an external connection terminal, via a plate-like conductor, or is directly connected to a plate-like conductor which is a part of the input terminal, and similarly,

the synchronous power MOSFET chip's source terminal has an electrical connection to the ground terminal, which is an external connection terminal, via a plate-like conductor, or is directly connected to a plate-like conductor which is a part of the ground terminal.

Furthermore, the control power MOSFET chip's source terminal and the synchronous power MOSFET chip's drain terminal are individually connected to plate-like conductors, and the plate-like conductors are connected to each other by a certain conductor, or the control power MOSFET chip's source terminal and the synchronous power MOSFET chip's drain terminal are connected to a part of a common conductor.

Furthermore, the conductor has an electrical connection to the output terminal which is an external connection terminal, or is a part of the output terminal.

Furthermore, a plate-like conductor which is connected to the input terminal, ground terminal and output terminal or is a part of the terminals is partially or entirely exposed outside the insulating material which encapsulates the semiconductor device.

Furthermore, a common plate-like conductor is used to connect the control power MOSFET chip's source terminal and the synchronous power MOSFET chip's drain terminal, and the synchronous power MOSFET is connected upside down to the common surface of the conductor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view, seen through a sealed body, showing an example of the structure of a semiconductor device (multiple chip module for a non-insulated DC/DC converter) according to embodiment 1 of the present invention;

FIG. 2 is a cross-sectional view showing the cross-sectional structure taken substantially along the lines A—A in FIG. 1;

FIG. 3 is a drawing of the rear surface showing the structure of the semiconductor device shown in FIG. 1;

FIG. 4 is an outside perspective view showing the structure of the semiconductor device shown in FIG. 1;

FIG. 5 is a cross-sectional view showing the structure of a semiconductor device which is an altered example according to embodiment 1 of the present invention;

FIG. 6 is a cross-sectional view showing the structure of a semiconductor device which is an altered example according to embodiment 1 of the present invention;

FIG. 7 is a cross-sectional view showing the structure of a semiconductor device which is an altered example according to embodiment 1 of the present invention;

FIG. 8 is a circuit diagram showing an example of an equivalent circuit when the MCM 1 shown in FIG. 1 is mounted on the semiconductor device (non-insulated DC/DC converter);

FIG. 9 is a plan view, seen through a sealed body, showing an example of the structure of a semiconductor device (multiple chip module for a non-insulated DC/DC converter) according to embodiment 2 of the present invention;

FIG. 10 is a cross-sectional view showing the cross-sectional structure taken substantially along the lines B—B in FIG. 9;

FIG. 11. is a drawing of the rear surface showing the structure of the semiconductor device shown in FIG. 9.

FIG. 12 is an outside perspective view showing the structure of the semiconductor device shown in FIG. 9;

FIG. 13 is a cross-sectional view showing an example of the structure of a semiconductor device (multiple chip module for a non-insulated DC/DC converter) according to embodiment 3 of the present invention;

FIG. 14 is a cross-sectional view showing the structure of a semiconductor device which is an altered example according to embodiment 3 of the present invention;

FIG. 15 is a plan view, seen through a sealed body, showing an example of the structure of a semiconductor device (multiple chip module for a non-insulated DC/DC converter) according to embodiment 4 of the present invention;

FIG. 16 is a plan view, seen through a sealed body, showing the structure of a power-supply multiple chip module which is a comparative example; and

FIG. 17 is a perspective view, seen through a sealed body, showing the inside of the semiconductor device shown in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following embodiments, the same or similar parts will not be repeatedly described unless specifically necessary.

Furthermore, as a matter of convenience, in the following embodiments, a plurality of separate sections or embodiments will be explained when necessary. However, those separate sections or embodiments are all related unless otherwise specified, and one section may be a part of or the whole of an altered example, or a description may be a detailed or supplementary explanation.

Moreover, in the following embodiments, when the number of elements (including the number of items, numeric value, quantity, and range) is mentioned, the number of elements is not limited to a specific number and could be more or less unless otherwise specified, or unless the number of elements is obviously limited to a specific number in principle.

Hereafter, embodiments of the present invention will be explained in detail with reference to the drawings. In all of the drawings used for explaining the embodiments, members that have the same function have been assigned the same numbers to avoid repeated explanations.

(Embodiment 1)

FIG. 1 is a plan view, seen through a sealed body, showing an example of the structure of a semiconductor device (multiple chip module for a non-insulated DC/DC converter) according to embodiment 1 of the present invention. FIG. 17 is a perspective view, seen through a sealed body, showing the inside of the semiconductor device shown in FIG. 1. FIG. 2 is a cross-sectional view showing the cross-sectional structure taken substantially along the lines A—A in FIG. 1. FIG. 3 is a drawing of the rear surface showing the structure of the semiconductor device shown in FIG. 1. FIG. 4 is an outside perspective view showing the structure of the semiconductor device shown in FIG. 1. FIGS. 5 through 7 are cross-sectional views showing the structure of a semiconductor device which is an altered example according to embodiment 1 of the present invention. FIG. 8 is a circuit diagram showing an example of an equivalent circuit when the MCM 1 shown in FIG. 1 is mounted on the semiconductor device (non-insulated DC/DC converter). FIG. 16 is a plan view, seen through a sealed body, showing the structure of a power-supply multiple chip module which is a comparative example.

In a semiconductor device according to embodiment 1, shown in FIGS. 1 through 4 and 17, a plurality of semiconductor chips are encapsulated in one sealed body (insulating resin for sealing) 17. In embodiment 1, an MCM (multiple chip module) 1 for a non-insulated DC/DC converter is explained as one example of the above-mentioned semiconductor device.

Furthermore, as shown in FIG. 3, an MCM 1 has a non-leaded QFN (Quad Flat Non-leaded Package) structure in which a plurality of external connection terminals 11 are disposed on the peripheral edge of the rear surface 17 b of the sealed body 17.

The MCM 1 according to embodiment 1 basically consists of a plurality of semiconductor chips, a plate-like conductive member which has electrical connections to at least two semiconductor chips' terminals among those semiconductor chips, a sealed body 17 which encapsulates the plural semiconductor chips, and a plurality of external connection terminals 11 disposed on the peripheral edge of the rear surface 17 b of the sealed body 17. Furthermore, in the MCM 1, at least two semiconductor chips connected by the plate-like conductive member have an individual transistor circuit, and the plate-like conductive member is exposed outside the sealed body 17.

Moreover, the MCM 1 has a control power MOSFET chip 2 (first semiconductor chip), a synchronous power MOSFET chip 3 (second semiconductor chip) which has an electrical connection in series to the control power MOSFET chip 2 by a plate-like conductive member, and a driver IC chip 4 (third semiconductor chip) which turns on and off those semiconductor chips. The three semiconductor chips are sealed (encapsulated) in the sealed body 17.

That is, the MCM 1 has two semiconductor chips (first and second semiconductor chips) each of which has a power-supply transistor circuit, and one semiconductor chip (third semiconductor chip) which has a driver circuit for controlling the two semiconductor chips.

The detailed structure of the MCM 1 according to embodiment 1 will be explained. As shown in FIGS. 1 and 2, a control power MOSFET chip (first transistor) 2 is disposed on the input-side plate-like lead (first plate-like conductive member) 5. That is, a terminal which functions as a drain terminal DT1 (first output electrode) of the control power MOSFET is formed on the rear surface 2 b of the control power MOSFET chip 2, and the input-side plate-like lead 5 which is a first plate-like conductive member is connected to the drain terminal DT1.

On the principal surface 2 a of the control power MOSFET chip 2, terminals which function as the control power MOSFET chip's source terminal (second output electrode) ST1 and gate terminal (input electrode) GT1 are formed, and the source terminal ST1 located on the principal surface 2 a of the control power MOSFET chip 2 is connected to the plate-like lead for source 12 which is a second plate-like conductive member.

Furthermore, a synchronous power MOSFET chip (second transistor) 3 is disposed on the output-side plate-like lead 6. That is, a terminal which functions as a drain terminal (first output terminal) DT2 of the synchronous power MOSFET is formed on the rear surface 3 b of the synchronous power MOSFET chip 3, and the output-side plate-like lead 6 which is a third plate-like conductive member is connected to the drain terminal DT2. On the principal surface 3 a of the synchronous power MOSFET chip 3, terminals which function as the synchronous power MOSFET chip's source terminal ST2 and gate terminal (input electrode) GT2 are formed, and the source terminal ST2 located on the principal surface 3 a of the synchronous power MOSFET chip 3 is connected to the plate-like lead for source 13 which is a fourth plate-like conductive member.

Furthermore, the MCM 1 has a ground-side plate-like lead 7 and a driver-side plate-like lead 8, and a driver IC chip 4 is disposed on the driver-side plate-like lead 8. That is, the driver IC chip 4 and the driver-side plate-like lead 8 are connected to each other. On the driver IC chip 4, some terminals 9 among a plurality of terminals 9 located on the principal surface 4 a of the driver IC chip 4 are electrically connected to the power MOSFET chips' gate terminal GT1, source terminal ST1, gate terminal GT2 and source terminal ST2 by wires 10, such as gold wires or thin metal wires, thereby the power MOSFETS are turned on and off.

Other terminals 9 located on the principal surface 4 a of the driver IC chip 4 are a power supply voltage terminal, boot terminal, voltage check terminal and a control signal input terminal, and each of the terminals is connected to a corresponding external connection terminal 11 by a wire 10.

As shown in FIG. 3, the input-side plate-like lead 5, output-side plate-like lead 6, and driver-side plate-like lead 8, each of which has an installed semiconductor chip, are partially or entirely exposed on the rear surface 17 b of the sealed body 17 of the MCM 1. Those leads function as external connection terminals that have electrical connections to the printed wiring board as well as function as heat radiating parts that dissipates heat on the printed wiring board.

As FIGS. 1 and 2 show, the plate-like lead for source 12 provides an electrical connection between the source terminal ST1 of the control power MOSFET chip 2 and the output-side plate-like lead 6. Similarly, the plate-like lead for source 13 provides an electrical connection between the source terminal ST2 of the synchronous power MOSFET chip 3 and the ground-side plate-like lead 7.

Moreover, as FIG. 4 shows, the plate-like lead for source 12 and the plate-like lead for source 13 are partially exposed on the upper surface 17 a of the sealed body 17 of the MCM 1.

Furthermore, as FIG. 2 shows, drain terminals DT1 and DT2 located on the rear surfaces 2 b and 3 b of the control power MOSFET chip 2 and the synchronous power MOSFET chip 3 are joined to the input-side plate-like lead 5 and the output-side plate-like lead 6, respectively, with die bonding material, such as silver paste 14, interposed.

On the other hand, source terminals ST1 and ST2 located on the principal surfaces 2 a and 3 a of the control power MOSFET chip 2 and the synchronous power MOSFET chip 3 are joined to the plate-like leads for source 12 and 13, respectively, via a plurality of protruding conductive electrodes such as gold bumps 15.

It is possible to use protruding solder electrodes or paste-like conductive adhesives to join the source terminals ST1 and ST2 located on the principal surfaces 2 a and 3 a of the control power MOSFET chip 2 and the synchronous power MOSFET chip 3, respectively, to the plate-like leads for source 12 and 13.

FIGS. 2, 5, 6 and 7 show various types of connections between the second plate-like conductive member and the third plate-like conductive member, and between the fourth plate-like conductive member and the ground-side plate-like lead 7.

As shown in FIG. 2, the plate-like lead for source 12 has an electrical connection to the output-side plate-like lead 6 via a conductor 16, and the plate-like lead for source 13 has an electrical connection to the ground-side plate-like lead 7 via a conductor 16. Furthermore, as shown in an altered example in FIG. 5, it is possible to create the portions between the plate-like leads for source 12 a and 13 a and the connections to the output-side plate-like lead 6 and the ground-side plate-like lead 7, respectively, so that those portions become the same conductive members as the leads and then provide electrical connections by using solder 18. A conductive member (second conductive member or third conductive member) which consists of a plate-like lead for source 12, conductor 16, and an output-side plate-like lead 6 has two bends which forms a nearly S-shape.

Furthermore, as shown in altered examples in FIGS. 6 and 7, it is possible to integrate the plate-like lead for source (second plate-like conductive member) 12 and the output-side plate-like lead (third plate-like conductive member) 6, and also integrate the plate-like lead for source 13 and the ground-side plate-like lead 7. In an altered example shown in FIG. 6, leads are integrated by press work. In an altered example shown in FIG. 7, leads are integrated by bending work.

Thus, in the MCM 1 according to embodiment 1, the plate-like lead for source 12 located on the upper-surface 17 a side of the sealed body 17 is joined and electrically connected to the output-side plate-like lead 6 located on the rear surface 17 b side of the sealed body 17, on the outside of the control power MOSFET chip 2 and the synchronous power MOSFET chip 3, inside the sealed body 17.

Next, FIG. 8 shows an example of an equivalent circuit when the MCM 1 is mounted. The MCM 1 is connected by a coil 20, capacitors 22 and 23, load 24 and an input power source 21 by wires. In a non-insulated DC/DC converter circuit 19, heat is mostly generated by the control power MOSFET chip 2 and the synchronous power MOSFET chip 3.

According to an MCM 1 of embodiment 1, one surface of the plate-like conductive member which functions as a current path is connected to a semiconductor chip and the other surface is exposed outside the sealed body 17, thereby making it possible to increase the capability of dissipating heat. The plate-like conductive member exposed on the rear surface 17 b of the sealed body 17 functions as an external connection terminal and is also capable of dissipating heat on the printed wiring board where the MCM 1 is mounted. Furthermore, the plate-like conductive member exposed on the upper surface 17 a of the sealed body 17 directly dissipates heat in the ambient air or increases the heat conductivity to a heat radiating member, such as a heat radiating fin 27 (see FIGS. 13 and 14) or heat sink, mounted on the MCM 1.

That is, heat generated by the control power MOSFET chip 2 and the synchronous power MOSFET chip 3 is conveyed from the input-side plate-like lead 5 and the output-side plate-like lead 6, which are exposed on the rear surface 17 b of the sealed body 17, to the printed wiring board, thereby dissipating the heat. Furthermore, heat can be externally dissipated from the plate-like lead for source 12 and the plate-like lead for source 13 which are exposed on the upper surface 17 a of the sealed body 17, thereby increasing the heat dissipation capability.

As a result, it is possible to increase the heat dissipation capability in the MCM 1. It is also possible to increase the voltage conversion efficiency of the MCM 1.

Furthermore, in an MCM 1 according to embodiment 1, the source terminal ST1 of the control power MOSFET chip 2 is connected to the output-side plate-like lead 6 by the plate-like leads for source 12, and the source terminal ST2 of the synchronous power MOSFET chip 3 is connected to the ground-side plate-like lead 7 by the plate-like leads for source 13. Therefore, when compared to a multiple chip module in a comparative example, shown in FIG. 16, which uses ordinary wire connections using wires 25 such as gold wires, the cross-sectional area of the current path can be made larger in the MCM 1 according to embodiment 1. As a result, parasitic components, such as parasitic resistances and inductances, are reduced, which makes it possible to increase the conversion efficiency.

That is, it is possible to reduce parasitic resistances and parasitic inductances compared to the situations where wire connections are used, thereby making it possible to increase the electrical characteristics of the MCM 1.

Furthermore, it is possible to easily manufacture a reliable semiconductor device by connecting in series the current path between the first transistor's first output electrode and second output electrode to the current path between the second transistor's first output electrode and second output electrode, and mechanically integrating the first, second and third conductive members, and first and second transistors.

(Embodiment 2)

FIG. 9 is a plan view, seen through a sealed body, showing an example of the structure of a semiconductor device (multiple chip module for a non-insulated DC/DC converter) according to embodiment 2 of the present invention. FIG. 10 is a cross-sectional view showing the cross-sectional structure taken substantially along the lines B—B in FIG. 9. FIG. 11 is a drawing of the rear surface showing the structure of the semiconductor device shown in FIG. 9. FIG. 12 is an outside perspective view showing the structure of the semiconductor device shown in FIG. 9.

Similar to embodiment 1, a semiconductor device according to embodiment 2 is an MCM (multiple chip module) 1 for a non-insulated DC/DC converter. The semiconductor device is a semiconductor package in which a control power MOSFET chip 2, synchronous power MOSFET chip 3 and a driver IC chip 4 which turns on and off those power MOSFET chips are encapsulated.

The structure of the MCM 1 according to embodiment 2 will be described. As FIGS. 9 and 10 show, a control power MOSFET chip 2 is disposed on an input-side plate-like lead 5. And, terminals which function as the control power MOSFET chip's source terminal ST1 and gate terminal GT1 are formed on the principal surface 2 a of the control power MOSFET chip 2. Furthermore, a terminal which functions as the control power MOSFET chip's drain terminal DT1 is formed on the rear surface 2 b of the control power MOSFET chip 2.

On the other hand, what is different from embodiment 1 is that a synchronous power MOSFET chip 3 is disposed on the ground-side plate-like lead 7. That is, as shown in FIG. 10, the synchronous power MOSFET chip 3, which is a second semiconductor chip, is disposed reversely (principal and rear surfaces upside down) compared to the control power MOSFET chip 2 which is a first semiconductor chip. Moreover, a terminal which functions as the synchronous power MOSFET chip's drain terminal DT2 is formed on the principal surface 3 a of the synchronous power MOSFET chip 3, and terminals which function as the synchronous power MOSFET chip's source terminal ST2 and gate terminal GT2 are formed on the rear surface 3 b of the synchronous power MOSFET chip 3.

As FIG. 9 shows, the MCM 1 for a DC/DC converter has an output-side plate-like lead 6.

Furthermore, a driver IC chip 4 is disposed on the driver-side plate-like lead 8. Some of the terminals 9 located on the principal surface 4 a of the driver IC chip 4 have electrical connections to the control power MOSFET chip's 2 gate terminal GT1 and source terminal ST1, and the synchronous power MOSFET chip's 3 source terminal ST2 and gate terminal GT2, thereby turning on and off each power MOSFET. Moreover, because the gate terminal GT2 is downwardly formed on the principal surface 3 a, as shown in FIG. 9, some of the terminals 9 of the driver IC chip 4 are connected to the synchronous power MOSFET chip's 3 gate terminal GT2 by wires 10 with a metal plate 26 interposed. The gate terminal GT2 has an electrical connection to a metal plate 26 via bump electrodes, for example. Other terminals are a power supply voltage terminal, boot terminal, voltage check terminal, and a control signal input terminal. Each of the terminals is connected to a corresponding external connection terminal 11 by a wire 10.

As shown in FIG. 11, the input-side plate-like lead 5, output-side plate-like lead 6, ground-side plate-like lead 7 and driver-side plate-like lead 8 are partially or entirely exposed on the rear surface 17 b of the sealed body 17. Thus, those plate-like leads function as external connection terminals which have electrical connections to the printed wiring board as well as function as heat radiating parts which dissipate heat on the printed wiring board.

However, it is not necessary to expose all of the plate-like leads. For example, it is possible that only the output-side plate-like lead 6 is hidden.

Furthermore, the plate-like lead for source 12 provides electrical connections between the source terminal ST1 of the control power MOSFET chip 2 and the drain terminal DT2 of the synchronous power MOSFET chip 3. As shown in FIG. 12, the plate-like lead for source 12 is partially exposed on the upper surface 17 a of the sealed body 17.

Therefore, in an MCM 1 according to embodiment 2, as shown in FIG. 9, the connecting portion of the plate-like lead for source 12 (second plate-like conductive member) at which the lead connects to the control power MOSFET chip 2 (one semiconductor chip) is joined to the connecting portion at which the lead connects to the synchronous power MOSFET chip 3 (the other semiconductor chip) on the upper surface 17 a of the sealed body 17.

Moreover, the surface of the control power MOSFET chip 2 on which the drain terminal DT1 is formed is pressure-bonded to the input-side plate-like lead 5, for example, via a die bonding material such as silver paste 14, and the source terminal ST1 located on the opposite surface is connected to the plate-like lead for source 12, for example, via a conductive material such as a gold bump 15.

On the other hand, the surface of the synchronous power MOSFET chip 3 on which the drain terminal DT2 is formed is pressure-bonded to the plate-like lead for source 12, for example, via a die bonding material such as silver paste 14, and the source terminal ST2 located on the opposite surface is connected to the ground-side plate-like lead 7, for example, via a conductive material such as a gold bump 15.

In an MCM 1 according to embodiment 2, by installing at least one semiconductor chip upside down, it is possible to make manufacturing of the plate-like lead for source 12 much easier than that of an MCM 1 according to embodiment 1. That is, as shown in FIG. 10, it is possible to connect the source terminal ST1 of the control power MOSFET chip 2 and the drain terminal DT2 of the synchronous power MOSFET chip 3 onto the same surface of the plate-like lead for source 12 by using only one plate-like lead for source 12. Therefore, it is possible to avoid the complicated manufacturing process in which a plurality of semiconductor chips are connected on the different surfaces of the plate-like lead for source 12. As a result, it is possible to reduce the time to connect and manufacture leads. Thus, the structure of the MCM 1 can be simplified.

Furthermore, because the plate-like lead for source 12 can be formed by using only one plate-like lead, it is possible to make the area of the plate-like lead for source 12 larger than that of the MCM 1 according to embodiment 1. As a consequence, the heat dissipation capability can be increased and the voltage conversion efficiency can also be increased.

(Embodiment 3)

FIG. 13 is a cross-sectional view showing an example of the structure of a semiconductor device (multiple chip module for a non-insulated DC/DC converter) according to embodiment 3 of the present invention. FIG. 14 is a cross-sectional view showing the structure of a semiconductor device which is an altered example according to embodiment 3 of the present invention.

Similar to embodiments 1 and 2, a semiconductor device according to embodiment 3 is an MCM (multiple chip module) 1 for a non-insulated DC/DC converter. The structure which will increase the heat dissipation capability will be explained.

An MCM 1 shown in FIG. 13 is an MCM 1 in which a heat radiating fin 27 (heat radiating member) is mounted to the MCM 1 according to embodiment 1. That is, in an MCM 1 according to embodiment 1, two plate-like leads (plate-like leads for source 12 and 13) exposed on the upper surface 17 a of the sealed body 17 have different potentials, and therefore, a heat radiating member such as a heat radiating fin 27 is installed with an insulating sheet 28 interposed.

Thus, by mounting a heat radiating fin 27 to the plate-like lead exposed on the upper surface 17 a of the MCM 1, it is possible to increase the heat dissipation capability of the MCM 1.

Furthermore, an MCM 1 shown in FIG. 14 is an MCM 1 in which a heat radiating fin 27 (heat radiating member) is mounted to the MCM 1 according to embodiment 2. In this MCM 1, only one plate-like lead for source 12 is exposed on the upper surface 17 a of the sealed body 17. Therefore, the plate-like lead for source 12 can be directly connected to the heat radiating fin 27 without an insulating sheet 28 interposed. Consequently, it is possible to make the heat dissipation capability higher than that of the MCM 1 shown in FIG. 13.

Furthermore, it is also possible to integrate the plate-like lead for source 12 and the heat radiating fin 27, thereby making it possible to increase the heat dissipation capability.

(Embodiment 4)

FIG. 15 is a plan view, seen through a sealed body, showing an example of the structure of a semiconductor device (multiple chip module for a non-insulated DC/DC converter) according to embodiment 4 of the present invention.

Similar to embodiments 1 and 2, a semiconductor device according to embodiment 4 is an MCM (multiple chip module) 1 for a non-insulated DC/DC converter. In an MCM 1 according to embodiments 1 and 2, wires 10 are used to connect the control power MOSFET chip's 2 source terminal ST1 and gate terminal GT1 to the driver IC chip's 4 terminals 9, or to connect the synchronous power MOSFET chip's 3 source terminal ST2 and gate terminal GT2 to the driver IC chip's 4 terminals 9. However, in an MCM 1 according to embodiment 4, metal plates (other plate-like conductive members) 29 are used for the connections of the gate drive circuits, or other connections.

That is, in an example shown in FIG. 15, the terminal of the control power MOSFET chip 2 has an electrical connection to a corresponding terminal 9 of the driver IC chip 4 by a metal plate 29, and the terminal of the synchronous power MOSFET chip 3 also has an electrical connection to a corresponding terminal 9 of the driver IC chip 4 by a metal plate 29. Furthermore, electrical connections between the terminals and metal plates 29 are provided, for example, by using gold bumps 15.

In the MCM 1, when the high-speed switching is selected, parasitic resistances and parasitic inductances, including a gate drive circuit, other than the main current path may cause the efficiency to decrease. Therefore, by connecting the driver IC chip 4 to the electrodes of the control power MOSFET chip 2 and synchronous power MOSFET chip 3 by using metal plates 29, it is possible to reduce the parasitic resistances and parasitic inductances compared to the situations where wire connections are used.

Moreover, other connections that use wires 10 as shown in FIG. 15 can be replaced with metal plates 29.

As stated above, the present invention provided by the inventor has been explained in detail according to the embodiments. However, the present invention is not intended to be limited to the above-mentioned embodiments, and can be embodied in a variety of forms as long as they do not depart from the concept of the present invention.

For example, in the above embodiments 1 through 4, the MCM 1 which is a QFN-type semiconductor device is explained. However, the MCM 1 is not intended to be limited to the QFN-type semiconductor device, and can be a semiconductor device of other structures such as a QFP (Quad Flat Package) type semiconductor device as long as a plurality of semiconductor chips are encapsulated in a sealed body. Furthermore, the number of encapsulated semiconductor chips is not intended to be limited to three, therefore, there can be four or more semiconductor chips.

The present invention is suitable for use in a semiconductor device or electronic device.

A major embodiment of the present invention disclosed in this application is briefly described as shown below:

Because the present invention has a plate-like conductive member to connect terminals of two semiconductor chips, it is possible to reduce parasitic resistances and parasitic inductances compared to the situations where wire connections are used, thereby increasing the electrical characteristics of the semiconductor device. Furthermore, the above-mentioned plate-like conductive member is exposed outside the sealed body, thereby making it possible to increase the heat dissipation capability of the semiconductor device.

Claims (24)

1. A semiconductor device comprising a first transistor and a second transistor, each of which has an input electrode, first output electrode and second output electrode, wherein
the current path connecting between said first output electrode and said second output electrode of said first transistor are connected in series to the current path connecting between said first output electrode and said second output electrode of said second transistor;
either said first output electrode or said second output electrode of said first transistor is connected to a first conductive member; and
the other output electrode of said first transistor is connected to a second conductive member;
either said first output electrode or said second output electrode of said second transistor is connected to said second conductive member;
the other output electrode of said second transistor is connected to a third conductive member;
said first conductive member, said second conductive member and said third conductive member are electrically isolated from one another; and
said first conductive member, said second conductive member, said third conductive member, said first transistor and said second transistor are mechanically integrated.
2. A semiconductor device according to claim 1, wherein said second conductive member has two or more bends.
3. A semiconductor device according to claim 1, wherein said second conductive member is a nearly S-shape.
4. A semiconductor device according to claim 1, wherein in said second conductive member, the surface to which an output electrode of said first transistor is connected is located on the same side of the surface to which an output electrode of said second transistor is connected.
5. A semiconductor device comprising
a plurality of semiconductor chips, each of which has a terminal on its principal surface,
a conductive plate which has electrical connections to at least two semiconductor chips' terminals among said plurality of semiconductor chips,
a sealed body which encapsulates said plurality of semiconductor chips, and
a plurality of external connection terminals which have individual electrical connections to the plurality of semiconductor chips, wherein
at least two semiconductor chips which are connected by the conductive plate have an individual transistor circuit, and the conductive plate is exposed outside said sealed body.
6. A semiconductor device according to claim 5, wherein among said plurality of semiconductor chips, each of a first semiconductor chip and a second semiconductor chip has a power-supply transistor circuit; and
said semiconductor device further comprising
a first conductive plate which connects to a drain terminal of said first semiconductor chip,
a second conductive plate which connects to a source terminal of said first semiconductor chip,
a third conductive plate which connects to a drain terminal of said second semiconductor chip, and
a fourth conductive plate which connects to a source terminal of said second semiconductor chip, wherein
said second conductive plate has an electrical connection to said third conductive plate, and said second and third conductive plates are at least partially exposed outside said sealed body.
7. A semiconductor device according to claim 6, wherein said second conductive plate and said third conductor plate are integrated.
8. A semiconductor device according to claim 5, wherein
among said plurality of semiconductor chips,
each of a first semiconductor chip and a second semiconductor chip has a power-supply transistor circuit, and a third semiconductor chip has a driver circuit which controls said first and second semiconductor chips.
9. A semiconductor device according to claim 6, wherein said second and fourth conductive plates are partially exposed on either the principal or rear surface of said sealed body, and said first and third conductive plates are partially exposed on the other surface of said sealed body.
10. A semiconductor device according to claim 9, wherein said second conductive plate and said third conductor plate are integrated.
11. A semiconductor device according to claim 5, wherein among said plurality of semiconductor chips,
at least one semiconductor chip is installed upside down in relation to the other semiconductor chips.
12. A semiconductor device according to claim 6, wherein said second semiconductor chip is installed upside down in relation to said first semiconductor chip,
said second and third conductive plates are partially exposed on either the principal or rear surface of said sealed body; and
said first and fourth conductive plates are partially exposed on the other surface of said sealed body.
13. A semiconductor device according to claim 12, wherein said second conductive plate and said third conductive plate are integrated.
14. A semiconductor device according to claim 5, wherein a heat radiating member is installed in the exposed area of said conductive plate exposed outside said sealed body.
15. A semiconductor device comprising
a plurality of semiconductor chips, each of which has a terminal on its principal surface,
a conductive plate which has electrical connections to at least two semiconductor chips' terminals among said plurality of semiconductor chips,
a sealed body which encapsulates said plurality of semiconductor chips by resin,
a plurality of external connection terminals which have individual electrical connections to the plurality of semiconductor chips, wherein
said conductive plate is exposed outside said sealed body, and
the connecting portion of said conductive plate at which said conductive plate is connected to one semiconductor chip is joined to the connecting portion at which said conductive plate is connected to the other semiconductor chip, on either the principal or rear surface of said sealed body, or on the outside of said semiconductor chips inside said sealed body.
16. A semiconductor device according to claim 15, wherein among said plurality of semiconductor chips,
each of a first semiconductor chip and a second semiconductor chip has a power-supply transistor circuit, and a third semiconductor chip has a driver circuit which controls said first and second semiconductor chips.
17. A semiconductor device according to claim 15, wherein a heat radiating member is installed in the exposed area of said conductive plate exposed outside said sealed body.
18. A semiconductor device according to claim 15, wherein said conductive plate has an electrical connection to the semiconductor chip via a plurality of gold bumps.
19. A semiconductor device according to claim 16, wherein the terminal of said first semiconductor chip has an electrical connection to the terminal of said third semiconductor chip by said conductive plate, and the terminal of said second semiconductor chip has an electrical connection to the terminal of said third semiconductor chip by another conductive plate.
20. A semiconductor device comprising
a plurality of semiconductor chips, each of which has a terminal on its principal surface,
a conductive plate which has electrical connections to at least two semiconductor chips' terminals among said plurality of semiconductor chips,
a sealed body which encapsulates said plurality of semiconductor chips by resin,
a plurality of external connection terminals which have individual electrical connections to said plurality of semiconductor chips and are disposed on the peripheral edge of the rear surface of said sealed body, wherein
said conductive plate is exposed on the at least either principal or rear surface of said sealed body.
21. A semiconductor device according to claim 20, wherein among said plurality of semiconductor chips,
each of a first semiconductor chip and a second semiconductor chip has a power-supply transistor circuit, and
a third semiconductor chip has a driver circuit which controls said first and second semiconductor chips.
22. A semiconductor device according to claim 20, wherein a heat radiating member is installed in the exposed area of said conductive plate exposed outside said sealed body.
23. A semiconductor device according to claim 20, wherein
said conductive plate has an electrical connection to the semiconductor chip via a plurality of gold bumps.
24. A semiconductor device according to claim 20, wherein
among said plurality of semiconductor chips,
each of a first semiconductor chip and a second semiconductor chip has a power-supply transistor circuit, and
said second semiconductor chip is installed upside down compared to said first semiconductor chip; and
said semiconductor device further comprising
a first conductive plate which connects to a drain terminal of said first semiconductor chip,
a second conductive plate which connects to a source terminal of said first semiconductor chip,
a third conductive plate which connects to a drain terminal of said second semiconductor chip, and
a fourth conductive plate which connects to a source terminal of said second semiconductor chip, wherein
said second and third conductive plates are partially exposed on either the principal or rear surface of said sealed body, and said first and fourth conductive plates are partially exposed on the other surface of said sealed body.
US11041200 2004-01-28 2005-01-25 Semiconductor device Active US7145224B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004020474A JP2005217072A (en) 2004-01-28 2004-01-28 Semiconductor device
JP2004-020474 2004-01-28

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12130782 USRE41869E1 (en) 2004-01-28 2008-05-30 Semiconductor device
US12821999 USRE43663E1 (en) 2004-01-28 2010-06-23 Semiconductor device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12130782 Reissue USRE41869E1 (en) 2004-01-28 2008-05-30 Semiconductor device
US12821999 Reissue USRE43663E1 (en) 2004-01-28 2010-06-23 Semiconductor device

Publications (2)

Publication Number Publication Date
US20050161785A1 true US20050161785A1 (en) 2005-07-28
US7145224B2 true US7145224B2 (en) 2006-12-05

Family

ID=34792612

Family Applications (3)

Application Number Title Priority Date Filing Date
US11041200 Active US7145224B2 (en) 2004-01-28 2005-01-25 Semiconductor device
US12130782 Active USRE41869E1 (en) 2004-01-28 2008-05-30 Semiconductor device
US12821999 Active USRE43663E1 (en) 2004-01-28 2010-06-23 Semiconductor device

Family Applications After (2)

Application Number Title Priority Date Filing Date
US12130782 Active USRE41869E1 (en) 2004-01-28 2008-05-30 Semiconductor device
US12821999 Active USRE43663E1 (en) 2004-01-28 2010-06-23 Semiconductor device

Country Status (4)

Country Link
US (3) US7145224B2 (en)
JP (1) JP2005217072A (en)
KR (5) KR101100838B1 (en)
CN (2) CN100521196C (en)

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060022298A1 (en) * 2004-07-30 2006-02-02 Masaki Shiraishi Semiconductor device and a manufacturing method of the same
US20070187807A1 (en) * 2006-02-13 2007-08-16 Jeongil Lee Multi-chip module for battery power control
US20070216011A1 (en) * 2006-03-17 2007-09-20 Ralf Otremba Multichip module with improved system carrier
US20080251912A1 (en) * 2007-04-10 2008-10-16 Ralf Otremba Multi-Chip Module
US20090001532A1 (en) * 2006-01-10 2009-01-01 Sanken Electric Co., Ltd. Plastic-Encapsulated Semiconductor Device with an Exposed Radiator at the Top and Manufacture Thereof
US20090085181A1 (en) * 2007-09-28 2009-04-02 Advincula Jr Abelardo Hadap Integrated circuit package system with multiple die
US20090166850A1 (en) * 2008-01-02 2009-07-02 Oseob Jeon High-Power Semiconductor Die Packages With Integrated Heat-Sink Capability and Methods of Manufacturing the Same
US20100270992A1 (en) * 2009-04-28 2010-10-28 Renesas Electronics Corporation Semiconductor device
US20110012255A1 (en) * 2009-07-16 2011-01-20 Shinko Electric Industries Co., Ltd. Semiconductor device
US20110169102A1 (en) * 2006-03-28 2011-07-14 Renesas Electronics Corporation Semiconductor device including a dc-dc converter having a metal plate
US20110278655A1 (en) * 2006-05-30 2011-11-17 Renesas Electronics Corporation Semiconductor Device with Circuit for Reduced Parasitic Inductance
DE102010030838A1 (en) * 2010-07-02 2012-01-05 Robert Bosch Gmbh A semiconductor device with improved heat dissipation
US20120181706A1 (en) * 2011-01-18 2012-07-19 Jian-Hong Zeng Power semiconductor package structure and manufacturing method thereof
US20130003309A1 (en) * 2011-06-30 2013-01-03 Stmicroelectronics S.R.L. Half-bridge electronic device with common auxiliary heat sink
US20130003305A1 (en) * 2011-06-30 2013-01-03 Stmicroelectronics S.R.L. Half-bridge electronic device with common heat sink on mounting surface
US20140117526A1 (en) * 2012-10-31 2014-05-01 Kabushiki Kaisha Toshiba Semiconductor power converter and method of manufacturing the same
US8817475B2 (en) 2011-06-30 2014-08-26 Stmicroelectronics S.R.L. System with shared heatsink
US8837153B2 (en) 2011-06-30 2014-09-16 Stmicroelectronics S.R.L. Power electronic device having high heat dissipation and stability
US8837154B2 (en) 2011-06-30 2014-09-16 Stmicroelectronics S.R.L. System with stabilized heatsink
US8860192B2 (en) 2011-06-30 2014-10-14 Stmicroelectronics S.R.L. Power device having high switching speed
US9018744B2 (en) * 2012-09-25 2015-04-28 Infineon Technologies Ag Semiconductor device having a clip contact
US9029197B2 (en) 2012-09-26 2015-05-12 Renesas Electronics Corporation Method of manufacturing semiconductor device
US9105598B2 (en) 2011-06-30 2015-08-11 Stmicroelectronics S.R.L. Package/heatsink system for electronic device
US9202796B2 (en) 2013-01-31 2015-12-01 Samsung Electronics Co., Ltd. Semiconductor package including stacked chips and a redistribution layer (RDL) structure
US9236321B2 (en) 2012-02-15 2016-01-12 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US9275943B2 (en) 2011-06-30 2016-03-01 Stmicroelectronics S.R.L. Power device having reduced thickness
US9530724B2 (en) 2010-12-13 2016-12-27 Infineon Technologies Americas Corp. Compact power quad flat no-lead (PQFN) package
US9620954B2 (en) 2010-12-13 2017-04-11 Infineon Technologies Americas Corp. Semiconductor package having an over-temperature protection circuit utilizing multiple temperature threshold values
US9659845B2 (en) 2010-12-13 2017-05-23 Infineon Technologies Americas Corp. Power quad flat no-lead (PQFN) package in a single shunt inverter circuit
US9711437B2 (en) 2010-12-13 2017-07-18 Infineon Technologies Americas Corp. Semiconductor package having multi-phase power inverter with internal temperature sensor

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7501702B2 (en) * 2004-06-24 2009-03-10 Fairchild Semiconductor Corporation Integrated transistor module and method of fabricating same
JP2006073655A (en) * 2004-08-31 2006-03-16 Toshiba Corp Semiconductor module
JP2007116012A (en) * 2005-10-24 2007-05-10 Renesas Technology Corp Semiconductor device and power supply using same
JP4875380B2 (en) 2006-02-24 2012-02-15 ルネサスエレクトロニクス株式会社 Semiconductor device
US7768075B2 (en) * 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
US7618896B2 (en) 2006-04-24 2009-11-17 Fairchild Semiconductor Corporation Semiconductor die package including multiple dies and a common node structure
DE102006021959B4 (en) * 2006-05-10 2011-12-29 Infineon Technologies Ag Power semiconductor device and process for its preparation
DE112007001240T5 (en) * 2006-05-19 2009-04-23 Fairchild Semiconductor Corp. Integrated transistor module with double-sided cooling and processes for preparing
JP5191689B2 (en) * 2006-05-30 2013-05-08 ルネサスエレクトロニクス株式会社 Semiconductor device
JP5165214B2 (en) 2006-06-26 2013-03-21 オンセミコンダクター・トレーディング・リミテッド Semiconductor device
JP5261636B2 (en) 2006-10-27 2013-08-14 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー Semiconductor device
US20080180921A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
JP2008218688A (en) * 2007-03-05 2008-09-18 Denso Corp Semiconductor device
JP5272191B2 (en) * 2007-08-31 2013-08-28 三菱電機株式会社 The method of manufacturing a semiconductor device and a semiconductor device
US8642394B2 (en) 2008-01-28 2014-02-04 Infineon Technologies Ag Method of manufacturing electronic device on leadframe
JP2009200338A (en) * 2008-02-22 2009-09-03 Renesas Technology Corp Method for manufacturing semiconductor device
US8507320B2 (en) * 2008-03-18 2013-08-13 Infineon Technologies Ag Electronic device including a carrier and a semiconductor chip attached to the carrier and manufacturing thereof
US8138587B2 (en) * 2008-09-30 2012-03-20 Infineon Technologies Ag Device including two mounting surfaces
US7898067B2 (en) * 2008-10-31 2011-03-01 Fairchild Semiconductor Corporaton Pre-molded, clip-bonded multi-die semiconductor package
WO2010113120A1 (en) * 2009-04-02 2010-10-07 Koninklijke Philips Electronics N.V. An integrated circuit system with a thermally isolating frame construction and method for producing such integrated circuit system
WO2011016360A1 (en) * 2009-08-03 2011-02-10 株式会社安川電機 Power converter
US20110075392A1 (en) 2009-09-29 2011-03-31 Astec International Limited Assemblies and Methods for Directly Connecting Integrated Circuits to Electrically Conductive Sheets
JP5126278B2 (en) * 2010-02-04 2013-01-23 株式会社デンソー Semiconductor device and manufacturing method thereof
JP2011187809A (en) * 2010-03-10 2011-09-22 Renesas Electronics Corp Semiconductor device and multilayer wiring board
JP5655339B2 (en) * 2010-03-26 2015-01-21 サンケン電気株式会社 Semiconductor device
JP5253455B2 (en) 2010-06-01 2013-07-31 三菱電機株式会社 Power semiconductor device
JP5709299B2 (en) * 2010-09-29 2015-04-30 ローム株式会社 Semiconductor power module and a manufacturing method thereof
US8749034B2 (en) 2011-01-03 2014-06-10 International Rectifier Corporation High power semiconductor package with conductive clip and flip chip driver IC with integrated control transistor
US20120200281A1 (en) * 2011-02-07 2012-08-09 Texas Instruments Incorporated Three-Dimensional Power Supply Module Having Reduced Switch Node Ringing
JP5936310B2 (en) * 2011-03-17 2016-06-22 三菱電機株式会社 The power semiconductor module and its mounting structure
EP2701192B1 (en) * 2011-04-18 2017-11-01 Mitsubishi Electric Corporation Semiconductor device, inverter device provided with semiconductor device, and in-vehicle rotating electrical machine provided with semiconductor device and inverter device
JP5947537B2 (en) * 2011-04-19 2016-07-06 トヨタ自動車株式会社 Semiconductor device and manufacturing method thereof
JP5431406B2 (en) * 2011-04-22 2014-03-05 ルネサスエレクトロニクス株式会社 Semiconductor device
JP5254398B2 (en) * 2011-04-22 2013-08-07 ルネサスエレクトロニクス株式会社 Semiconductor device
US8531016B2 (en) * 2011-05-19 2013-09-10 International Rectifier Corporation Thermally enhanced semiconductor package with exposed parallel conductive clip
US8614503B2 (en) * 2011-05-19 2013-12-24 International Rectifier Corporation Common drain exposed conductive clip for high power semiconductor packages
US8344464B2 (en) 2011-05-19 2013-01-01 International Rectifier Corporation Multi-transistor exposed conductive clip for high power semiconductor packages
WO2012169044A1 (en) * 2011-06-09 2012-12-13 三菱電機株式会社 Semiconductor device
US9881898B2 (en) * 2011-11-07 2018-01-30 Taiwan Semiconductor Manufacturing Co.,Ltd. System in package process flow
US20130113115A1 (en) * 2011-11-07 2013-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. System in package process flow
DE102011088250A1 (en) * 2011-12-12 2013-06-13 Robert Bosch Gmbh Power module for an electric drive
DE102011089740B4 (en) * 2011-12-23 2017-01-19 Conti Temic Microelectronic Gmbh power module
US8916968B2 (en) 2012-03-27 2014-12-23 Infineon Technologies Ag Multichip power semiconductor device
US8847385B2 (en) * 2012-03-27 2014-09-30 Infineon Technologies Ag Chip arrangement, a method for forming a chip arrangement, a chip package, a method for forming a chip package
JP5924110B2 (en) * 2012-05-11 2016-05-25 株式会社ソシオネクスト The method of manufacturing a semiconductor device, a semiconductor device module and a semiconductor device
WO2013171946A1 (en) * 2012-05-15 2013-11-21 パナソニック株式会社 Method for manufacturing semiconductor device and semiconductor device
JP5924164B2 (en) * 2012-07-06 2016-05-25 株式会社豊田自動織機 Semiconductor device
US9171837B2 (en) 2012-12-17 2015-10-27 Nxp B.V. Cascode circuit
JP5487290B2 (en) * 2012-12-21 2014-05-07 ルネサスエレクトロニクス株式会社 Semiconductor device
JP5966921B2 (en) * 2012-12-28 2016-08-10 トヨタ自動車株式会社 A method of manufacturing a semiconductor module
JP5493021B2 (en) * 2013-03-08 2014-05-14 ルネサスエレクトロニクス株式会社 Semiconductor device
JP5966979B2 (en) * 2013-03-14 2016-08-10 株式会社デンソー Semiconductor device and manufacturing method thereof
WO2014202282A1 (en) * 2013-06-20 2014-12-24 Conti Temic Microelectronic Gmbh Circuit board
US8884420B1 (en) * 2013-07-12 2014-11-11 Infineon Technologies Austria Ag Multichip device
DE102013217802A1 (en) * 2013-09-05 2015-03-05 Infineon Technologies Ag A semiconductor device, method for manufacturing a semiconductor device, method for manufacturing a semiconductor device and method of operating a semiconductor device
JP2015056563A (en) * 2013-09-12 2015-03-23 株式会社東芝 Semiconductor device and method of manufacturing the same
US20150145107A1 (en) * 2013-11-26 2015-05-28 Infineon Technologies Ag Semiconductor Chip with Electrically Conducting Layer
US9437516B2 (en) * 2014-01-07 2016-09-06 Infineon Technologies Austria Ag Chip-embedded packages with backside die connection
US9837380B2 (en) * 2014-01-28 2017-12-05 Infineon Technologies Austria Ag Semiconductor device having multiple contact clips
JP6228490B2 (en) * 2014-03-04 2017-11-08 ローム株式会社 The method of manufacturing a semiconductor device and a semiconductor device
US9431327B2 (en) * 2014-05-30 2016-08-30 Delta Electronics, Inc. Semiconductor device
DE102014114933A1 (en) * 2014-10-15 2016-04-21 Infineon Technologies Austria Ag Semiconductor device
US9704787B2 (en) * 2014-10-16 2017-07-11 Infineon Technologies Americas Corp. Compact single-die power semiconductor package
JP6152842B2 (en) * 2014-11-04 2017-06-28 トヨタ自動車株式会社 Semiconductor device and manufacturing method thereof
US9780018B2 (en) * 2014-12-16 2017-10-03 Infineon Technologies Americas Corp. Power semiconductor package having reduced form factor and increased current carrying capability
CN105551982A (en) * 2015-12-24 2016-05-04 江苏长电科技股份有限公司 Multi-chip upright tile sandwich package structure and technique therefor
CN105405832A (en) * 2015-12-24 2016-03-16 江苏长电科技股份有限公司 Part frame exposed multi-chip flat-paved sandwich encapsulation structure and technological process thereof
CN105448881A (en) * 2015-12-24 2016-03-30 江苏长电科技股份有限公司 Framework exposed multi-core multi-lapping, tiling and core-sandwiching packaging structure and technological method thereof
CN105609425A (en) * 2015-12-24 2016-05-25 江苏长电科技股份有限公司 Multi-chip and single-lap flat sandwich package structure with partially exposed frames and technique for multi-chip and single-lap flat sandwich package structure
CN105448880A (en) * 2015-12-24 2016-03-30 江苏长电科技股份有限公司 Multi-core single-lapping, tiling and core-sandwiching packaging structure and technological method thereof
CN105405831A (en) * 2015-12-24 2016-03-16 江苏长电科技股份有限公司 Frame exposed multi-chip forward-assembled flat-paved sandwich encapsulation structure and technological process thereof
CN105405833A (en) * 2015-12-24 2016-03-16 江苏长电科技股份有限公司 Multi-chip multi-overlap flat-paved sandwich encapsulation structure and technological process thereof
CN105448882A (en) * 2015-12-24 2016-03-30 江苏长电科技股份有限公司 Exposed-frame multi-chip single-lap tiled sandwiched core package structure and production method thereof
CN105633051A (en) * 2015-12-24 2016-06-01 江苏长电科技股份有限公司 Multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and process method of structure
DE102016107792A1 (en) * 2016-04-27 2017-11-02 Infineon Technologies Ag Pack with a vertical connection between the carrier and clip
US9773753B1 (en) * 2016-11-18 2017-09-26 Advanced Semiconductor Engineering, Inc. Semiconductor devices and methods of manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110893A (en) 2000-10-04 2002-04-12 Denso Corp Semiconductor device
JP2003046036A (en) 2001-08-01 2003-02-14 Denso Corp Semiconductor device
US6693350B2 (en) * 1999-11-24 2004-02-17 Denso Corporation Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
US6891265B2 (en) * 1999-11-24 2005-05-10 Denso Corporation Semiconductor device having radiation structure
US6917103B2 (en) * 2001-12-27 2005-07-12 Denso Corporation Molded semiconductor power device having heat sinks exposed on one surface
US6963133B2 (en) * 2001-04-25 2005-11-08 Denso Corporation Semiconductor device and method for manufacturing semiconductor device

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3129020B2 (en) 1992-04-09 2001-01-29 富士電機株式会社 Semiconductor device
JP2894089B2 (en) 1992-06-19 1999-05-24 竹内精工株式会社 Linear motion bearings
KR20000057810A (en) * 1999-01-28 2000-09-25 가나이 쓰토무 Semiconductor device
KR100335481B1 (en) * 1999-09-13 2002-05-04 김덕중 Power device having multi-chip package structure
JP2001291823A (en) 2000-04-05 2001-10-19 Toshiba Corp Semiconductor device
EP2234154B1 (en) 2000-04-19 2016-03-30 Denso Corporation Coolant cooled type semiconductor device
JP4192396B2 (en) 2000-04-19 2008-12-10 株式会社デンソー Semiconductor switching module - Le and a semiconductor device using the same
JP4423746B2 (en) 2000-05-10 2010-03-03 株式会社デンソー The refrigerant cooled double-sided cooling semiconductor device
JP4292686B2 (en) 2000-06-08 2009-07-08 株式会社デンソー The refrigerant cooled double-sided cooling semiconductor device
JP3578335B2 (en) 2000-06-29 2004-10-20 株式会社デンソー The power semiconductor device
JP4774581B2 (en) 2000-06-30 2011-09-14 株式会社デンソー The cooling fluid cooled semiconductor device
US6545364B2 (en) * 2000-09-04 2003-04-08 Sanyo Electric Co., Ltd. Circuit device and method of manufacturing the same
US6707671B2 (en) 2001-05-31 2004-03-16 Matsushita Electric Industrial Co., Ltd. Power module and method of manufacturing the same
US7215022B2 (en) 2001-06-21 2007-05-08 Ati Technologies Inc. Multi-die module
US6946740B2 (en) 2002-07-15 2005-09-20 International Rectifier Corporation High power MCM package
JP4294405B2 (en) * 2003-07-31 2009-07-15 株式会社ルネサステクノロジ Semiconductor device
JP3809168B2 (en) * 2004-02-03 2006-08-16 株式会社東芝 Semiconductor module
DE102004047358B3 (en) * 2004-09-29 2005-11-03 Infineon Technologies Ag In two semiconductor bodies integrated circuit arrangement having a power component and a drive circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6693350B2 (en) * 1999-11-24 2004-02-17 Denso Corporation Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
US6891265B2 (en) * 1999-11-24 2005-05-10 Denso Corporation Semiconductor device having radiation structure
US6960825B2 (en) * 1999-11-24 2005-11-01 Denso Corporation Semiconductor device having radiation structure
JP2002110893A (en) 2000-10-04 2002-04-12 Denso Corp Semiconductor device
US6963133B2 (en) * 2001-04-25 2005-11-08 Denso Corporation Semiconductor device and method for manufacturing semiconductor device
JP2003046036A (en) 2001-08-01 2003-02-14 Denso Corp Semiconductor device
US6917103B2 (en) * 2001-12-27 2005-07-12 Denso Corporation Molded semiconductor power device having heat sinks exposed on one surface

Cited By (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9793265B2 (en) 2004-07-30 2017-10-17 Renesas Electronics Corporation Semiconductor device including Schottky barrier diode and power MOSFETs and a manufacturing method of the same
US20140054692A1 (en) * 2004-07-30 2014-02-27 Renesas Electronics Corporation Semiconductor device and a manufacturing method of the same
US8853846B2 (en) * 2004-07-30 2014-10-07 Renesas Electronics Corporation Semiconductor device and a manufacturing method of the same
US8592904B2 (en) 2004-07-30 2013-11-26 Renesas Electronics Corporation Semiconductor device including Schottky barrier diode
US8138598B2 (en) 2004-07-30 2012-03-20 Renesas Electronics Corporation Semiconductor device and a manufacturing method of the same
US9153686B2 (en) 2004-07-30 2015-10-06 Renesas Electronics Corporation Semiconductor device including DC-DC converter
US8519533B2 (en) 2004-07-30 2013-08-27 Renesas Electronics Corporation Semiconductor device including a DC-DC converter with schottky barrier diode
US7687902B2 (en) * 2004-07-30 2010-03-30 Renesas Technology Corp. Semiconductor device and a manufacturing method of the same
US9461163B2 (en) 2004-07-30 2016-10-04 Renesas Electronics Corporation Semiconductor device including Schottky barrier diode and power MOSFETs and a manufacturing method of the same
US20060022298A1 (en) * 2004-07-30 2006-02-02 Masaki Shiraishi Semiconductor device and a manufacturing method of the same
US20090001532A1 (en) * 2006-01-10 2009-01-01 Sanken Electric Co., Ltd. Plastic-Encapsulated Semiconductor Device with an Exposed Radiator at the Top and Manufacture Thereof
US8003447B2 (en) * 2006-02-13 2011-08-23 Fairchild Semiconductor Corporation Multi-chip module for battery power control
US20070187807A1 (en) * 2006-02-13 2007-08-16 Jeongil Lee Multi-chip module for battery power control
US7868432B2 (en) * 2006-02-13 2011-01-11 Fairchild Semiconductor Corporation Multi-chip module for battery power control
US20110078899A1 (en) * 2006-02-13 2011-04-07 Jeongil Lee Multi-chip module for battery power control
US20070216011A1 (en) * 2006-03-17 2007-09-20 Ralf Otremba Multichip module with improved system carrier
US8115294B2 (en) * 2006-03-17 2012-02-14 Infineon Technologies Ag Multichip module with improved system carrier
US8592914B2 (en) 2006-03-28 2013-11-26 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
US8237232B2 (en) 2006-03-28 2012-08-07 Renesas Electronics Corporation Semiconductor device including a DC-DC converter having a metal plate
US20110169102A1 (en) * 2006-03-28 2011-07-14 Renesas Electronics Corporation Semiconductor device including a dc-dc converter having a metal plate
US20110278655A1 (en) * 2006-05-30 2011-11-17 Renesas Electronics Corporation Semiconductor Device with Circuit for Reduced Parasitic Inductance
US7872350B2 (en) * 2007-04-10 2011-01-18 Qimonda Ag Multi-chip module
US20080251912A1 (en) * 2007-04-10 2008-10-16 Ralf Otremba Multi-Chip Module
US20090085181A1 (en) * 2007-09-28 2009-04-02 Advincula Jr Abelardo Hadap Integrated circuit package system with multiple die
US8067825B2 (en) * 2007-09-28 2011-11-29 Stats Chippac Ltd. Integrated circuit package system with multiple die
US20110059580A1 (en) * 2008-01-02 2011-03-10 Oseob Jeon High-power semiconductor die packages with integrated heat-sink capability and methods of manufacturing the same
US20090166850A1 (en) * 2008-01-02 2009-07-02 Oseob Jeon High-Power Semiconductor Die Packages With Integrated Heat-Sink Capability and Methods of Manufacturing the Same
US7800219B2 (en) * 2008-01-02 2010-09-21 Fairchild Semiconductor Corporation High-power semiconductor die packages with integrated heat-sink capability and methods of manufacturing the same
US8193043B2 (en) 2008-01-02 2012-06-05 Fairchild Semiconductor Corporation High-power semiconductor die packages with integrated heat-sink capability and methods of manufacturing the same
US20100270992A1 (en) * 2009-04-28 2010-10-28 Renesas Electronics Corporation Semiconductor device
US20110012255A1 (en) * 2009-07-16 2011-01-20 Shinko Electric Industries Co., Ltd. Semiconductor device
DE102010030838A1 (en) * 2010-07-02 2012-01-05 Robert Bosch Gmbh A semiconductor device with improved heat dissipation
US9711437B2 (en) 2010-12-13 2017-07-18 Infineon Technologies Americas Corp. Semiconductor package having multi-phase power inverter with internal temperature sensor
US9659845B2 (en) 2010-12-13 2017-05-23 Infineon Technologies Americas Corp. Power quad flat no-lead (PQFN) package in a single shunt inverter circuit
US9620954B2 (en) 2010-12-13 2017-04-11 Infineon Technologies Americas Corp. Semiconductor package having an over-temperature protection circuit utilizing multiple temperature threshold values
US9530724B2 (en) 2010-12-13 2016-12-27 Infineon Technologies Americas Corp. Compact power quad flat no-lead (PQFN) package
US9899302B2 (en) 2010-12-13 2018-02-20 Infineon Technologies Americas Corp. Semiconductor package having multi-phase power inverter with internal temperature sensor
US20120181706A1 (en) * 2011-01-18 2012-07-19 Jian-Hong Zeng Power semiconductor package structure and manufacturing method thereof
US8426963B2 (en) * 2011-01-18 2013-04-23 Delta Electronics, Inc. Power semiconductor package structure and manufacturing method thereof
US9786516B2 (en) 2011-06-30 2017-10-10 Stmicroelectronics S.R.L. Power device having reduced thickness
US8755188B2 (en) * 2011-06-30 2014-06-17 Stmicroelectronics S.R.L. Half-bridge electronic device with common auxiliary heat sink
US20130003309A1 (en) * 2011-06-30 2013-01-03 Stmicroelectronics S.R.L. Half-bridge electronic device with common auxiliary heat sink
US9105598B2 (en) 2011-06-30 2015-08-11 Stmicroelectronics S.R.L. Package/heatsink system for electronic device
US8837154B2 (en) 2011-06-30 2014-09-16 Stmicroelectronics S.R.L. System with stabilized heatsink
US8837153B2 (en) 2011-06-30 2014-09-16 Stmicroelectronics S.R.L. Power electronic device having high heat dissipation and stability
US20130003305A1 (en) * 2011-06-30 2013-01-03 Stmicroelectronics S.R.L. Half-bridge electronic device with common heat sink on mounting surface
US8817475B2 (en) 2011-06-30 2014-08-26 Stmicroelectronics S.R.L. System with shared heatsink
US9275943B2 (en) 2011-06-30 2016-03-01 Stmicroelectronics S.R.L. Power device having reduced thickness
US8860192B2 (en) 2011-06-30 2014-10-14 Stmicroelectronics S.R.L. Power device having high switching speed
US8723311B2 (en) * 2011-06-30 2014-05-13 Stmicroelectronics S.R.L. Half-bridge electronic device with common heat sink on mounting surface
US9236321B2 (en) 2012-02-15 2016-01-12 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US9018744B2 (en) * 2012-09-25 2015-04-28 Infineon Technologies Ag Semiconductor device having a clip contact
US9343451B2 (en) 2012-09-26 2016-05-17 Renesas Electronics Corporation Method of manufacturing semiconductor device
US9704844B2 (en) 2012-09-26 2017-07-11 Renesas Electronics Corporation Method of manufacturing semiconductor device
US9029197B2 (en) 2012-09-26 2015-05-12 Renesas Electronics Corporation Method of manufacturing semiconductor device
US20140117526A1 (en) * 2012-10-31 2014-05-01 Kabushiki Kaisha Toshiba Semiconductor power converter and method of manufacturing the same
US9147673B2 (en) * 2012-10-31 2015-09-29 Kabushiki Kaisha Toshiba Semiconductor power converter and method of manufacturing the same
US9202796B2 (en) 2013-01-31 2015-12-01 Samsung Electronics Co., Ltd. Semiconductor package including stacked chips and a redistribution layer (RDL) structure

Also Published As

Publication number Publication date Type
KR101127199B1 (en) 2012-03-29 grant
KR20100028606A (en) 2010-03-12 application
KR101168973B1 (en) 2012-07-27 grant
KR20120008480A (en) 2012-01-30 application
KR101168972B1 (en) 2012-07-27 grant
CN1649146A (en) 2005-08-03 application
USRE41869E1 (en) 2010-10-26 grant
CN100521196C (en) 2009-07-29 grant
KR101100838B1 (en) 2012-01-02 grant
KR101127195B1 (en) 2012-03-29 grant
KR20120008481A (en) 2012-01-30 application
KR20050077759A (en) 2005-08-03 application
KR20100028605A (en) 2010-03-12 application
JP2005217072A (en) 2005-08-11 application
CN101567367A (en) 2009-10-28 application
US20050161785A1 (en) 2005-07-28 application
USRE43663E1 (en) 2012-09-18 grant
CN101567367B (en) 2011-07-20 grant

Similar Documents

Publication Publication Date Title
US6054754A (en) Multi-capacitance lead frame decoupling device
US7436070B2 (en) Semiconductor device
US7271470B1 (en) Electronic component having at least two semiconductor power devices
US6566164B1 (en) Exposed copper strap in a semiconductor package
US6946740B2 (en) High power MCM package
US20120326287A1 (en) Dc/dc convertor power module package incorporating a stacked controller and construction methodology
US7149088B2 (en) Half-bridge power module with insert molded heatsinks
US20060055432A1 (en) Semiconductor module
US20050280163A1 (en) Semiconductor device module with flip chip devices on a common lead frame
US20080197463A1 (en) Electronic Component And Method For Manufacturing An Electronic Component
US20070249092A1 (en) Semiconductor die package including multiple dies and a common node structure
US5170337A (en) Low-inductance package for multiple paralleled devices operating at high frequency
US7291869B2 (en) Electronic module with stacked semiconductors
US6806580B2 (en) Multichip module including substrate with an array of interconnect structures
US5977630A (en) Plural semiconductor die housed in common package with split heat sink
US7045884B2 (en) Semiconductor device package
US6593622B2 (en) Power mosfet with integrated drivers in a common package
US20050156204A1 (en) Semiconductor device
US20030183924A1 (en) High speed switching mosfets using multi-parallel die packages with/without special leadframes
US20080017907A1 (en) Semiconductor Module with a Power Semiconductor Chip and a Passive Component and Method for Producing the Same
US6448643B2 (en) Three commonly housed diverse semiconductor dice
US20050133902A1 (en) Dual semiconductor die package with reverse lead form
US20040004272A1 (en) Integrated circuit package for semicoductor devices with improved electric resistance and inductance
US20050285238A1 (en) Integrated transistor module and method of fabricating same
US20070132079A1 (en) Power Semiconductor Component With Semiconductor Chip Stack In A Bridge Circuit And Method For Producing The Same

Legal Events

Date Code Title Description
AS Assignment

Owner name: RENESAS TECHNOLOGY CORP., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KAWASHIMA, TETSUYA;MISHIMA, AKIRA;REEL/FRAME:016221/0414

Effective date: 20050112

RF Reissue application filed

Effective date: 20080530

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: RENESAS ELECTRONICS CORPORATION,JAPAN

Free format text: MERGER;ASSIGNOR:RENESAS TECHNOLOGY CORP.;REEL/FRAME:024599/0001

Effective date: 20100401

RF Reissue application filed

Effective date: 20100623

AS Assignment

Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN

Free format text: MERGER;ASSIGNOR:RENESAS TECHNOLOGY CORP.;REEL/FRAME:025008/0362

Effective date: 20100401

RF Reissue application filed

Effective date: 20120914