US20110278655A1 - Semiconductor Device with Circuit for Reduced Parasitic Inductance - Google Patents

Semiconductor Device with Circuit for Reduced Parasitic Inductance Download PDF

Info

Publication number
US20110278655A1
US20110278655A1 US13/192,584 US201113192584A US2011278655A1 US 20110278655 A1 US20110278655 A1 US 20110278655A1 US 201113192584 A US201113192584 A US 201113192584A US 2011278655 A1 US2011278655 A1 US 2011278655A1
Authority
US
United States
Prior art keywords
semiconductor chip
power
electrically connected
external terminal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/192,584
Inventor
Takayuki Hashimoto
Noboru Akiyama
Masaki Shiraishi
Tetsuya Kawashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to US13/192,584 priority Critical patent/US20110278655A1/en
Publication of US20110278655A1 publication Critical patent/US20110278655A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the present invention relates to a technology for a semiconductor device. More particularly, it relates to a technology effectively applied to a semiconductor device having a power source circuit.
  • a power MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the power MOSFET for high side has a switch function for control of the DC-DC converter
  • the MOSFET for low side has a switch function for synchronous rectification.
  • Patent Document 1 Japanese Unexamined Patent Application Publication (Tokuhyo) No. 2003-528449 (Patent Document 1), and it discloses a structure in which a power MOSFET for high side, a power MOSFET for low side, a driver circuit which drives these power MOSFETs, and an input capacitor are contained in the same package.
  • Patent Document 2 discloses a package structure in which a power MOSFET for high side constituting a DC-DC converter is formed of a horizontal power MOSFET, a power MOSFET for low side is formed of a vertical power MOSFET, and these power MOSFETs are mounted on a common frame.
  • a structure in which a semiconductor chip on which a power MOSFET for high side is formed and a semiconductor chip on which a power MOSFET for low side is formed are contained in the same package is used. Further, a structure in which a semiconductor chip on which a power MOSFET for high side is formed, a semiconductor chip on which a power MOSFET for low side is formed, and a semiconductor chip on which a driver circuit is formed are contained in the same package is also used. In both cases, the respective semiconductor chips are mounted on respectively different die pads, and the source of the power MOSFET for high side is electrically connected via a bonding wire to the die pad on which the semiconductor chip on which the power MOSFET for low side is formed is mounted.
  • the Patent Document 2 discloses a structure in which a semiconductor chip on which a power MOSFET for high side is formed, a semiconductor chip on which a power MOSFET for low side is formed, a semiconductor chip on which a driver circuit is formed, and an input capacitor Cin are contained in the same package.
  • the source of the power MOSFET for high side is electrically connected to a wiring of a wiring board via a bonding wire
  • the wiring is electrically connected to the drain of the power MOSFET for low side.
  • the source of the power MOSFET for low side is electrically connected via a bonding wire to the output wiring of the wiring board.
  • an object of the present invention is to provide a technology capable of reducing the parasitic inductance of the main circuit of a power source circuit.
  • a field effect transistor of a first semiconductor chip is formed of an n-channel vertical field effect transistor
  • a field effect transistor of a second semiconductor chip is formed of an n-channel vertical field effect transistor
  • a surface on which a source electrode of the first semiconductor chip is disposed and a surface on which a drain electrode of the second semiconductor chip is disposed are mounted on the same chip mounting portion and electrically connected to each other
  • a drain electrode of the first semiconductor chip has a first lead plate connected to an external terminal for supplying input power
  • a source electrode of the second semiconductor chip has a second lead plate connected to an external terminal for supplying reference potential.
  • a field effect transistor of a first semiconductor chip is formed of an n-channel vertical field effect transistor
  • a field effect transistor of a second semiconductor chip is formed of an n-channel vertical field effect transistor
  • a surface on which a source electrode of the first semiconductor chip is disposed and a surface on which a drain electrode of the second semiconductor chip is disposed are mounted on the same chip mounting portion and electrically connected to each other
  • a drain electrode of the first semiconductor chip has a first lead plate connected to an external terminal for supplying input power
  • a source electrode of the second semiconductor chip has a second lead plate connected to an external terminal for supplying reference potential
  • a capacitor electrically connected between the first lead plate and the second lead plate is provided, and in the capacitor, one of a pair of electrodes is connected to the first lead plate and the other of the pair of electrodes is connected to the second lead plate.
  • a field effect transistor of a first semiconductor chip is formed of an n-channel vertical field effect transistor
  • a field effect transistor of a second semiconductor chip is formed of an n-channel vertical field effect transistor
  • a surface on which a source electrode of the first semiconductor chip is disposed and a surface on which a drain electrode of the second semiconductor chip is disposed are mounted on the same chip mounting portion and electrically connected to each other
  • a drain electrode of the first semiconductor chip has a first lead plate connected to an external terminal for supplying input power
  • a source electrode of the second semiconductor chip has a second lead plate connected to an external terminal for supplying reference potential.
  • FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a timing chart of the semiconductor device in FIG. 1 ;
  • FIG. 3 is a plan view showing an inside of a package examined by the inventors of the present invention.
  • FIG. 4 is a cross sectional view taken along the line Y 1 -Y 1 in FIG. 3 ;
  • FIG. 5 is a plan view showing an inside of a package examined by the inventors of the present invention.
  • FIG. 6 is a cross sectional view taken along the Y 2 -Y 2 in FIG. 5 ;
  • FIG. 7 is a plan view showing an inside of a package according to Patent Document 2 examined by the inventors of the present invention.
  • FIG. 8 is a plan view showing an inside of a package of a semiconductor device according to an embodiment of the present invention.
  • FIG. 9 is a cross sectional view taken along the line Y 3 -Y 3 in FIG. 8 ;
  • FIG. 10 is a plan view showing an inside of a package of a semiconductor device according to an embodiment of the present invention.
  • FIG. 11 is a cross sectional view taken along the line Y 4 -Y 4 in FIG. 10 ;
  • FIG. 12 is a cross sectional view of a semiconductor device according to an embodiment of the present invention.
  • FIG. 13 is a graph showing the relation between main circuit inductance and switching loss for describing the effect of the present invention.
  • FIG. 14 is a graph showing the relation between main circuit inductance and jump voltage for describing the effect of the present invention.
  • FIG. 15A is a diagram for describing the MOS for low side in FIG. 8 and peripheral structure thereof;
  • FIG. 15B is a diagram for describing the MOS for low side in FIG. 8 and peripheral structure thereof;
  • FIG. 15C is a diagram for describing the MOS for low side in FIG. 8 and peripheral structure thereof.
  • FIG. 15D is a diagram for describing the MOS for low side in FIG. 8 and peripheral structure thereof.
  • the invention will be described in a plurality of sections or embodiments when required as a matter of convenience. However, these sections or embodiments are not irrelevant to each other unless otherwise stated, and the one relates to the entire or a part of the other as a modification example, details, or a supplementary explanation thereof. Also, in the embodiments described below, when referring to the number of elements (including number of pieces, values, amount, range, and the like), the number of the elements is not limited to a specific number unless otherwise stated or except the case where the number is apparently limited to a specific number in principle. The number larger or smaller than the specified number is also applicable.
  • a semiconductor device is a non-insulated DC-DC converter used for a power source circuit of, for example, a desktop personal computer, a notebook personal computer, a server, a game machine and others.
  • FIG. 1 shows the circuit diagram of an example of a non-insulated DC-DC converter 1 examined by the inventors of the present invention.
  • the non-insulated DC-DC converter 1 has such elements as a control circuit 2 , a driver circuit 3 , power MOSFETs (hereinafter, referred to simply as power MOS) QH 1 and QL 1 , an input capacitor Cin, an output capacitor Cout, and a coil L.
  • D denotes a drain
  • S denotes a source.
  • L 1 to L 6 denote parasitic inductances that parasitize in the main circuit of the non-insulated DC-DC converter.
  • the control circuit 2 is a circuit that supplies the signal to control the width of voltage switch on (ON time) of the power MOSs QH 1 and QL 1 such as a pulse width modulation (PWM) circuit.
  • the output of the control circuit 2 (terminal for control signals) is electrically connected to the input of the driver circuit 3 .
  • the output of the driver circuit (first control circuit) 3 is electrically connected to the gate terminal GH of the power MOS QH 1 and the gate terminal GL of the power MOS QL 1 .
  • the driver circuit 3 controls the potentials of the gate terminals GH and GL of the respective power MOSs QH 1 and QL 1 , thereby controlling the operations of the power MOSs QH 1 and QL 1 .
  • VDIN denotes the input power of the driver circuit 3 .
  • the power MOSs QH 1 and QL 1 are connected in series between a terminal (first power source terminal) ET 1 for supplying high potential (first power source potential) VDD of the input power source VIN and a terminal (second power source terminal) ET 2 for supplying reference potential (second power source potential) GND. That is, the power MOS QH 1 is disposed so that the source and drain paths thereof are connected in series between the terminal ET 1 for supplying high potential VDD of the input power source VIN and the output node (output terminal) Lx, and the power MOS QL 1 is disposed so that the source and drain paths thereof are connected in series between the output node Lx and the terminal ET 2 for supplying ground potential GND.
  • Dp 1 denotes a parasitic diode (internal diode) of the power MOS QH 1
  • Dp 2 denotes a parasitic diode (internal diode) of the power MOS QL 1 .
  • the power MOS QH 1 is a power transistor for high side switch (high potential side: first operation voltage; hereinafter, referred to simply as high side) and has a switch function to store energy in the coil L that supplies electric power to the output of the non-insulated DC-DC converter 1 (input of the load circuit 4 ).
  • This power MOSFET QH 1 is formed of an n-channel vertical field effect transistor.
  • the vertical field effect transistor is an element whose channel is formed in a thickness direction of the semiconductor chip, and it can increase the channel width per unit area more than the horizontal field effect transistor and can reduce ON-resistance. Therefore, it is possible to realize the size reduction of the element and the reduction of the package size.
  • the power MOS (second field effect transistor) QL 1 is a power transistor for low side switch (low potential side: second operation voltage; hereinafter, referred to simply as low side), and it is a transistor for rectification of the non-insulated DC-DC converter 1 and has a function to perform rectification by lowering the resistance of the transistor in synchronization with the frequency from the control circuit 2 .
  • this power MOS QL 1 is formed of an n-channel vertical power MOS. The reason why the vertical type is used is as follows. That is, as shown in the timing chart of the non-insulated DC-DC converter 1 of FIG.
  • the power MOS QL 1 for low side has a longer ON time (time of applying voltage) than the ON time of the power MOS QH 1 for high side, and losses by ON resistance appears larger than switching loss. Accordingly, it is advantageous to use the vertical field effect transistor that can increase the channel width per unit area more than the horizontal field effect transistor. In other words, by forming the power MOS QL 1 for low side by the vertical field effect transistor, the ON resistance can be lowered, and thus, it is possible to improve the voltage conversion efficiency even if the current flowing in the non-insulated DC-DC converter 1 increases. Meanwhile, in FIG. 2 , Ton denotes the pulse width at ON time of the power MOS QH 1 for high side, and T denotes the pulse period.
  • the input capacitor Cin is electrically connected to the input power source VIN in FIG. 1 in parallel.
  • This input capacitor Cin is a power source circuit that temporarily stores the energy (electric charge) supplied from the input power source VIN and supplies the stored energy to the main circuit of the non-insulated DC-DC converter 1 .
  • the input power source VIN is the power source for not only the non-insulated DC-DC converter 1 but also other devices, it is disposed at a position away from the non-insulated DC-DC converter 1 , and since the power supply efficiency decreases if power is supplied from the input power source VIN directly to the non-insulated DC-DC converter 1 , power is supplied to the input capacitor Cin disposed at a relatively close position to the main circuit of the non-insulated DC-DC converter 1 , and then the power is supplied therefrom to the main circuit of the non-insulated DC-DC converter 1 .
  • the input power source potential VDD of the input power source VIN is, for example, around 5 to 12 V.
  • the reference potential GND is, for example, lower than the input power source potential and is, for example, ground potential 0 V.
  • the operation frequency of the non-insulated DC-DC converter 1 (period to turn ON and OFF the power MOSs QH 1 and QL 1 ) is, for example, 1 MHz.
  • the output node Lx that supplies the output power source potential to the outside is disposed.
  • the output node Lx is electrically connected via the output wiring to the coil L, and further electrically connected via the output wiring to the load circuit 4 .
  • a Schottky barrier diode (hereinafter, referred to as SBD) may be electrically connected between the output wiring that connects this output node Lx and the coil L and the terminal for supplying the reference potential GND so as to be in parallel to the above-mentioned power MOS QL 1 .
  • the SBD is a diode whose forward voltage Vf is lower than that of the parasitic diode Dp 2 of the power MOS QL 1 .
  • the anode thereof is electrically connected to the terminal ET 2 for supplying the reference potential GND, and the cathode thereof is electrically connected to the output wiring that connects the output node Lx and the drain of the power MOS QL 1 .
  • the output capacitor Cout is electrically connected between the output wiring that connects the coil L and the load circuit 4 and the terminal for supplying the reference potential GND.
  • a central processing unit (CPU) or a micro processing unit (MPU) of the above-mentioned electronic device and the like can be exemplified. Iout denotes output current and Vout denotes output voltage.
  • the power MOSs QH 1 and QL 1 are alternately turned ON/OFF in synchronization, thereby converting the power source voltage. That is, when the power MOS QH 1 for high side switch is ON, current (first current) I 1 flows from the terminal ET 1 electrically connected to the drain D of the power MOS QH 1 via the power MOS QH 1 to the output node Lx, and when the power MOS QH 1 for high side switch is OFF, current I 2 flows by the back electromotive voltage of the coil L. By turning on the power MOS QL 1 for low side switch when this current I 2 is flowing, the voltage drop can be reduced.
  • the current I 1 is large current of, for example, about 20 A.
  • FIG. 3 is a plan view showing the inside of the package
  • FIG. 4 is a cross sectional view taken along the line Y 1 -Y 1 in FIG. 3 .
  • a semiconductor chip 5 a on which the power MOS QH 1 for high side and a semiconductor chip 5 b on which the power MOS QL 1 for low side are contained in the same sealing body 6 .
  • Semiconductor chips 5 a and 5 b are mounted on respectively different die pads 7 a 1 and 7 a 2 .
  • the source of the power MOS QH 1 for high side is electrically connected via a bonding wire (hereinafter, referred to simply as wire) W to the die pad 7 a 2 on which the power MOS QL 1 for low side is mounted.
  • wire bonding wire
  • FIG. 5 is a plan view showing the inside of the package
  • FIG. 6 is a cross sectional view taken along the line Y 2 -Y 2 in FIG. 5 .
  • a semiconductor chip 5 c on which the driver circuit 3 is formed is also contained in the same sealing body 6 .
  • the semiconductor chip 5 c is mounted on a die pad 7 a 3 different from the die pads 7 a 1 and 7 a 2 .
  • the semiconductor chips 5 a and 5 b are mounted on respectively different die pads 7 a 1 and 7 a 2 , and the source of the power MOS QH 1 for high side is electrically connected via the wire W to the die pad 7 a 2 on which the power MOS QL 1 for low side is mounted.
  • FIG. 7 shows the package structure disclosed in the Patent Document 2, in which, in addition to the semiconductor chips 5 a , 5 b , and 5 c , the input capacitor Cin is also contained in the same sealing body 6 .
  • the source of the power MOS QH 1 for high side is electrically connected via the wire W to the wiring of a wiring board 50
  • the wiring is electrically connected to the drain of the power MOS QL 1 for low side.
  • the source of the power MOS QL 1 for low side is electrically connected via the wire W to the output wiring of the wiring board 50 .
  • the semiconductor chips 5 a , 5 b , and 5 c and the input capacitor Cin are contained in the same sealing body 6 as shown in FIG. 7 , since they are connected via the wire W, it is not possible to reduce the parasitic inductances L 3 and L 5 , and further, since there is a certain distance between the input capacitor Cin and the respective power MOSs QH 1 and QL 1 , the reduction of the parasitic inductances L 1 and L 6 is limited.
  • the power MOS for high side and the power MOS for low side are mounted on a common die pad (tab, chip mounting portion). Therefore, in the first embodiment, the power MOS for high side of the non-insulated DC-DC converter 1 is formed of an n-channel vertical power MOS, and a flip chip structure is used to connect the source electrode thereof to a die pad.
  • FIG. 8 and FIG. 9 show an example of the package structure according to the first embodiment.
  • FIG. 8 is a plan view showing the inside of the package
  • FIG. 9 is a cross sectional view taken along the line Y 3 -Y 3 in FIG. 8 .
  • the inside of the package is shown in a see-through manner for easy understanding of the structure.
  • Two separately-formed semiconductor chips 5 a and 5 b are mounted on a common die pad 8 b and contained in the package.
  • the n-channel vertical power MOS for high side of the non-insulated DC-DC converter 1 is formed on the semiconductor chip (first semiconductor chip) 5 a .
  • the n-channel vertical power MOS for low side of the non-insulated DC-DC converter 1 is formed on the semiconductor chip (second semiconductor chip) 5 b .
  • a driving IC (Integrated Circuit) 5 c (third semiconductor chip) for driving the gates of the first semiconductor chip and the second semiconductor chip is mounted on the die pad 8 d and is connected via the wire bonding to the die pad 8 b corresponding to the source electrode of the first semiconductor chip 5 a and the pad 9 b corresponding to the gate electrode thereof.
  • the third semiconductor chip is connected to the source electrode 9 c and the gate electrode pad 9 a of the second semiconductor chip via the wire bonding.
  • the drain electrode of the first semiconductor chip is connected via a lead plate 8 c to the external terminal Vin for supplying power
  • the source electrode 9 c of the second semiconductor chip is connected via the lead plate 8 a to the external terminal Gnd for supplying reference voltage
  • the common die pad 8 b is connected to the external terminal Lx for output.
  • the parasitic inductances L 3 and L 4 are reduced. Further, since the lead plate is used for the connection between the drain electrode of the MOS for high side and the external terminal and the connection between the source electrode of the MOS for low side and the external terminal, the parasitic inductances L 2 and L 5 are reduced.
  • FIG. 15A shows a pattern of the lead frame, in which the bonding pad (high side) 9 b for the gate and the lead plate 8 b for the source are shown.
  • 12 a and 12 b denote structures in an upper layer than the lead frame of FIG. 15A , that is, a gate pad 12 a and a source pad 12 b .
  • FIG. 15C shows a structure in an upper layer than the gate pad 12 a and the source pad 12 b in FIG. 15B , in which the semiconductor chip (power MOS for low side) 5 a is shown.
  • FIG. 15D shows a structure in an upper layer than the semiconductor chip 5 a in FIG. 15C , in which the lead plate (power source voltage) 8 a is shown.
  • the structure according to the first embodiment it is possible to reduce the inductances L 2 , L 3 , L 4 , and L 5 of the wirings shown in FIG. 1 .
  • the first embodiment it is not possible to reduce the parasitic inductance L 1 which occurs between the plus terminal of the input capacitor Cin and the drain terminal of the power MOS for high side and the parasitic inductance L 6 which occurs between the minus terminal of the input capacitor Cin and the source terminal of the power MOS for low side.
  • the second embodiment has been made in consideration of this, and it enables to reduce the inductances L 1 and L 6 .
  • FIG. 10 and FIG. 11 show an example of the package structure according to the second embodiment.
  • FIG. 10 is a plan view showing the inside of the package
  • FIG. 11 is a cross sectional view taken along the line Y 4 -Y 4 in FIG. 10 .
  • the inside of the package is shown in a see-through manner for easy understanding of the structure.
  • an input capacitor 11 is mounted on a surface of the package.
  • a plus electrode 11 a of the input capacitor 11 is connected via a conductive component 11 c to the lead plate 8 a that is electrically connected to the external terminal for supplying input power
  • a minus electrode 11 b of the input capacitor 11 is connected via a conductive component 11 d to the lead plate 8 b that is electrically connected to the external terminal for supplying reference potential.
  • FIG. 13 shows the wiring inductance of the main circuit in the horizontal axis and the switching loss of the power MOS for high side (first semiconductor) in the vertical axis.
  • the wiring inductance of the main circuit is equivalent to the total value of L 1 to L 6 in FIG. 1 .
  • the conventional example is the measurement result of the case using the package in FIG. 5 . Since the inductance of the present embodiment is smaller than that of the conventional example, it can be understood that the switching loss can be decreased.
  • the switching loss is small, it is possible to eliminate cooling parts such as a heat sink and the like, which makes it possible to reduce the size of a power source.
  • the switching frequency can be improved in the present embodiment. Therefore, it is possible to reduce the size of an output filter consisting of an inductor and a capacitor.
  • FIG. 14 shows the wiring inductance of the main circuit in the horizontal axis and jump voltage between the source and the drain of the MOS for high side at the time of switching in the vertical axis.
  • the jump voltage becomes smaller.
  • the conventional example is the measurement result of the case using the package in FIG. 5 . Since the inductance of the present embodiment is smaller than that of the conventional example, the jump voltage decreases. When the jump voltage is low, conduction noise and radiation noise become small, and therefore, it is possible to prevent the malfunction of other semiconductor devices and electronic devices.
  • the structure according to the second embodiment it is possible to reduce the inductances L 1 to L 6 of the wirings shown in FIG. 1 .
  • the capacitor since the capacitor is mounted on the package surface, there is a problem that the heat resistance of the surface is high.
  • the third embodiment has been made in consideration of this, and it enables to reduce the heat resistance of the surface.
  • FIG. 12 is a diagram for describing the third embodiment, and the point different from FIG. 11 is that the lead plates 8 a and 8 b are exposed on the package surface.
  • the plus electrode 11 a of the input capacitor 11 is connected to the lead plate 8 a that is electrically connected to the external terminal for supplying input power
  • the minus electrode 11 b of the input capacitor 11 is connected to the lead plate 8 b that is electrically connected to the external terminal for supplying reference potential.
  • the present invention can be applied to a semiconductor device and an electronic device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Engineering & Computer Science (AREA)
  • Dc-Dc Converters (AREA)

Abstract

Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • The application is a continuation application of U.S. patent application Ser. No. 12/721,201, filed on Mar. 10, 2010, which is a continuation of U.S. patent application Ser. No. 11/809,023, filed on May 30, 2007, which claims priority from Japanese Patent Application No. JP 2006-149489, filed on May 30, 2006, all of which are herein incorporated by reference for all purposes.
    • TECHNICAL FIELD OF THE INVENTION
  • The present invention relates to a technology for a semiconductor device. More particularly, it relates to a technology effectively applied to a semiconductor device having a power source circuit.
    • BACKGROUND OF THE INVENTION
  • In a DC-DC converter widely used as an example of a power source circuit, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) for a high side and a power MOSFET for a low side are connected in series. The power MOSFET for high side has a switch function for control of the DC-DC converter, and the MOSFET for low side has a switch function for synchronous rectification. These two power MOSFETs are alternately turned ON/OFF in synchronization, thereby converting power source voltage.
  • Such a DC-DC converter is described, for example, in Japanese Unexamined Patent Application Publication (Tokuhyo) No. 2003-528449 (Patent Document 1), and it discloses a structure in which a power MOSFET for high side, a power MOSFET for low side, a driver circuit which drives these power MOSFETs, and an input capacitor are contained in the same package.
  • Further, Japanese Patent Application Laid-Open Publication No. 2002-217416 (Patent Document 2) discloses a package structure in which a power MOSFET for high side constituting a DC-DC converter is formed of a horizontal power MOSFET, a power MOSFET for low side is formed of a vertical power MOSFET, and these power MOSFETs are mounted on a common frame.
    • SUMMARY OF THE INVENTION
  • Meanwhile, the current and frequency of a non-insulated DC-DC converter used for a power source circuit of a desktop personal computer, a server, a game machine and others have been increased along with the increasing demands for the current increase in CPU (Central Processing Unit) to be driven and the size reduction of passive components such as a choke coil and an input/output capacitor.
  • However, under the large current and high frequency conditions, there occurs a problem that losses increase due to a main circuit inductance that parasitizes in the main circuit around an input capacitor of a non-insulated DC-DC converter. In particular, when the main circuit inductance that parasitizes in the main circuit around the input capacitor becomes large along with the current increase and frequency increase, the jump voltage at the turn-off of the power MOSFET for high side of the DC-DC converter increases, and as a result, the switching losses are increased, and large losses are caused.
  • In order to reduce the main circuit inductance described above, a structure in which a semiconductor chip on which a power MOSFET for high side is formed and a semiconductor chip on which a power MOSFET for low side is formed are contained in the same package is used. Further, a structure in which a semiconductor chip on which a power MOSFET for high side is formed, a semiconductor chip on which a power MOSFET for low side is formed, and a semiconductor chip on which a driver circuit is formed are contained in the same package is also used. In both cases, the respective semiconductor chips are mounted on respectively different die pads, and the source of the power MOSFET for high side is electrically connected via a bonding wire to the die pad on which the semiconductor chip on which the power MOSFET for low side is formed is mounted. However, in these structures, since the input capacitor is externally disposed, it is not possible to sufficiently reduce the parasitic inductance. Further, since the source of the power MOSFET for high side and the die pads and the source of the power MOSFET for low side and the reference potential are electrically connected by bonding wires, respectively, the reduction of the parasitic inductance is limited.
  • Further, the Patent Document 2 discloses a structure in which a semiconductor chip on which a power MOSFET for high side is formed, a semiconductor chip on which a power MOSFET for low side is formed, a semiconductor chip on which a driver circuit is formed, and an input capacitor Cin are contained in the same package. In this case, the source of the power MOSFET for high side is electrically connected to a wiring of a wiring board via a bonding wire, and the wiring is electrically connected to the drain of the power MOSFET for low side. The source of the power MOSFET for low side is electrically connected via a bonding wire to the output wiring of the wiring board. However, even in such a structure, it is not possible to sufficiently reduce the parasitic inductance because connections are made by bonding wires, and furthermore, the reduction of the parasitic inductance is limited because there is a certain distance between the input capacitor and the respective power MOSFETs.
  • Accordingly, an object of the present invention is to provide a technology capable of reducing the parasitic inductance of the main circuit of a power source circuit.
  • The above and other objects and novel characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.
  • The typical ones of the inventions disclosed in this application will be briefly described as follows.
  • That is, according to the present invention, a field effect transistor of a first semiconductor chip is formed of an n-channel vertical field effect transistor, a field effect transistor of a second semiconductor chip is formed of an n-channel vertical field effect transistor, a surface on which a source electrode of the first semiconductor chip is disposed and a surface on which a drain electrode of the second semiconductor chip is disposed are mounted on the same chip mounting portion and electrically connected to each other, a drain electrode of the first semiconductor chip has a first lead plate connected to an external terminal for supplying input power, and a source electrode of the second semiconductor chip has a second lead plate connected to an external terminal for supplying reference potential.
  • Further, according to the present invention, a field effect transistor of a first semiconductor chip is formed of an n-channel vertical field effect transistor, a field effect transistor of a second semiconductor chip is formed of an n-channel vertical field effect transistor, a surface on which a source electrode of the first semiconductor chip is disposed and a surface on which a drain electrode of the second semiconductor chip is disposed are mounted on the same chip mounting portion and electrically connected to each other, a drain electrode of the first semiconductor chip has a first lead plate connected to an external terminal for supplying input power, and a source electrode of the second semiconductor chip has a second lead plate connected to an external terminal for supplying reference potential, wherein a capacitor electrically connected between the first lead plate and the second lead plate is provided, and in the capacitor, one of a pair of electrodes is connected to the first lead plate and the other of the pair of electrodes is connected to the second lead plate.
  • The effects obtained by typical aspects of the present invention will be briefly described below.
  • That is, according to the present invention, a field effect transistor of a first semiconductor chip is formed of an n-channel vertical field effect transistor, a field effect transistor of a second semiconductor chip is formed of an n-channel vertical field effect transistor, a surface on which a source electrode of the first semiconductor chip is disposed and a surface on which a drain electrode of the second semiconductor chip is disposed are mounted on the same chip mounting portion and electrically connected to each other, a drain electrode of the first semiconductor chip has a first lead plate connected to an external terminal for supplying input power, and a source electrode of the second semiconductor chip has a second lead plate connected to an external terminal for supplying reference potential. By this means, since it is possible to reduce inductance in the wiring between the first and second semiconductor chips, it is possible to reduce the parasitic inductance of the main circuit of a power source circuit.
    • BRIEF DESCRIPTIONS OF THE DRAWINGS
  • FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention;
  • FIG. 2 is a timing chart of the semiconductor device in FIG. 1;
  • FIG. 3 is a plan view showing an inside of a package examined by the inventors of the present invention;
  • FIG. 4 is a cross sectional view taken along the line Y1-Y1 in FIG. 3;
  • FIG. 5 is a plan view showing an inside of a package examined by the inventors of the present invention;
  • FIG. 6 is a cross sectional view taken along the Y2-Y2 in FIG. 5;
  • FIG. 7 is a plan view showing an inside of a package according to Patent Document 2 examined by the inventors of the present invention;
  • FIG. 8 is a plan view showing an inside of a package of a semiconductor device according to an embodiment of the present invention;
  • FIG. 9 is a cross sectional view taken along the line Y3-Y3 in FIG. 8;
  • FIG. 10 is a plan view showing an inside of a package of a semiconductor device according to an embodiment of the present invention;
  • FIG. 11 is a cross sectional view taken along the line Y4-Y4 in FIG. 10;
  • FIG. 12 is a cross sectional view of a semiconductor device according to an embodiment of the present invention;
  • FIG. 13 is a graph showing the relation between main circuit inductance and switching loss for describing the effect of the present invention;
  • FIG. 14 is a graph showing the relation between main circuit inductance and jump voltage for describing the effect of the present invention;
  • FIG. 15A is a diagram for describing the MOS for low side in FIG. 8 and peripheral structure thereof;
  • FIG. 15B is a diagram for describing the MOS for low side in FIG. 8 and peripheral structure thereof;
  • FIG. 15C is a diagram for describing the MOS for low side in FIG. 8 and peripheral structure thereof; and
  • FIG. 15D is a diagram for describing the MOS for low side in FIG. 8 and peripheral structure thereof.
    •  DESCRIPTIONS OF THE PREFERRED EMBODIMENTS
  • In the embodiments described below, the invention will be described in a plurality of sections or embodiments when required as a matter of convenience. However, these sections or embodiments are not irrelevant to each other unless otherwise stated, and the one relates to the entire or a part of the other as a modification example, details, or a supplementary explanation thereof. Also, in the embodiments described below, when referring to the number of elements (including number of pieces, values, amount, range, and the like), the number of the elements is not limited to a specific number unless otherwise stated or except the case where the number is apparently limited to a specific number in principle. The number larger or smaller than the specified number is also applicable. Further, in the embodiments described below, it goes without saying that the components (including element steps) are not always indispensable unless otherwise stated or except the case where the components are apparently indispensable in principle. Similarly, in the embodiments described below, when the shape of the components, positional relation thereof, and the like are mentioned, the substantially approximate and similar shapes and the like are included therein unless otherwise stated or except the case where it can be conceived that they are apparently excluded in principle. The same goes for the numerical value and the range described above. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. The embodiments of the present invention will be described below in detail with reference to the drawings.
    • First Embodiment
  • A semiconductor device according to the first embodiment of the present invention is a non-insulated DC-DC converter used for a power source circuit of, for example, a desktop personal computer, a notebook personal computer, a server, a game machine and others.
  • FIG. 1 shows the circuit diagram of an example of a non-insulated DC-DC converter 1 examined by the inventors of the present invention. The non-insulated DC-DC converter 1 has such elements as a control circuit 2, a driver circuit 3, power MOSFETs (hereinafter, referred to simply as power MOS) QH1 and QL1, an input capacitor Cin, an output capacitor Cout, and a coil L. Meanwhile, D denotes a drain and S denotes a source. Further, L1 to L6 denote parasitic inductances that parasitize in the main circuit of the non-insulated DC-DC converter.
  • The control circuit 2 is a circuit that supplies the signal to control the width of voltage switch on (ON time) of the power MOSs QH1 and QL1 such as a pulse width modulation (PWM) circuit. The output of the control circuit 2 (terminal for control signals) is electrically connected to the input of the driver circuit 3. The output of the driver circuit (first control circuit) 3 is electrically connected to the gate terminal GH of the power MOS QH1 and the gate terminal GL of the power MOS QL1. According to the control signal supplied from the control circuit 2, the driver circuit 3 controls the potentials of the gate terminals GH and GL of the respective power MOSs QH1 and QL1, thereby controlling the operations of the power MOSs QH1 and QL1. Meanwhile, VDIN denotes the input power of the driver circuit 3.
  • The power MOSs QH1 and QL1 are connected in series between a terminal (first power source terminal) ET1 for supplying high potential (first power source potential) VDD of the input power source VIN and a terminal (second power source terminal) ET2 for supplying reference potential (second power source potential) GND. That is, the power MOS QH1 is disposed so that the source and drain paths thereof are connected in series between the terminal ET1 for supplying high potential VDD of the input power source VIN and the output node (output terminal) Lx, and the power MOS QL1 is disposed so that the source and drain paths thereof are connected in series between the output node Lx and the terminal ET2 for supplying ground potential GND. Meanwhile, Dp1 denotes a parasitic diode (internal diode) of the power MOS QH1, and Dp2 denotes a parasitic diode (internal diode) of the power MOS QL1.
  • The power MOS QH1 is a power transistor for high side switch (high potential side: first operation voltage; hereinafter, referred to simply as high side) and has a switch function to store energy in the coil L that supplies electric power to the output of the non-insulated DC-DC converter 1 (input of the load circuit 4). This power MOSFET QH1 is formed of an n-channel vertical field effect transistor. The vertical field effect transistor is an element whose channel is formed in a thickness direction of the semiconductor chip, and it can increase the channel width per unit area more than the horizontal field effect transistor and can reduce ON-resistance. Therefore, it is possible to realize the size reduction of the element and the reduction of the package size.
  • On the other hand, the power MOS (second field effect transistor) QL1 is a power transistor for low side switch (low potential side: second operation voltage; hereinafter, referred to simply as low side), and it is a transistor for rectification of the non-insulated DC-DC converter 1 and has a function to perform rectification by lowering the resistance of the transistor in synchronization with the frequency from the control circuit 2. Similar to the power MOS QH1, this power MOS QL1 is formed of an n-channel vertical power MOS. The reason why the vertical type is used is as follows. That is, as shown in the timing chart of the non-insulated DC-DC converter 1 of FIG. 2, the power MOS QL1 for low side has a longer ON time (time of applying voltage) than the ON time of the power MOS QH1 for high side, and losses by ON resistance appears larger than switching loss. Accordingly, it is advantageous to use the vertical field effect transistor that can increase the channel width per unit area more than the horizontal field effect transistor. In other words, by forming the power MOS QL1 for low side by the vertical field effect transistor, the ON resistance can be lowered, and thus, it is possible to improve the voltage conversion efficiency even if the current flowing in the non-insulated DC-DC converter 1 increases. Meanwhile, in FIG. 2, Ton denotes the pulse width at ON time of the power MOS QH1 for high side, and T denotes the pulse period.
  • The input capacitor Cin is electrically connected to the input power source VIN in FIG. 1 in parallel. This input capacitor Cin is a power source circuit that temporarily stores the energy (electric charge) supplied from the input power source VIN and supplies the stored energy to the main circuit of the non-insulated DC-DC converter 1. In this case, since the input power source VIN is the power source for not only the non-insulated DC-DC converter 1 but also other devices, it is disposed at a position away from the non-insulated DC-DC converter 1, and since the power supply efficiency decreases if power is supplied from the input power source VIN directly to the non-insulated DC-DC converter 1, power is supplied to the input capacitor Cin disposed at a relatively close position to the main circuit of the non-insulated DC-DC converter 1, and then the power is supplied therefrom to the main circuit of the non-insulated DC-DC converter 1. The input power source potential VDD of the input power source VIN is, for example, around 5 to 12 V. Further, the reference potential GND is, for example, lower than the input power source potential and is, for example, ground potential 0 V. Furthermore, the operation frequency of the non-insulated DC-DC converter 1 (period to turn ON and OFF the power MOSs QH1 and QL1) is, for example, 1 MHz.
  • On the wiring that connects the source of the power MOS QH1 and the drain of the power MOS QL1 of the non-insulated DC-DC converter 1, the output node Lx that supplies the output power source potential to the outside is disposed. The output node Lx is electrically connected via the output wiring to the coil L, and further electrically connected via the output wiring to the load circuit 4. A Schottky barrier diode (hereinafter, referred to as SBD) may be electrically connected between the output wiring that connects this output node Lx and the coil L and the terminal for supplying the reference potential GND so as to be in parallel to the above-mentioned power MOS QL1. The SBD is a diode whose forward voltage Vf is lower than that of the parasitic diode Dp2 of the power MOS QL1. In this SBD, the anode thereof is electrically connected to the terminal ET2 for supplying the reference potential GND, and the cathode thereof is electrically connected to the output wiring that connects the output node Lx and the drain of the power MOS QL1. By connecting the SBD in the above-described manner, the voltage drop in dead time when the power MOS QL1 is turned off can be decreased, and thus, the conductivity loss of the diode can be reduced. Further, it is possible to reduce the diode recovery loss because of the reduction in the reverse recovery time (trr).
  • The output capacitor Cout is electrically connected between the output wiring that connects the coil L and the load circuit 4 and the terminal for supplying the reference potential GND. Further, as the load circuit 4, a central processing unit (CPU) or a micro processing unit (MPU) of the above-mentioned electronic device and the like can be exemplified. Iout denotes output current and Vout denotes output voltage.
  • In the circuit described above, the power MOSs QH1 and QL1 are alternately turned ON/OFF in synchronization, thereby converting the power source voltage. That is, when the power MOS QH1 for high side switch is ON, current (first current) I1 flows from the terminal ET1 electrically connected to the drain D of the power MOS QH1 via the power MOS QH1 to the output node Lx, and when the power MOS QH1 for high side switch is OFF, current I2 flows by the back electromotive voltage of the coil L. By turning on the power MOS QL1 for low side switch when this current I2 is flowing, the voltage drop can be reduced. The current I1 is large current of, for example, about 20 A.
  • Meanwhile, in such a non-insulated DC-DC converter 1, along with the increase in current and frequency, the parasitic inductances (L1+L2+L3+L4+L5+L6) that parasitize in the main circuit around the input capacitor Cin become large, and the jump voltage particularly at the time of turn-off of the power MOS QH1 for high side of the non-insulated DC-DC converter 1 increases. As a result, the switching loss increases and large losses are caused.
  • Herein, according to the examinations by the inventors of the present invention, as an example of the package structure for reducing the parasitic inductance, the structure shown in FIG. 3 to FIG. 7 can be exemplified. FIG. 3 is a plan view showing the inside of the package, and FIG. 4 is a cross sectional view taken along the line Y1-Y1 in FIG. 3. In FIG. 3 and FIG. 4, a semiconductor chip 5 a on which the power MOS QH1 for high side and a semiconductor chip 5 b on which the power MOS QL1 for low side are contained in the same sealing body 6. Semiconductor chips 5 a and 5 b are mounted on respectively different die pads 7 a 1 and 7 a 2. The source of the power MOS QH1 for high side is electrically connected via a bonding wire (hereinafter, referred to simply as wire) W to the die pad 7 a 2 on which the power MOS QL1 for low side is mounted.
  • FIG. 5 is a plan view showing the inside of the package, and FIG. 6 is a cross sectional view taken along the line Y2-Y2 in FIG. 5. In FIG. 5 and FIG. 6, in addition to the above-mentioned semiconductor chips 5 a and 5 b, a semiconductor chip 5 c on which the driver circuit 3 is formed is also contained in the same sealing body 6. The semiconductor chip 5 c is mounted on a die pad 7 a 3 different from the die pads 7 a 1 and 7 a 2. Also in this example, the semiconductor chips 5 a and 5 b are mounted on respectively different die pads 7 a 1 and 7 a 2, and the source of the power MOS QH1 for high side is electrically connected via the wire W to the die pad 7 a 2 on which the power MOS QL1 for low side is mounted.
  • Further, FIG. 7 shows the package structure disclosed in the Patent Document 2, in which, in addition to the semiconductor chips 5 a, 5 b, and 5 c, the input capacitor Cin is also contained in the same sealing body 6. In this case, the source of the power MOS QH1 for high side is electrically connected via the wire W to the wiring of a wiring board 50, and the wiring is electrically connected to the drain of the power MOS QL1 for low side. The source of the power MOS QL1 for low side is electrically connected via the wire W to the output wiring of the wiring board 50.
  • However, in the structure shown in FIG. 3 and FIG. 4 and that shown in FIG. 5 and FIG. 6, since the input capacitor Cin is externally disposed, it is not possible to reduce the parasitic inductances L1 and L6. Further, since the source of the power MOS QH1 for high side and the die pad 7 a 2 are electrically connected via the wire W and the source of the power MOS QL1 for low side and the reference potential GND are electrically connected via the wire W, the reduction of the parasitic inductances L3 and L5 is limited.
  • In addition, in the structure in which the semiconductor chips 5 a, 5 b, and 5 c and the input capacitor Cin are contained in the same sealing body 6 as shown in FIG. 7, since they are connected via the wire W, it is not possible to reduce the parasitic inductances L3 and L5, and further, since there is a certain distance between the input capacitor Cin and the respective power MOSs QH1 and QL1, the reduction of the parasitic inductances L1 and L6 is limited.
  • Therefore, in the first embodiment, in order to reduce the parasitic inductances L3 and L4 of the parasitic inductances L1 to L6, the power MOS for high side and the power MOS for low side are mounted on a common die pad (tab, chip mounting portion). Therefore, in the first embodiment, the power MOS for high side of the non-insulated DC-DC converter 1 is formed of an n-channel vertical power MOS, and a flip chip structure is used to connect the source electrode thereof to a die pad.
  • FIG. 8 and FIG. 9 show an example of the package structure according to the first embodiment. FIG. 8 is a plan view showing the inside of the package, and FIG. 9 is a cross sectional view taken along the line Y3-Y3 in FIG. 8. In FIG. 8, the inside of the package is shown in a see-through manner for easy understanding of the structure.
  • Two separately-formed semiconductor chips 5 a and 5 b are mounted on a common die pad 8 b and contained in the package. The n-channel vertical power MOS for high side of the non-insulated DC-DC converter 1 is formed on the semiconductor chip (first semiconductor chip) 5 a. Further, the n-channel vertical power MOS for low side of the non-insulated DC-DC converter 1 is formed on the semiconductor chip (second semiconductor chip) 5 b. A driving IC (Integrated Circuit) 5 c (third semiconductor chip) for driving the gates of the first semiconductor chip and the second semiconductor chip is mounted on the die pad 8 d and is connected via the wire bonding to the die pad 8 b corresponding to the source electrode of the first semiconductor chip 5 a and the pad 9 b corresponding to the gate electrode thereof. Also, the third semiconductor chip is connected to the source electrode 9 c and the gate electrode pad 9 a of the second semiconductor chip via the wire bonding.
  • The drain electrode of the first semiconductor chip is connected via a lead plate 8 c to the external terminal Vin for supplying power, and the source electrode 9 c of the second semiconductor chip is connected via the lead plate 8 a to the external terminal Gnd for supplying reference voltage, and the common die pad 8 b is connected to the external terminal Lx for output.
  • As described above, in the first embodiment, since the MOS for high side and the MOS for low side are mounted on the common die pad, the parasitic inductances L3 and L4 are reduced. Further, since the lead plate is used for the connection between the drain electrode of the MOS for high side and the external terminal and the connection between the source electrode of the MOS for low side and the external terminal, the parasitic inductances L2 and L5 are reduced.
  • Next, the MOS for low side in FIG. 8 and the peripheral structure thereof will be described with reference to FIG. 15.
  • FIG. 15A shows a pattern of the lead frame, in which the bonding pad (high side) 9 b for the gate and the lead plate 8 b for the source are shown. In FIG. 15B, 12 a and 12 b denote structures in an upper layer than the lead frame of FIG. 15A, that is, a gate pad 12 a and a source pad 12 b. FIG. 15C shows a structure in an upper layer than the gate pad 12 a and the source pad 12 b in FIG. 15B, in which the semiconductor chip (power MOS for low side) 5 a is shown. Further, FIG. 15D shows a structure in an upper layer than the semiconductor chip 5 a in FIG. 15C, in which the lead plate (power source voltage) 8 a is shown.
    • Second Embodiment
  • As described above, by the structure according to the first embodiment, it is possible to reduce the inductances L2, L3, L4, and L5 of the wirings shown in FIG. 1. However, in the first embodiment, it is not possible to reduce the parasitic inductance L1 which occurs between the plus terminal of the input capacitor Cin and the drain terminal of the power MOS for high side and the parasitic inductance L6 which occurs between the minus terminal of the input capacitor Cin and the source terminal of the power MOS for low side. The second embodiment has been made in consideration of this, and it enables to reduce the inductances L1 and L6.
  • FIG. 10 and FIG. 11 show an example of the package structure according to the second embodiment. FIG. 10 is a plan view showing the inside of the package, and FIG. 11 is a cross sectional view taken along the line Y4-Y4 in FIG. 10. In FIG. 10, the inside of the package is shown in a see-through manner for easy understanding of the structure.
  • The point where the second embodiment is different from the first embodiment is that an input capacitor 11 is mounted on a surface of the package. A plus electrode 11 a of the input capacitor 11 is connected via a conductive component 11 c to the lead plate 8 a that is electrically connected to the external terminal for supplying input power, and a minus electrode 11 b of the input capacitor 11 is connected via a conductive component 11 d to the lead plate 8 b that is electrically connected to the external terminal for supplying reference potential.
  • Next, the effect of the present embodiment will be described with reference to FIG. 13 and FIG. 14. FIG. 13 shows the wiring inductance of the main circuit in the horizontal axis and the switching loss of the power MOS for high side (first semiconductor) in the vertical axis. The wiring inductance of the main circuit is equivalent to the total value of L1 to L6 in FIG. 1. As the main circuit inductance decreases, the switching loss lowers, but when the main circuit inductance reaches 1 nH or less, the switching loss increases. The conventional example is the measurement result of the case using the package in FIG. 5. Since the inductance of the present embodiment is smaller than that of the conventional example, it can be understood that the switching loss can be decreased. When the switching loss is small, it is possible to eliminate cooling parts such as a heat sink and the like, which makes it possible to reduce the size of a power source. In addition, under the conditions that the loss is fixed, the switching frequency can be improved in the present embodiment. Therefore, it is possible to reduce the size of an output filter consisting of an inductor and a capacitor.
  • FIG. 14 shows the wiring inductance of the main circuit in the horizontal axis and jump voltage between the source and the drain of the MOS for high side at the time of switching in the vertical axis. As the main circuit inductance is smaller, the jump voltage becomes smaller. The conventional example is the measurement result of the case using the package in FIG. 5. Since the inductance of the present embodiment is smaller than that of the conventional example, the jump voltage decreases. When the jump voltage is low, conduction noise and radiation noise become small, and therefore, it is possible to prevent the malfunction of other semiconductor devices and electronic devices.
    • Third Embodiment
  • As described above, by the structure according to the second embodiment, it is possible to reduce the inductances L1 to L6 of the wirings shown in FIG. 1. However, in the second embodiment, since the capacitor is mounted on the package surface, there is a problem that the heat resistance of the surface is high. The third embodiment has been made in consideration of this, and it enables to reduce the heat resistance of the surface.
  • FIG. 12 is a diagram for describing the third embodiment, and the point different from FIG. 11 is that the lead plates 8 a and 8 b are exposed on the package surface. The plus electrode 11 a of the input capacitor 11 is connected to the lead plate 8 a that is electrically connected to the external terminal for supplying input power, and the minus electrode 11 b of the input capacitor 11 is connected to the lead plate 8 b that is electrically connected to the external terminal for supplying reference potential.
  • In the above descriptions, the cases where the invention made by the inventors of the present invention is applied to the power source unit of a CPU and a DSP which is the background thereof have been described. However, the application of the present invention is not limited to this, and the present invention can be applied to various devices. For example, it may be applied to a power source unit of other circuit.
  • The present invention can be applied to a semiconductor device and an electronic device.

Claims (4)

1. A semiconductor device comprising:
an external terminal for supplying input power disposed in a sealing body;
an external terminal for supplying reference potential disposed in the sealing body;
an external terminal for output disposed in the sealing body;
a first semiconductor chip sealed in the sealing body;
a second semiconductor chip sealed in the sealing body;
a drain electrode of the first semiconductor chip being electrically connected to the external terminal for supplying input power,
a source electrode of the second semiconductor chip being electrically connected to the external terminal for supplying reference potential,
a source electrode of the first semiconductor chip and a drain electrode of the second semiconductor chip being electrically connected to the external terminal for output, and
a capacitor electrically connected to the external terminal for supplying input power and the external terminal for supplying reference potential,
wherein the drain electrode of the first semiconductor chip and the source electrode of the second semiconductor chip are disposed in the same planar direction, and
the capacitor is disposed on the drain electrode of the first semiconductor chip and the source electrode of the second semiconductor chip.
2. The semiconductor device according to claim 1,
wherein the first semiconductor chip, the second semiconductor chip, and the capacitor are sealed by sealant.
3. The semiconductor device according to claim 2,
wherein a driver circuit which drives a gate electrode of the first semiconductor chip and a gate electrode of the second semiconductor chip is provided, and
the driver circuit is sealed in the sealing body together with the first semiconductor chip and the second semiconductor chip.
4. The semiconductor device according to claim 1,
wherein a Schottky barrier diode electrically connected between the drain electrode of the second semiconductor chip and the source electrode of the second semiconductor chip is provided.
US13/192,584 2006-05-30 2011-07-28 Semiconductor Device with Circuit for Reduced Parasitic Inductance Abandoned US20110278655A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/192,584 US20110278655A1 (en) 2006-05-30 2011-07-28 Semiconductor Device with Circuit for Reduced Parasitic Inductance

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2006149489 2006-05-30
JP2006-149489 2006-05-30
US11/809,023 US7687885B2 (en) 2006-05-30 2007-05-30 Semiconductor device with reduced parasitic inductance
US12/721,201 US8008699B2 (en) 2006-05-30 2010-03-10 Semiconductor device with circuit for reduced parasitic inductance
US13/192,584 US20110278655A1 (en) 2006-05-30 2011-07-28 Semiconductor Device with Circuit for Reduced Parasitic Inductance

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/721,201 Continuation US8008699B2 (en) 2006-05-30 2010-03-10 Semiconductor device with circuit for reduced parasitic inductance

Publications (1)

Publication Number Publication Date
US20110278655A1 true US20110278655A1 (en) 2011-11-17

Family

ID=38789070

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/809,023 Active US7687885B2 (en) 2006-05-30 2007-05-30 Semiconductor device with reduced parasitic inductance
US12/721,201 Expired - Fee Related US8008699B2 (en) 2006-05-30 2010-03-10 Semiconductor device with circuit for reduced parasitic inductance
US13/192,584 Abandoned US20110278655A1 (en) 2006-05-30 2011-07-28 Semiconductor Device with Circuit for Reduced Parasitic Inductance

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US11/809,023 Active US7687885B2 (en) 2006-05-30 2007-05-30 Semiconductor device with reduced parasitic inductance
US12/721,201 Expired - Fee Related US8008699B2 (en) 2006-05-30 2010-03-10 Semiconductor device with circuit for reduced parasitic inductance

Country Status (2)

Country Link
US (3) US7687885B2 (en)
TW (1) TW200812066A (en)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4875380B2 (en) * 2006-02-24 2012-02-15 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4916745B2 (en) * 2006-03-28 2012-04-18 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US7687885B2 (en) * 2006-05-30 2010-03-30 Renesas Technology Corp. Semiconductor device with reduced parasitic inductance
JP4405529B2 (en) * 2007-05-15 2010-01-27 株式会社東芝 Semiconductor device
ITTO20070392A1 (en) * 2007-06-05 2008-12-06 St Microelectronics Srl POWER BALANCING DEVICE INCLUDING COLUMN STRUCTURES AND REDUCED RESISTANCE
US8581345B2 (en) * 2007-06-05 2013-11-12 Stmicroelectronics S.R.L. Charge-balance power device comprising columnar structures and having reduced resistance, and method and system of same
US8102668B2 (en) * 2008-05-06 2012-01-24 International Rectifier Corporation Semiconductor device package with internal device protection
US8222695B2 (en) 2009-06-30 2012-07-17 Semiconductor Components Industries, Llc Process of forming an electronic device including an integrated circuit with transistors coupled to each other
US8124468B2 (en) 2009-06-30 2012-02-28 Semiconductor Components Industries, Llc Process of forming an electronic device including a well region
US8169088B2 (en) * 2009-07-02 2012-05-01 Monolithic Power Systems, Inc. Power converter integrated circuit floor plan and package
US9257375B2 (en) 2009-07-31 2016-02-09 Alpha and Omega Semiconductor Inc. Multi-die semiconductor package
US8164199B2 (en) * 2009-07-31 2012-04-24 Alpha and Omega Semiconductor Incorporation Multi-die package
JP5401292B2 (en) 2009-12-15 2014-01-29 ルネサスエレクトロニクス株式会社 Semiconductor device and communication method
US8298886B2 (en) * 2010-02-08 2012-10-30 Semiconductor Components Industries, Llc Electronic device including doped regions between channel and drain regions and a process of forming the same
US8299560B2 (en) * 2010-02-08 2012-10-30 Semiconductor Components Industries, Llc Electronic device including a buried insulating layer and a vertical conductive structure extending therethrough and a process of forming the same
US8389369B2 (en) * 2010-02-08 2013-03-05 Semiconductor Components Industries, Llc Electronic device including a doped region disposed under and having a higher dopant concentration than a channel region and a process of forming the same
CN102169873B (en) * 2010-02-25 2013-12-11 万国半导体有限公司 Semiconductor packing structure applied to power switcher circuit
JP4985810B2 (en) * 2010-03-23 2012-07-25 サンケン電気株式会社 Semiconductor device
US8582317B2 (en) 2010-05-26 2013-11-12 Semiconductor Components Industries, Llc Method for manufacturing a semiconductor component and structure therefor
JP5525917B2 (en) 2010-05-27 2014-06-18 ローム株式会社 Electronic circuit
MY163694A (en) 2010-06-02 2017-10-13 Semiconductor Components Ind Llc Semiconductor component and method of manufacture
US8921986B2 (en) * 2013-03-15 2014-12-30 Microchip Technology Incorporated Insulated bump bonding
US9166487B2 (en) * 2013-12-06 2015-10-20 Zentel Electronics Corp. Package structure integrating a start-up component, a controller, and a power switch
CN104716128B (en) 2013-12-16 2019-11-22 台达电子企业管理（上海）有限公司 The manufacturing method of power module, supply convertor and power module
US10050025B2 (en) 2016-02-09 2018-08-14 Texas Instruments Incorporated Power converter monolithically integrating transistors, carrier, and components
JP6689708B2 (en) * 2016-08-10 2020-04-28 ルネサスエレクトロニクス株式会社 Electronic device
DE102016122162B4 (en) 2016-11-17 2022-05-05 Infineon Technologies Ag SEMICONDUCTOR DEVICE WITH METALLIZATION STRUCTURES ON OPPOSITE SIDES OF A SEMICONDUCTOR REGION, SEMICONDUCTOR SWITCHING ARRANGEMENT AND METHOD
CN108282092B (en) * 2017-01-05 2020-08-14 罗姆股份有限公司 Rectifier IC and insulated switching power supply using the same
TWI664701B (en) 2018-07-04 2019-07-01 朋程科技股份有限公司 Package structure of power device
CN115101498A (en) * 2022-05-18 2022-09-23 华为数字能源技术有限公司 Power module, power supply system, vehicle and photovoltaic system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7145224B2 (en) * 2004-01-28 2006-12-05 Renesas Technology Corp. Semiconductor device
US7554181B2 (en) * 2004-03-31 2009-06-30 Renesas Technology Corp. Semiconductor device with non-overlapping chip mounting sections
US8008699B2 (en) * 2006-05-30 2011-08-30 Renesas Electronics Corporation Semiconductor device with circuit for reduced parasitic inductance

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049972A (en) * 1988-01-29 1991-09-17 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
WO2001072092A1 (en) 2000-03-22 2001-09-27 International Rectifier Corporation Gate driver multi-chip module
JP2002217416A (en) 2001-01-16 2002-08-02 Hitachi Ltd Semiconductor device
JP2003197750A (en) * 2001-12-21 2003-07-11 Mitsubishi Electric Corp Semiconductor device
US6940724B2 (en) * 2003-04-24 2005-09-06 Power-One Limited DC-DC converter implemented in a land grid array package
JP4658481B2 (en) * 2004-01-16 2011-03-23 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4477952B2 (en) * 2004-07-09 2010-06-09 株式会社ルネサステクノロジ Semiconductor device, DC / DC converter and power supply system
JP4445351B2 (en) * 2004-08-31 2010-04-07 株式会社東芝 Semiconductor module
JP4426955B2 (en) * 2004-11-30 2010-03-03 株式会社ルネサステクノロジ Semiconductor device
JP5291864B2 (en) * 2006-02-21 2013-09-18 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device for DC / DC converter and semiconductor device for DC / DC converter
JP4916745B2 (en) * 2006-03-28 2012-04-18 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7145224B2 (en) * 2004-01-28 2006-12-05 Renesas Technology Corp. Semiconductor device
USRE41869E1 (en) * 2004-01-28 2010-10-26 Renesas Electronics Corp. Semiconductor device
US7554181B2 (en) * 2004-03-31 2009-06-30 Renesas Technology Corp. Semiconductor device with non-overlapping chip mounting sections
US8013430B2 (en) * 2004-03-31 2011-09-06 Renesas Electronics Corporation Semiconductor device including DC-DC converter
US8008699B2 (en) * 2006-05-30 2011-08-30 Renesas Electronics Corporation Semiconductor device with circuit for reduced parasitic inductance

Also Published As

Publication number Publication date
US20100176430A1 (en) 2010-07-15
TWI360218B (en) 2012-03-11
US8008699B2 (en) 2011-08-30
US7687885B2 (en) 2010-03-30
TW200812066A (en) 2008-03-01
US20070278516A1 (en) 2007-12-06

Similar Documents

Publication Publication Date Title
US8008699B2 (en) Semiconductor device with circuit for reduced parasitic inductance
US10749520B2 (en) Power circuit and power module using MISFET having control circuit disposed between gate and source
US6700793B2 (en) Semiconductor device
US8044520B2 (en) Semiconductor device
US7659144B2 (en) Semiconductor device and manufacturing the same
US8344459B2 (en) Semiconductor device
US8203380B2 (en) Semiconductor device
KR101086751B1 (en) Semiconductor device and power supply system
US8067979B2 (en) Semiconductor device and power supply device using the same
US20100171543A1 (en) Packaged power switching device
US20110181255A1 (en) Semiconductor device and power supply unit using the same
JP2006216940A (en) Semiconductor device
US11990455B2 (en) Semiconductor device
JP5191689B2 (en) Semiconductor device
JP5412559B2 (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION