WO2014202282A1 - Circuit board - Google Patents

Circuit board Download PDF

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Publication number
WO2014202282A1
WO2014202282A1 PCT/EP2014/059632 EP2014059632W WO2014202282A1 WO 2014202282 A1 WO2014202282 A1 WO 2014202282A1 EP 2014059632 W EP2014059632 W EP 2014059632W WO 2014202282 A1 WO2014202282 A1 WO 2014202282A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
electronic components
printed circuit
conductor
connection
Prior art date
Application number
PCT/EP2014/059632
Other languages
German (de)
French (fr)
Inventor
Michael Pechtold
Thomas Hofmann
Johannes Bock
Original Assignee
Conti Temic Microelectronic Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conti Temic Microelectronic Gmbh filed Critical Conti Temic Microelectronic Gmbh
Publication of WO2014202282A1 publication Critical patent/WO2014202282A1/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4697Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251Disposition
    • H01L2224/2518Disposition being disposed on at least two different sides of the body, e.g. dual array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/0243Printed circuits associated with mounted high frequency components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/025Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10166Transistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10439Position of a single component
    • H05K2201/10477Inverted
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10522Adjacent components

Definitions

  • the invention relates to a circuit carrier, such as a printed circuit board, with inner and outer conductor tracks and at least two electronic components. Furthermore, the invention relates to a method for producing a printed circuit board.
  • Circuit boards as circuit carriers of electronic circuits and components, such as control devices, sensors, in the
  • FIG. 1 For a better overview, the illustration of a single MOSFET can be seen in FIG.
  • Such an equidirectional orientation of the transistors 4, 5 in the circuit board 1 in the interconnection of this to a semiconductor bridge H has the disadvantage that the upper source terminal 4b of a transistor 4 to the lower gate terminal 5c of other transistor 5 only by means of a compound 8 of the upper surface side Ol with the lower surface side 02 (for example in the form of a
  • the transistors 4 and 5 are connected via further leads 11 to the terminals 4d, 5d in the upper conductor tracks 2.
  • the invention has for its object to provide a very compact circuit board with at least two electronic components with the shortest possible links. Moreover, it is an object of the invention to provide a method for producing such a printed circuit board.
  • the printed circuit board according to the invention comprises inner and outer conductor tracks, which are arranged on at least one conductor layer, and at least two internal, electronic components whose connection pins are connected to one of the conductor tracks, wherein the at least two electronic components are arranged in the circuit board in that their connection pins to be connected to one another are directed in the direction of a surface side of the printed circuit board.
  • the known from the prior art vias and long links of the electronic components can be significantly reduced or even avoided.
  • the electrical paths or links are shorter by "flipping" one of the two electronic components, such as a transistor
  • the interconnection of the electronic components is on the same board level ("ply") and / or on the same surface side of the board ⁇ terplatte possible.
  • an embodiment of the invention provides that further connection pins of the at least two electronic components to be connected to one another, in particular transistors of a bridge circuit, by means of a component or a component, such as a ceramic capacitor, from another circuit part, eg Supply voltage, are decoupled.
  • the connection pins to be decoupled and the connection pins of the at least two electronic components to be directly connected to one another on opposite surface sides of the circuit board are decoupled or connected. This allows a simple and fast assembly and contacting during manufacture.
  • the at least two electronic components are each arranged in an associated molded cavity and are electrically connected to conductor tracks of at least one conductor layer, wherein the connection pins of the two electronic components to be connected to one another are connected in a conductor layer to a conductor track.
  • the electronic components are spaced from each other.
  • the respective connection pin of the electronic component (s) is designed as a bonding connection, which branches off in the manner of an arm from the associated electronic component and whose free end is contacted with one of the conductor tracks.
  • the connection pins are contacted in particular in connection with several Lei ⁇ terbahnen in a conductor layer with the conductor tracks, in order to avoid plated-through holes.
  • At least one carrier layer in particular a copper carrier above and / or below the electronic Be arranged component.
  • a carrier layer formed of copper can serve as a conductor track and / or connection element, whereby the electrical connection links are further reduced.
  • the inventive method for producing a printed circuit board with internal and / or external conductor tracks and at least two internal electronic components provides that in the circuit board for each electronic component introduced a cavity, in particular lasered, and the electronic components in this cavity can be arranged such that their connection pins to be connected together are directed in the direction of a surface side of the circuit board and that these connecting pins to be connected to one of the conductor tracks of a conductor layer are connected and fixed together and then optionally the cavities with the positioned therein and electrically connected electronic components.
  • Printed circuit board connected to conductor tracks of a conductor layer and decoupled by means of a component between these interconnects.
  • the method is particularly simple and inexpensive and avoids vias.
  • FIG. 4 to 9 show schematically different sectional views.
  • the interconnects 2 ⁇ , 3 ⁇ are formed as copper surfaces or tracks, layers and serve the electrical connection of at least two electronic components 4 ⁇ and 5 ⁇ .
  • the electronic components 4 ⁇ and 5 ⁇ are inside lying in the circuit board 1 ⁇ in ⁇ tegrated.
  • further electronic components not shown in detail may be arranged inside and / or outside.
  • the printed circuit board 1 ⁇ may be formed as a single-layer or multi- layered printed circuit board with inner and / or outer conductor tracks 2 ⁇ and 3 ⁇ .
  • the electronic components 4 ⁇ , 5 ⁇ may be Halbleitererbauele ⁇ elements, such as transistors, power transistors, sensors, diodes, capacitors and / or control devices.
  • the electronic components 4 ⁇ , 5 for connecting the two internal electronic components 4 ⁇ , 5 in particular their connection pins 4a x to 4c 5a ⁇ to 5c with the outer conductor tracks 2 ⁇ , 3 in particular with terminals 4d 4e 5e 5d x in the outer tracks 2 ⁇ , 3 are inner conductor tracks 10 or leads 11 ⁇ provided.
  • the two internal electronic components 4 ⁇ and 5 ⁇ are in the embodiment of Figure 4 transistors which are connected to a Half bridge ⁇ ⁇ by means of the outer conductor tracks 2 ⁇ , 3 ⁇ and the inner leads 11 ⁇ are connected, as shown by the circuit in Figure 5.
  • the transistors are power transistors, in particular so-called MOSFETs.
  • connection pins 4b ⁇ and 5c ⁇ to be electrically connected are by means of the inner lead 11 ⁇ or an electrically conductive layer 6, in particular an electrically conductive adhesive, with the relevant terminals 4e ⁇ or 5f ⁇ in the conductor 3 ⁇ of a conductor layer L2 electrically connected.
  • the electrically conductive layer 6 ⁇ serves the material-conclusive attachment of the respective electronic component 4 ⁇ , 5 ⁇ on the copper layer of the conductor 2 ⁇ or 3 ⁇ .
  • the electronic components 4 5 ⁇ may be integrated in the circuit substrate or circuit board 1 ⁇ both as packaged as well as a "bare the" components.
  • Figure 6 shows in detail the connection of the connecting pins 4c ⁇ and 5b ⁇ of at least two electronic components 4 ⁇ or 5 ⁇ by means of the component 9 ⁇ or a decoupling element, in ⁇ particular of a capacitor on the outside of the surface ⁇ side Ol ⁇ on the associated terminals 4f ⁇ and 5f ⁇ of upper tracks 2 ⁇ in the one conductor layer LI is attached by means of an electrically conductive layer 6 in particular a elekt ⁇ driven conductive adhesive.
  • connection pins 4c ⁇ and 5b ⁇ to be decoupled and their terminals 4f ⁇ and 5e ⁇ in the upper interconnects 2 ⁇ and the connection pins 4b ⁇ and 5c ⁇ and their interconnected directly to one another Terminals 4e ⁇ and 5f x arranged on opposite surface sides of Ol ⁇ and 02 ⁇ of the circuit board 1 ⁇ .
  • the following component carrier is in particular at least one conductor layer, which is arranged above and / or below the electronic component 4 ⁇ and 5 ⁇ and at least one of the interconnects 2 3 ⁇ or 10 and one of the adjacent printed circuit board insulating LPl to LPm is formed.
  • Figure 7 shows an embodiment for a multilayer printed circuit board 1 ⁇ having a plurality of insulating layers LPL to LPm and a plurality of outer strip conductors 2 ⁇ 3 ⁇ and internal interconnects 10, in particular so-called copper intermediate layers in multiple conductor layers LI to Ln.
  • the at least two internal electronic components 4 5 ⁇ are integrated into the second insulating layer LP2.
  • the electronic components 4 ⁇ and 5 ⁇ are arranged spaced from each other.
  • connection pin 4a ⁇ to 4c ⁇ and 5a ⁇ to 5c ⁇ of the electronic components 4 ⁇ and 5 ⁇ is formed as a bond connection, which in the manner of an arm of the associated electronic component 4 ⁇ and 5 ⁇ goes off and whose free end is contacted with one of the conductor tracks 2 ⁇ , 3 ⁇ or 10.
  • the electronic components 4 ⁇ , 5 ⁇ on a component carrier for example a copper carrier
  • the component carrier is aligned and pressed "face up” or “face down” during the laying / stacking of the conductor layers LI to Lm and the insulating layers LP1 to LPm.
  • the component carrier is contacted by drilling and etching processes using micro-vias.
  • the electronic components 4 ⁇ , 5 ⁇ be anorialiert also by drilling and etching processes by micro-vias (supply lines 11 and ⁇ connections 4d x to 4f ⁇ and 5d x to 5f ⁇ .
  • Figure 8 shows an alternative embodiment for a multilayer printed circuit board 1 ⁇ .
  • the at least two internal electronic components 4 5 ⁇ are integrated into the second conductor layer L2.
  • the electronic components 4 ⁇ and 5 ⁇ are introduced into an associated cavity K of a component carrier and assembled and fixed electrically conductive, for example by soldering, sintering, Leitkleben.
  • the component carrier is aligned and pressed "face up” or “face down” when laying / stacking the conductor layers LI to Ln and the insulating layers LP1 to LPm.
  • the at least two electronic components 4 ⁇ and 5 ⁇ may be arranged in each case in an associated molded cavity K and electrically connected to inner and / or outer conductor tracks 2 ⁇ , 3 ⁇ and 10 at least one conductor layer LI to Ln.
  • the connection pins 4b ⁇ and 5c ⁇ of the two electronic components 4 ⁇ and 5 ⁇ to be connected to one another are connected in a conductor layer L3 to a conductor track 4e ⁇ .
  • the exemplary embodiment according to FIG. 8 has the advantage over the exemplary embodiment according to FIG. 7 that no openings / "windows" in the laminate of the insulating layers LP1 to LPm in the area of the electronic components 4 are present when the prepreg layers or insulating layers LP1 to LPm are laid ⁇ , 5, for example, a chip must be.
  • the disadvantage is that the components or electronic components 4 ⁇ , 5 ⁇ in the embodiment of Figure 8 in a cavity K of one of the inner conductor tracks 10 of the respective conductor layer L2 and thus the copper must be assembled.
  • FIG. 9 shows a further alternative exemplary embodiment of a multilayer printed circuit board 1 ⁇ with three insulating layers LP1 to LP3, of which two insulating layers LP1 and LP2 directly adjoin each other without intermediate conductor tracks, and with inner and outer conductor tracks 2 3 10 in three conductor layers LI to L3 are connected.
  • an electrically insulating adhesive 7 or other suitable electrically insulating material in the manner of a layer ordered on ⁇ .
  • the electronic components 4 ⁇ , 5 ⁇ are glued "face up” or “face down” on a Cu carrier film as a component carrier.
  • the structure of the inner layers and thus the iso ⁇ lierlagen LP1 and LP2 are laid and pressed.
  • the core is drilled at the contact points and by chemical processes, the micro-via connections between the inner layers, the insulating layers LP1 to LP2 and the components 4 ⁇ , 5 ⁇ (top and bottom) generated.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention relates to a circuit board (1'), comprising internal and external conducting tracks (2', 3', 10), which are arranged on at least one conducting layer (L1 to Ln), and comprising at least two internal electronic components (4', 5'), which are connected to one of the conducting tracks (2', 3', 10) by means of at least one connection pin (4a' to 4c', 5a' to 5c'), wherein the at least two electronic components (4', 5') are arranged in the circuit board (1') in such a way that the connection pins (4a' to 4c', 5a' to 5c') thereof to be connected to each other are directed in the direction of a surface side (O1' or O2') of the circuit board (1').

Description

Beschreibung Leiterplatte Description printed circuit board
Die Erfindung betrifft einen Schaltungsträger, wie eine Lei- terplatte, mit innen und außen liegenden Leiterbahnen und mindestens zwei elektronischen Bauteilen. Des Weiteren betrifft die Erfindung ein Verfahren zur Herstellung einer Leiterplatte.  The invention relates to a circuit carrier, such as a printed circuit board, with inner and outer conductor tracks and at least two electronic components. Furthermore, the invention relates to a method for producing a printed circuit board.
Leiterplatten als Schaltungsträger von elektronischen Schal- tungen und Bauteilen, wie Steuergeräte, Sensoren, die imCircuit boards as circuit carriers of electronic circuits and components, such as control devices, sensors, in the
Allgemeinen von einem Gehäuse umgeben sind, sind hinlänglich bekannt. Die Bestückung und Integration von verschiedenen gehäusten Bauteilen, zum Beispiel Hall-Sensoren, Beschleunigungssensoren, erfolgt üblicherweise zwischen Außenlagen oder Oberflächen eines Schaltungsträgers oder einer Leiterplatte durch unterschiedliche sogenannte „Surface Mounted" Techno¬ logien und „Embedding"-Technologien, die aus der Leiterplattentechnik bekannt sind. Üblicherweise werden derzeit alle elektronischen Bauteile durch die „Embedding" Technologie gleich orientiert integriert. Generally surrounded by a housing, are well known. The assembly and integration of different packaged components, such as Hall sensors, acceleration sensors, is usually between outer layers or surfaces of a circuit board or a printed circuit board by means of different so-called "surface mounted" Techno ¬ gies and "Embedding" technologies that are known from the printed circuit board technology are. Usually, all electronic components are currently integrated in the same way through the "embedding" technology.
Figuren 1 bis 3 zum Stand der Technik zeigt eine Leiterplatte 1, mit Leiterbahnen 2 und 3, wobei die Leiterbahnen 2 (= obere Leiterbahnen 2) auf einer Oberflächenseite Ol und die anderen Leiterbahnen 3 (= untere Leiterbahnen 3) auf der gegenüberliegenden Oberflächenseite 02 der Leiterplatte 1 angeordnet sind . Die Leiterplatte 1 ist mit zwei gleich orientierten Transis¬ toren 4 und 5, insbesondere Leistungstransistoren, bestückt, die insbesondere als eine Halbbrücke H geschaltet sind, wie in Figur 1 gezeigt. Dabei weist ein Drain-Anschluss 4c, 5c (=D1, D2) aller in die Leiterplatte 1 zu integrierender Transistoren 4, 5 (Leistungstransistoren) auf eine Oberflächenseite 02 (zumFigures 1 to 3 to the prior art shows a circuit board 1, with tracks 2 and 3, wherein the tracks 2 (= upper tracks 2) on one surface side Ol and the other tracks 3 (= lower tracks 3) on the opposite surface side 02 of Printed circuit board 1 are arranged. The circuit board 1 is equipped with two identically oriented Transis ¬ motors 4 and 5, in particular power transistors, which in particular are connected as a half-bridge H, as shown in FIG. 1 In this case, has a drain terminal 4c, 5c (= D1, D2) of all to be integrated in the circuit board 1 transistors 4, 5 (power transistors) on a surface side 02 (for
Beispiel nach unten), während ein Source-Anschluss 4b, 5b (Sl, S2) und ein Gate-Anschluss 4a, 5a (Gl, G2) der Transistoren 4, 5 (Leistungstransistoren) auf die andere, gegenüberliegende Oberflächenseite Ol weist (zum Beispiel nach oben) . Example below), while a source terminal 4b, 5b (Sl, S2) and a gate terminal 4a, 5a (G1, G2) of the transistors 4, 5 (power transistors) to the other, opposite surface side Ol has (for example, up).
Zur besseren Übersicht ist in Figur 2 die Darstellung eines einzelnen MOSFETs zu sehen. For a better overview, the illustration of a single MOSFET can be seen in FIG.
Eine derartige gleichsinnige Orientierung der Transistoren 4, 5 in die Leiterplatte 1 hat bei der Verschaltung dieser zu einer Halbleiterbrücke H (siehe Figuren 1 und 3) den Nachteil, dass der obere Source-Anschluss 4b des einen Transistors 4 mit demunteren Gate-Anschluss 5c des anderen Transistors 5 nur mit Hilfe einer Verbindung 8 der oberen Oberflächenseite Ol mit der unteren Oberflächenseite 02 (zum Beispiel in Form einer Such an equidirectional orientation of the transistors 4, 5 in the circuit board 1 in the interconnection of this to a semiconductor bridge H (see Figures 1 and 3) has the disadvantage that the upper source terminal 4b of a transistor 4 to the lower gate terminal 5c of other transistor 5 only by means of a compound 8 of the upper surface side Ol with the lower surface side 02 (for example in the form of a
Durchkontaktierung) bewerkstelligt werden kann. Through-hole) can be accomplished.
Das bedeutet eine verlängerte Strecke zwischen den beiden Transistoren 4 und 5 und damit einen höheren ohmschen Widerstand und eine höhere Induktivität der Verbindungsstrecke, die nicht nur von inneren Zuleitungen 11 zu Anschlüssen 4e, 5e, 5f zur Durchkontaktierung herrühren, sondern vor allem auch durch die Durchkontaktierung von Anschluss 4e in der oberen Leiterbahn 2 zum Anschluss 5f in der unteren Leiterbahn 3 und deren Verbindung 8 selbst. Die Transistoren 4 und 5 sind über weitere Zuleitungen 11 mit den Anschlüssen 4d, 5d in den oberen Lei- terbahnen 2 verbunden. This means an extended distance between the two transistors 4 and 5 and thus a higher ohmic resistance and a higher inductance of the connecting path, which not only come from inner leads 11 to terminals 4e, 5e, 5f for via, but especially through the via from terminal 4e in the upper conductor 2 to the terminal 5f in the lower conductor 3 and their connection 8 itself. The transistors 4 and 5 are connected via further leads 11 to the terminals 4d, 5d in the upper conductor tracks 2.
Der Erfindung liegt die Aufgabe zugrunde, eine möglichst kompakte Leiterplatte mit mindestens zwei elektronischen Bauteilen bei möglichst kurzen Verbindungsstrecken anzugeben. Darüber hinaus ist es Aufgabe der Erfindung, ein Verfahren zur Herstellung einer solchen Leiterplatte anzugeben. The invention has for its object to provide a very compact circuit board with at least two electronic components with the shortest possible links. Moreover, it is an object of the invention to provide a method for producing such a printed circuit board.
Die Aufgabe wird erfindungsgemäß durch die im Patentanspruch 1 angegebenen Merkmale gelöst. Hinsichtlich des Verfahrens wird die Aufgabe erfindungsgemäß durch die im Patentanspruch 8 angegebenen Merkmale gelöst. Vorteilhafte Weiterbildungen der Erfindung sind Gegenstand der Unteransprüche . The object is achieved by the features specified in claim 1. With regard to the method, the object is achieved by the features specified in claim 8. Advantageous developments of the invention are the subject of the dependent claims.
Die erfindungsgemäße Leiterplatte umfasst innen und außen liegende Leiterbahnen, die auf wenigstens einer Leiterlage angeordnet sind, sowie mindestens zwei innen liegende, elektronische Bauteile, deren Anschluss-Pins mit einer der Leiterbahnen verbunden sind, wobei die mindestens zwei elektronischen Bauteile derart in der Leiterplatte angeordnet sind, dass deren miteinander zu verbindende Anschluss-Pins in Richtung einer Oberflächenseite der Leiterplatte gerichtet sind. The printed circuit board according to the invention comprises inner and outer conductor tracks, which are arranged on at least one conductor layer, and at least two internal, electronic components whose connection pins are connected to one of the conductor tracks, wherein the at least two electronic components are arranged in the circuit board in that their connection pins to be connected to one another are directed in the direction of a surface side of the printed circuit board.
Die aus dem Stand der Technik bekannten Durchkontaktierungen und lange Verbindungsstrecken der elektronischen Bauteile können deutlich reduziert oder gar vermieden werden. Insbesondere sind die elektrischen Pfade oder Verbindungsstrecken durch ein „Umdrehen" eines der beiden elektronischen Bauteile, wie eines Transistors, kürzer. Darüber hinaus ist die Verschaltung der elektronischen Bauteile auf der gleichen Leiterplattenebene („Lage") und/oder auf der gleichen Oberflächenseite der Lei¬ terplatte möglich. The known from the prior art vias and long links of the electronic components can be significantly reduced or even avoided. In particular, the electrical paths or links are shorter by "flipping" one of the two electronic components, such as a transistor In addition, the interconnection of the electronic components is on the same board level ("ply") and / or on the same surface side of the board ¬ terplatte possible.
Durch Verkürzung der elektrischen Verbindungsstrecken werden die ohmschen Widerstände und Induktivitäten in der Verbindung der beiden elektronischen Bauteile, wie Transistoren, zueinander reduziert. Dies wiederum führt zu geringeren Verlustleistungen und besserem Schaltverhalten in EMV-Hinsicht . By shortening the electrical connection distances, the ohmic resistances and inductances in the connection of the two electronic components, such as transistors, are reduced to one another. This in turn leads to lower power losses and better switching behavior in EMC terms.
Ein weiterer Vorteil dieser Anordnung ergibt sich im Fall einer Brückenschaltung zweier Transistoren. Nachdem durch die Umkehrung des einen Transistors die Spannungsanschlüsse auf einer Oberflächenseite der Leiterplatte zu liegen kommen, kann auf dieser Oberflächenseite auch sehr niederimpedant und kurz ein oder mehrere Keramikkondensatoren zur Entkopplung des Brü- ckenkreises von der Versorgungsspannung angeschlossen werden, wodurch solche Bauteile im Allgemeinen kleiner und billiger gewählt werden können und sowohl die EMV als auch die Performance der Brücke verbessert werden kann. Mit anderen Worten: Eine Ausführungsform der Erfindung sieht vor, dass weitere miteinander zu verbindende Anschluss-Pins der mindestens zwei elektronischen Bauteile, insbesondere Tran- sistoren einer Brückenschaltung, mittels eines Bauteils oder eines Bauteils, wie eines Keramikkondensators, von einem anderen Schaltungsteil, z.B. einer Versorgungsspannung, entkoppelt sind . In einer weiteren Ausführungsform sind die zu entkoppelnden Anschluss-Pins und die miteinander direkt zu verbindenden Anschluss-Pins der mindestens zwei elektronischen Bauteilen auf gegenüberliegenden Oberflächenseiten der Leiterplatte entkoppelt bzw. verbunden. Dies ermöglicht eine einfache und schnelle Bestückung und Kontaktierung während der Herstellung. Another advantage of this arrangement results in the case of a bridge circuit of two transistors. After the voltage connections come to lie on a surface side of the printed circuit board as a result of the inversion of the one transistor, one or more ceramic capacitors for decoupling the bridge circuit from the supply voltage can be connected on this surface side, whereby such components are generally smaller and smaller can be chosen cheaper and both the EMC and the performance of the bridge can be improved. In other words, an embodiment of the invention provides that further connection pins of the at least two electronic components to be connected to one another, in particular transistors of a bridge circuit, by means of a component or a component, such as a ceramic capacitor, from another circuit part, eg Supply voltage, are decoupled. In a further embodiment, the connection pins to be decoupled and the connection pins of the at least two electronic components to be directly connected to one another on opposite surface sides of the circuit board are decoupled or connected. This allows a simple and fast assembly and contacting during manufacture.
Gemäß einer möglichen Ausführungsform sind die mindestens zwei elektronischen Bauteile in jeweils einer zugehörigen vergossenen Kavität angeordnet und elektrisch mit Leiterbahnen mindestens einer Leiterlage verbunden, wobei die miteinander zu verbindenden Anschluss-Pins der zwei elektronischen Bauteile in einer Leiterlage mit einer Leiterbahn verbunden sind. Durch die Verbindung mit Leiterbahnen einer Leiterlage sind According to one possible embodiment, the at least two electronic components are each arranged in an associated molded cavity and are electrically connected to conductor tracks of at least one conductor layer, wherein the connection pins of the two electronic components to be connected to one another are connected in a conductor layer to a conductor track. By the connection with conductor tracks of a conductor layer are
Durchkontaktierungen sicher vermieden und kurze Verbindungs- strecken ermöglicht. Through holes reliably avoided and short connecting distances possible.
Vorzugsweise sind die elektronischen Bauteile voneinander beabstandet angeordnet. Darüber hinaus ist der jeweilige An- schluss-Pin des oder der elektronischen Bauteile als eine Bond-Verbindung ausgebildet, die in Art eines Armes von dem zugehörigen elektronischen Bauteil abgeht und dessen freies Ende mit einer der Leiterbahnen kontaktiert ist. Dabei sind die Anschluss-Pins insbesondere bei Verbindung mit mehreren Lei¬ terbahnen in einer Leiterlage mit den Leiterbahnen kontaktiert, um Durchkontaktierungen zu vermeiden. Preferably, the electronic components are spaced from each other. In addition, the respective connection pin of the electronic component (s) is designed as a bonding connection, which branches off in the manner of an arm from the associated electronic component and whose free end is contacted with one of the conductor tracks. The connection pins are contacted in particular in connection with several Lei ¬ terbahnen in a conductor layer with the conductor tracks, in order to avoid plated-through holes.
Zusätzlich kann mindestens eine Trägerlage, insbesondere ein Kupferträger oberhalb und/oder unterhalb des elektronischen Bauteils angeordnet sein. Eine solche aus Kupfer gebildete Trägerlage kann als Leiterbahn und/oder Anschluss-Element dienen, wodurch die elektrischen Verbindungsstrecken weiter reduziert sind. In addition, at least one carrier layer, in particular a copper carrier above and / or below the electronic Be arranged component. Such a carrier layer formed of copper can serve as a conductor track and / or connection element, whereby the electrical connection links are further reduced.
Das erfindungsgemäße Verfahren zur Herstellung einer Leiterplatte mit innen und/oder außen liegenden Leiterbahnen und mindestens zwei innen liegenden, elektronischen Bauteilen sieht vor, dass in die Leiterplatte für ein jedes elektronisches Bauteil eine Kavität eingebracht, insbesondere gelasert, wird und die elektronischen Bauteile in diese Kavität derart anordenbar sind, dass deren miteinander zu verbindenden An- schluss-Pins in Richtung einer Oberflächenseite der Leiterplatte gerichtet sind und dass diese zu verbindenden Anschluss-Pins mit einer der Leiterbahnen einer Leiterlage miteinander verbunden und befestigt werden sowie anschließend gegebenenfalls die Kavitäten mit den darin positionierten und elektrisch verbundenen elektronischen Bauteilen vergossen werden. Vorzugsweise werden zu entkoppelnde Anschluss-Pins der elektronischen Bauteile auf einer gegenüberliegenden Oberflächenseite derThe inventive method for producing a printed circuit board with internal and / or external conductor tracks and at least two internal electronic components provides that in the circuit board for each electronic component introduced a cavity, in particular lasered, and the electronic components in this cavity can be arranged such that their connection pins to be connected together are directed in the direction of a surface side of the circuit board and that these connecting pins to be connected to one of the conductor tracks of a conductor layer are connected and fixed together and then optionally the cavities with the positioned therein and electrically connected electronic components. Preferably, to be decoupled connection pins of the electronic components on an opposite surface side of
Leiterplatte mit Leiterbahnen einer Leiterlage verbunden und mittels eines Bauteils zwischen diesen Leiterbahnen entkoppelt. Printed circuit board connected to conductor tracks of a conductor layer and decoupled by means of a component between these interconnects.
Das Verfahren ist besonders einfach und kostengünstig und vermeidet Durchkontaktierungen . The method is particularly simple and inexpensive and avoids vias.
Ausführungsbeispiele der Erfindung werden anhand von Zeichnungen näher erläutert. Dabei zeigen: Fig. 4 bis 9 schematisch in Schnittdarstellung verschiedene Embodiments of the invention will be explained in more detail with reference to drawings. FIG. 4 to 9 show schematically different sectional views. FIG
Ausführungsformen für eine Leiterplatte mit innen und außen liegenden Leiterbahnen und mehreren integrierten elektronischen Bauteilen, die miteinander elektrisch verschaltet sind.  Embodiments of a printed circuit board with inner and outer traces and a plurality of integrated electronic components, which are electrically interconnected.
Einander entsprechende Bauteile sind in allen Figuren mit den gleichen Bezugszeichen versehen. Figur 4 zeigt ein Ausführungsbeispiel für eine erfindungsgemäße Leiterplatte 1λ mit außen liegenden Leiterbahnen 2λ und 3 von denen die einen Leiterbahnen 2 λ auf einer Oberflächenseite Ol λ in einer Leiterlage LI (= obere Leiterbahnen) und die anderen Leiterbahnen 3 λ auf der gegenüberliegenden Oberflächenseite 02 λ der Leiterplatte 1 λ in einer weiteren Leiterlage L2 angeordnet sind . Corresponding components are provided in all figures with the same reference numerals. Figure 4 shows an embodiment of a circuit board according to the invention 1 λ with external conductors 2 λ and 3 of which one conductor 2 λ on a surface side Ol λ in a conductor layer LI (= upper interconnects) and the other interconnects 3 λ on the opposite surface side 02 λ of the circuit board 1 λ are arranged in a further conductor layer L2.
Die Leiterbahnen 2λ, 3λ sind dabei als Kupferflächen oder -bahnen, -lagen ausgebildet und dienen der elektrischen Verbindung von wenigstens zwei elektronischen Bauteilen 4λ und 5λ. Hierzu sind die elektronischen Bauteile 4λ, 5λ mit den Lei¬ terbahnen 2λ, 3λ verbunden, insbesondere Stoffschlüssig ver¬ bunden, beispielsweise gelötet. The interconnects 2 λ , 3 λ are formed as copper surfaces or tracks, layers and serve the electrical connection of at least two electronic components 4 λ and 5 λ . For this purpose, the electronic components 4 λ , 5 λ with the Lei ¬ terbahnen 2 λ , 3 λ connected, in particular cohesively ver ¬ connected, for example, soldered.
Im Ausführungsbeispiel nach Figur 4 sind die elektronischen Bauteile 4 λ und 5 λ innen liegend in die Leiterplatte 1 λ in¬ tegriert. Alternativ oder zusätzlich können weitere nicht näher dargestellte elektronische Bauteile innen und/oder außen an- geordnet sein. In the embodiment of Figure 4, the electronic components 4 λ and 5 λ are inside lying in the circuit board 1 λ in ¬ tegrated. Alternatively or additionally, further electronic components not shown in detail may be arranged inside and / or outside.
Die Leiterplatte 1 λ kann als eine einschichtige oder mehr¬ schichtige Leiterplatte mit innen und/oder außen liegenden Leiterbahnen 2λ und 3λ ausgebildet sein. The printed circuit board 1 λ may be formed as a single-layer or multi- layered printed circuit board with inner and / or outer conductor tracks 2 λ and 3 λ .
Die elektronischen Bauteile 4λ, 5λ können Halbleiterbauele¬ mente, wie Transistoren, Leistungstransistoren, Sensoren, Dioden, Kondensatoren und/oder Steuergeräte sein. Zur Verbindung der zwei innen liegenden, elektronischen Bauteile 4λ, 5 insbesondere deren Anschluss-Pins 4axbis 4c 5a λ bis 5c mit den außen liegenden Leiterbahnen 2λ, 3 insbesondere mit Anschlüssen 4d 4e 5e 5dx in den außen liegenden Leiterbahnen 2λ, 3 sind innen liegende Leiterbahnen 10 oder Zuleitungen 11 λ vorgesehen. The electronic components 4 λ , 5 λ may be Halbleitererbauele ¬ elements, such as transistors, power transistors, sensors, diodes, capacitors and / or control devices. For connecting the two internal electronic components 4 λ , 5 in particular their connection pins 4a x to 4c 5a λ to 5c with the outer conductor tracks 2 λ , 3 in particular with terminals 4d 4e 5e 5d x in the outer tracks 2 λ , 3 are inner conductor tracks 10 or leads 11 λ provided.
Die zwei innen liegenden elektronischen Bauteile 4 λ und 5 λ sind im Ausführungsbeispiel nach Figur 4 Transistoren, die zu einer Halbbrücke Ηλ mittels der außen liegenden Leiterbahnen 2λ, 3λ und der innen liegenden Zuleitungen 11 λ verschaltet sind, wie anhand der Schaltung in Figur 5 gezeigt. Die Transistoren sind Leistungstransistoren, insbesondere sogenannte MOSFETs. The two internal electronic components 4 λ and 5 λ are in the embodiment of Figure 4 transistors which are connected to a Half bridge Η λ by means of the outer conductor tracks 2 λ , 3 λ and the inner leads 11 λ are connected, as shown by the circuit in Figure 5. The transistors are power transistors, in particular so-called MOSFETs.
Dabei bilden die Anschluss-Pins 4a λ bis 4c λ des einen Tran¬ sistors (= 4λ) einen Gate-Anschluss Gl (= 4ax), einen Sour- ce-Anschluss Sl (= 4bx) und einen Drain-Anschluss Dl (= 4cx), und die Anschluss-Pins 5a λ bis 5c λ des anderen Transistors (= 5) λ einen Gate-Anschluss G2 (= 5ax), einen Source-Anschluss S2 (= 5b λ ) und einen Drain-Anschluss D2 (= 5cx), wie in Figur 5 gezeigt. Dabei ist der Source-Anschluss Sl des einen Transistors (= 4λ) mit dem Drain-Anschluss D2 des anderen Transistors (= 5λ) direkt elektrisch miteinander verbunden, wobei der In this case, the connection pins 4a λ to 4c λ of a Tran ¬ sistors (= 4 λ ) form a gate terminal Gl (= 4a x ), a Sour- ce terminal Sl (= 4b x ) and a drain terminal Dl (= 4c x ), and the terminal pins 5a λ to 5c λ of the other transistor (= 5) λ a gate terminal G2 (= 5a x ), a source terminal S2 (= 5b λ ) and a drain terminal D2 (= 5c x ), as shown in FIG. In this case, the source terminal Sl of one transistor (= 4 λ ) with the drain terminal D2 of the other transistor (= 5 λ ) connected directly to each other electrically, wherein the
Drain-Anschluss Dl des einen Transistors (= 4λ) vom Sour¬ ce-Anschluss S2 des anderen Transistors (= 5λ) mittels eines Bauteils 9, insbesondere eines Kondensators, zum Beispiel eines Keramik-Kondensators, verbunden ist. Die mindestens zwei elektronischen Bauteile 4 λ und 5 λ sind derart in der Leiterplatte 1 λ angeordnet, dass deren miteinander zu verbindenden Anschluss-Pins 4b λ (= Soruce-Anschluss Sl) und 5c λ (Drain-Anschluss D2) in Richtung einer Oberflächenseite 02 λ der Leiterplatte 1 λ gerichtet sind und dabei über die außen liegende Leiterbahn 3λ in einer Leiterlage L2 direkt ohne Drain terminal Dl of one transistor (= 4 λ ) from the Sour ¬ ce terminal S2 of the other transistor (= 5 λ ) by means of a component 9, in particular a capacitor, for example a ceramic capacitor, is connected. The at least two electronic components 4 λ and 5 λ are arranged in the printed circuit board 1 λ such that their connection pins to be connected together 4b λ (= Soruce port Sl) and 5c λ (drain port D2) in the direction of a surface side 02 λ of the circuit board 1 λ are directed and thereby on the outer conductor 3 λ in a conductor layer L2 directly without
Durchkontaktierung miteinander elektrisch verbunden sind.  Through-connection are electrically connected to each other.
Hierzu sind die elektrisch zu verbindenden Anschluss-Pins 4b λ und 5c λ mittels der innen liegenden Zuleitung 11 λ bzw. einer elektrisch leitfähigen Schicht 6 insbesondere einem elekt- risch leitfähigen Kleber, mit den betreffenden Anschlüssen 4e λ bzw. 5f λ in der Leiterbahn 3λ der einen Leiterlage L2 elektrisch verbunden . For this purpose, the connection pins 4b λ and 5c λ to be electrically connected are by means of the inner lead 11 λ or an electrically conductive layer 6, in particular an electrically conductive adhesive, with the relevant terminals 4e λ or 5f λ in the conductor 3 λ of a conductor layer L2 electrically connected.
Die elektrisch leitfähige Schicht 6λ dient dabei der stoff- schlüssigen Befestigung des jeweiligen elektronischen Bauteils 4λ, 5λ auf der Kupferlage der Leiterbahn 2λ bzw. 3λ. Die elektronischen Bauteile 4 5 λ können sowohl als gehäuste wie auch als „bare die" Komponenten in den Schaltungsträger oder die Leiterplatte 1λ integriert sein. Figur 6 zeigt im Detail die Verbindung der Anschluss-Pins 4c λ und 5b λ der mindestens zwei elektronischen Bauteile 4λ bzw. 5λ mittels des Bauteils 9λ oder eines Entkopplungselement, ins¬ besondere eines Kondensators, der außen auf der Oberflächen¬ seite Ol λ auf den zugehörigen Anschlüssen 4f λ bzw. 5f λ von oberen Leiterbahnen 2λ in der einen Leiterlage LI mittels einer elektrisch leitfähigen Schicht 6 insbesondere eines elekt¬ risch leitfähigen Klebers, befestigt ist. The electrically conductive layer 6 λ serves the material-conclusive attachment of the respective electronic component 4 λ , 5 λ on the copper layer of the conductor 2 λ or 3 λ . The electronic components 4 5 λ may be integrated in the circuit substrate or circuit board 1 λ both as packaged as well as a "bare the" components. Figure 6 shows in detail the connection of the connecting pins 4c λ and 5b λ of at least two electronic components 4 λ or 5 λ by means of the component 9 λ or a decoupling element, in ¬ particular of a capacitor on the outside of the surface ¬ side Ol λ on the associated terminals 4f λ and 5f λ of upper tracks 2 λ in the one conductor layer LI is attached by means of an electrically conductive layer 6 in particular a elekt ¬ driven conductive adhesive.
Wie in Figur 6 gezeigt, sind die zu entkoppelnden An- schluss-Pins 4c λ und 5b λ und deren Anschlüsse 4f λ und 5e λ in den oberen Leiterbahnen 2 λ und die miteinander direkt zu verbindenden Anschluss-Pins 4b λ und 5c λ und deren Anschlüsse 4e λ bzw. 5fx auf gegenüberliegenden Oberflächenseiten Ol λ bzw. 02 λ der Leiterplatte 1λ angeordnet. As shown in FIG. 6, the connection pins 4c λ and 5b λ to be decoupled and their terminals 4f λ and 5e λ in the upper interconnects 2 λ and the connection pins 4b λ and 5c λ and their interconnected directly to one another Terminals 4e λ and 5f x arranged on opposite surface sides of Ol λ and 02 λ of the circuit board 1 λ .
Nachfolgend seien anhand von„bare die" MOSFETs als elektronische Bauteile 4 λ und 5 λ beispielhaft verschiedene mögliche Reali¬ sierungsvarianten gezeigt und beschrieben. Dabei bedeutet: Below are based on MOSFETs "the bare" λ 4, and λ 5 by way of example different possible Reali ¬ sierungsvarianten shown and described as an electronic component here means.:
„face up" : = Source-Anschluss Sl und Gate-Anschluss Gl nach oben orientiert in Richtung der oberen Oberflächenseite Ol .  "Face up": = source terminal Sl and gate terminal Gl oriented upward towards the upper surface side Ol.
„face down": Source-Anschluss S2 und Gate-Anschluss G2 nach unten orientiert in Richtung der unteren Oberflächenseite 02. "Face down": source S2 and gate G2 oriented down towards the lower surface side 02.
Bei dem nachfolgenden Komponententräger handelt es sich insbesondere um mindestens eine Leiterlage, die oberhalb und/oder unterhalb des elektronischen Bauteils 4 λ und 5 λ angeordnet ist und aus mindestens einer der Leiterbahnen 2 3 λ oder 10 und einer der angrenzenden Leiterplatten-Isolierlagen LPl bis LPm gebildet ist. Figur 7 zeigt ein Ausführungsbeispiel für eine mehrschichtige Leiterplatte 1 λ mit mehreren Isolierlagen LPl bis LPm und mehreren außen liegenden Leiterbahnen 2λ, 3λ und innen liegenden Leiterbahnen 10, insbesondere sogenannte Kupferzwischenlagen, in mehreren Leiterlagen LI bis Ln . The following component carrier is in particular at least one conductor layer, which is arranged above and / or below the electronic component 4 λ and 5 λ and at least one of the interconnects 2 3 λ or 10 and one of the adjacent printed circuit board insulating LPl to LPm is formed. Figure 7 shows an embodiment for a multilayer printed circuit board 1 λ having a plurality of insulating layers LPL to LPm and a plurality of outer strip conductors 2 λ 3 λ and internal interconnects 10, in particular so-called copper intermediate layers in multiple conductor layers LI to Ln.
Die mindestens zwei innen liegenden, elektronischen Bauteile 4 5λ sind in die zweite Isolierlage LP2 integriert. In der Leiterplatte 1λ sind die elektronischen Bauteile 4λ und 5λ voneinander beabstandet angeordnet. The at least two internal electronic components 4 5 λ are integrated into the second insulating layer LP2. In the circuit board 1 λ , the electronic components 4 λ and 5 λ are arranged spaced from each other.
Der jeweilige Anschluss-Pin 4a λ bis 4c λ und 5a λ bis 5c λ der elektronischen Bauteile 4λ bzw. 5λ ist als eine Bond-Verbindung ausgebildet, die in Art eines Armes von dem zugehörigen elektronischen Bauteil 4λ bzw. 5λ abgeht und dessen freies Ende mit einer der Leiterbahnen 2λ, 3λ oder 10 kontaktiert ist. The respective connection pin 4a λ to 4c λ and 5a λ to 5c λ of the electronic components 4 λ and 5 λ is formed as a bond connection, which in the manner of an arm of the associated electronic component 4 λ and 5 λ goes off and whose free end is contacted with one of the conductor tracks 2 λ , 3 λ or 10.
Dabei werden die elektronischen Bauteile 4λ, 5λ auf einen Komponententräger, zum Beispiel einem Kupfer-Träger, In this case, the electronic components 4 λ , 5 λ on a component carrier, for example a copper carrier,
Cu-Leadframe, Cu-kaschierte Laminatfolie, elektrisch leitend befestigt, insbesondere durch Löten, Sintern, Leitkleben, etc..  Cu leadframe, Cu-laminated laminate foil, electrically conductively fixed, in particular by soldering, sintering, conductive bonding, etc ..
Der Komponententräger wird beim Verlegen/Stapeln der Leiter- lagen LI bis Lm und der Isolierlagen LPl bis LPm „face up" bzw. „face down" ausgerichtet und verpresst. The component carrier is aligned and pressed "face up" or "face down" during the laying / stacking of the conductor layers LI to Lm and the insulating layers LP1 to LPm.
Der Komponententräger wird durch Bohr- und Ätzprozesse mittels Mikro-Vias ankontaktiert . The component carrier is contacted by drilling and etching processes using micro-vias.
Die elektronischen Bauteile 4λ, 5λ werden ebenfalls durch Bohr- und Ätzprozesse mittels Mikro-Vias (Zuleitungen 11 und An¬ schlüsse 4dx bis 4f λ und 5dx bis 5f λ ankontaktiert. Figur 8 zeigt ein alternatives Ausführungsbeispiel für eine mehrschichtige Leiterplatte 1 λ . Die mindestens zwei innen liegenden, elektronischen Bauteile 4 5λ sind in die zweite Leiterlage L2 integriert. The electronic components 4 λ, 5 λ be ankontaktiert also by drilling and etching processes by micro-vias (supply lines 11 and ¬ connections 4d x to 4f λ and 5d x to 5f λ. Figure 8 shows an alternative embodiment for a multilayer printed circuit board 1 λ . The at least two internal electronic components 4 5 λ are integrated into the second conductor layer L2.
Hierbei werden die elektronischen Bauteile 4 λ und 5 λ in einer zugehörigen Kavität K eines Komponententrägers eingebracht und bestückt sowie elektrisch leitend befestigt, zum Beispiel durch Löten, Sintern, Leitkleben. In this case, the electronic components 4 λ and 5 λ are introduced into an associated cavity K of a component carrier and assembled and fixed electrically conductive, for example by soldering, sintering, Leitkleben.
Der Komponententräger wird beim Verlegen/Stapeln der Leiterlagen LI bis Ln und der Isolierlagen LP1 bis LPm „face up" bzw. „face down" ausgerichtet und verpresst. The component carrier is aligned and pressed "face up" or "face down" when laying / stacking the conductor layers LI to Ln and the insulating layers LP1 to LPm.
Der Komponententräger wird durch Bohr- und Ätzprozesse mittels Mikro-Vias (= innere Zuleitungen 11 λ) ankontaktiert . The component carrier is contacted by drilling and etching processes by means of micro-vias (= inner leads 11 λ ).
Die elektronischen Bauteile 4 λ und 5 λ werden ebenfalls durch Bohr- und Ätzprozesse mittels Mikro-Vias (= Zuleitungen 11 λ) an die Anschlüsse 4dx bis 4f λ bzw. 5dx bis 5f λ einer der innen und/oder außen liegenden Leiterbahnen 2λ, 3 10 einer Lei- terlage LI bis Ln ankontaktiert. The electronic components 4 λ and 5 λ are also by drilling and etching processes by micro vias (= leads 11 λ ) to the terminals 4d x to 4f λ and 5d x to 5f λ one of the inside and / or outside conductor tracks. 2 λ , 3 10 of a Leitlage LI to Ln ankontaktiert.
Dabei können die mindestens zwei elektronischen Bauteile 4 λ und 5λ in jeweils einer zugehörigen vergossenen Kavität K angeordnet sein und elektrisch mit innen und/oder außen liegenden Lei- terbahnen 2λ, 3λ und 10 mindestens einer Leiterlage LI bis Ln verbunden sein. Dabei sind die miteinander zu verbindenden Anschluss-Pins 4b λ und 5c λ der zwei elektronischen Bauteile 4λ bzw. 5λ in einer Leiterlage L3 mit einer Leiterbahn 4e λ verbunden . In this case, the at least two electronic components 4 λ and 5 λ may be arranged in each case in an associated molded cavity K and electrically connected to inner and / or outer conductor tracks 2 λ , 3 λ and 10 at least one conductor layer LI to Ln. In this case, the connection pins 4b λ and 5c λ of the two electronic components 4 λ and 5 λ to be connected to one another are connected in a conductor layer L3 to a conductor track 4e λ .
Das Ausführungsbeispiel nach Figur 8 hat gegenüber dem Aus¬ führungsbeispiel nach Figur 7 den Vorteil, dass beim Verlegen der Prepreg-Lagen oder Isolierlagen LP1 bis LPm keine Öffnun- gen/"Fenster" im Laminat der Isolierlagen LP1 bis LPm im Bereich der elektronischen Bauteile 4λ, 5 zum Beispiel eines Chips, sein müssen. Nachteilig ist, dass die Komponenten oder elektronischen Bauteile 4λ, 5λ im Ausführungsbeispiel nach Figur 8 in eine Kavität K einer der innen liegenden Leiterbahnen 10 der betreffenden Leiterlage L2 und somit des Kupfers assembliert werden müssen. The exemplary embodiment according to FIG. 8 has the advantage over the exemplary embodiment according to FIG. 7 that no openings / "windows" in the laminate of the insulating layers LP1 to LPm in the area of the electronic components 4 are present when the prepreg layers or insulating layers LP1 to LPm are laid λ , 5, for example, a chip must be. The disadvantage is that the components or electronic components 4 λ , 5 λ in the embodiment of Figure 8 in a cavity K of one of the inner conductor tracks 10 of the respective conductor layer L2 and thus the copper must be assembled.
Figur 9 zeigt ein weiteres alternatives Ausführungsbeispiel für eine mehrschichtige Leiterplatte 1 λ mit drei Isolierlagen LP1 bis LP3, von denen zwei Isolierlagen LP1 und LP2 ohne Zwi- schenleiterbahnen unmittelbar aneinandergrenzen, und mit innen und außen liegenden Leiterbahnen 2 3 10 in drei Leiterlagen LI bis L3 verbunden sind. FIG. 9 shows a further alternative exemplary embodiment of a multilayer printed circuit board 1 λ with three insulating layers LP1 to LP3, of which two insulating layers LP1 and LP2 directly adjoin each other without intermediate conductor tracks, and with inner and outer conductor tracks 2 3 10 in three conductor layers LI to L3 are connected.
Hierzu ist zwischen dem in der Isolierlage LP1 integrierten elektronischen Bauteil 4 λ und der angrenzenden Isolierlage LP2 ein elektrisch isolierender Kleber 7 oder ein anderes geeignetes elektrisch isolierendes Material, in Art einer Schicht, an¬ geordnet . Die elektronischen Bauteile 4λ, 5λ werden „face up" bzw. „face down" auf einer Cu-Trägerfolie als Komponententräger geklebt. For this purpose, between the integrated in the insulating layer LP1 electronic component 4 λ and the adjacent insulating layer LP2 an electrically insulating adhesive 7 or other suitable electrically insulating material, in the manner of a layer ordered on ¬ . The electronic components 4 λ , 5 λ are glued "face up" or "face down" on a Cu carrier film as a component carrier.
Nachfolgend werden die Aufbauinnenlagen und somit die Iso¬ lierlagen LP1 und LP2 verlegt und verpresst. Der Kern wird an den Kontaktstellen aufgebohrt und durch chemische Prozesse werden die Mikro-Via Verbindungen zwischen den Innenlagen, den Isolierlagen LP1 bis LP2 und den Bauteilen 4λ, 5λ (Ober- und Unterseite) erzeugt. Subsequently, the structure of the inner layers and thus the iso ¬ lierlagen LP1 and LP2 are laid and pressed. The core is drilled at the contact points and by chemical processes, the micro-via connections between the inner layers, the insulating layers LP1 to LP2 and the components 4 λ , 5 λ (top and bottom) generated.

Claims

Patentansprüche claims
1. Leiterplatte (1λ) mit innen und außen liegenden Lei¬ terbahnen (2 3 10), die auf wenigstens einer Leiterlage (LI bis Ln) angeordnet sind, sowie mit mindestens zwei innen liegenden, elektronischen Bauteilen (4λ, 5λ), welche mittels mindestens eines Anschluss-Pins (4ax bis 4c 5ax bis 5cx) mit einer der Leiterbahnen (2λ, 3 10) verbunden sind, wobei die mindestens zwei elektronischen Bauteile (4 5λ) derart in der Leiterplatte (1λ) angeordnet sind, dass deren miteinander zu verbindende Anschluss-Pins (4axbis4c 5axbis5cx) in Richtung einer Oberflächenseite (Ol λ oder 02 λ ) der Leiterplatte (1λ) gerichtet sind. 1. printed circuit board (1 λ ) with inner and outer lying Lei ¬ terbahnen (2 3 10), which are arranged on at least one conductor layer (LI to Ln), and with at least two internal electronic components (4 λ , 5 λ ) which are connected by means of at least one connection pin (4a x to 4c 5a x to 5c x ) with one of the conductor tracks (2 λ , 3 10), wherein the at least two electronic components (4 5 λ ) in the circuit board (1 λ ) are arranged so that their connection pins to be connected together (4a x bis4c 5a x bis5c x ) in the direction of a surface side (Ol λ or 02 λ ) of the circuit board (1 λ ) are directed.
2. Leiterplatte (1λ) nach Anspruch 1, 2. printed circuit board (1 λ ) according to claim 1,
wobei weitere miteinander zu verbindende Anschluss-Pins (4a λ bis 4c 5a λ bis 5c λ) der mindestens zwei elektronischen Bautei¬ le (4λ, 5λ) über ein Bauteil (9λ) miteinander verbunden sind. wherein further each other to be connected to connection pins (4a to 4c λ λ 5a to 5c λ) of the at least two electronic Bautei ¬ le (4 λ, λ 5) via a component are 9) connected together.
3. Leiterplatte (1λ) nach Anspruch 2, 3. printed circuit board (1 λ ) according to claim 2,
wobei die über das Bauteil (9) zu verbindenden An¬ schluss-Pins (4ax bis 4c 5ax bis 5cx) und die miteinander direkt zu verbindenden Anschluss-Pins (4a λ bis 4c 5a λ bis 5c λ) der mindestens zwei elektronischen Bauteilen (4λ, 5λ) auf gegenüberliegenden Oberflächenseiten (01 02 λ ) der Leiterplatte (1λ) verbunden sind. wherein the above, the component (9) to be connected to ¬ circuit pins (4a x to 4c 5a x-5c x) and directly with each other to be connected to connection pins (4a λ to 4c 5a λ to 5c λ) of the at least two electronic Components (4 λ , 5 λ ) on opposite surface sides (01 02 λ ) of the circuit board (1 λ ) are connected.
4. Leiterplatte (1λ) nach einem der vorhergehenden Ansprüche, wobei die mindestens zwei elektronischen Bauteile (4 5λ) in j eweils einer zugehörigen vergossenen Kavität (K) angeordnet und elektrisch mit Leiterbahnen (2λ, 3 10) mindestens einer Leiterlage (LI bis Ln) verbunden sind, wobei die miteinander zu verbindenden Anschluss-Pins (4a λ bis 4c 5a λ bis 5c λ) der zwei elektronischen Bauteile (4 5λ) in einer Leiterlage (LI bis Ln) mit einer Leiterbahn (2λ, 3 10) verbunden sind. 4. printed circuit board (1 λ ) according to one of the preceding claims, wherein the at least two electronic components (4 5 λ ) in each case an associated potted cavity (K) and arranged electrically with conductor tracks (2 λ , 3 10) at least one conductor layer ( LI to Ln), wherein the connection pins (4a λ to 4c 5a λ to 5c λ ) to be connected to each other of the two electronic components (4 5 λ ) in a conductor layer (LI to Ln) with a conductor track (2 λ , 3 10) are connected.
5. Leiterplatte (1λ) nach einem der vorhergehenden Ansprüche, wobei die elektronischen Bauteile (4 5λ) voneinander beabstandet angeordnet sind. 5. printed circuit board (1 λ ) according to any one of the preceding claims, wherein the electronic components (4 5 λ ) are arranged spaced from each other.
6. Leiterplatte (1λ) nach einem der vorhergehenden Ansprüche, wobei der jeweilige Anschluss-Pin (4ax bis 4c 5ax bis 5cx) des oder der elektronischen Bauteile (4 5λ) als eine 6. printed circuit board (1 λ ) according to any one of the preceding claims, wherein the respective terminal pin (4a x to 4c 5a x to 5c x ) of the electronic components or (4 5 λ ) as a
Bond-Verbindung ausgebildet ist, die in Art eines Armes von dem zugehörigen elektronischen Bauteil (4 5λ) abgeht und dessen freies Ende mit einer der Leiterbahnen (2λ, 3 10) kontaktiert ist . Bond connection is formed, which in the manner of an arm of the associated electronic component (4 5 λ ) goes off and whose free end with one of the conductor tracks (2 λ , 3 10) is contacted.
7. Leiterplatte (1λ) nach einem der vorhergehenden Ansprüche, wobei mindestens eine Trägerlage oberhalb und/oder unterhalb des elektronischen Bauteils (4 5λ) angeordnet ist. 7. printed circuit board (1 λ ) according to one of the preceding claims, wherein at least one carrier layer above and / or below the electronic component (4 5 λ ) is arranged.
8. Verfahren zur Herstellung einer Leiterplatte (1λ) mit innen und/oder außen liegenden Leiterbahnen (2λ, 3 10) und mindestens zwei innen liegenden, elektronischen Bauteilen (4λ, 5λ) nach einem der vorhergehenden Ansprüche, 8. A method for producing a printed circuit board (1 λ ) with inner and / or outer conductor tracks (2 λ , 3 10) and at least two internal electronic components (4 λ , 5 λ ) according to any one of the preceding claims,
wobei in die Leiterplatte (1λ) für ein jedes elektronisches Bauteil (4 5λ) eine Kavität (K) eingebracht wird und die elektronischen Bauteile (4 5λ) in diese Kavität (K) derart anordenbar sind, deren miteinander zu verbindende An- schluss-Pins (4ax bis 4c 5ax bis 5cx) in Richtung einerwherein a cavity (K) is introduced into the printed circuit board (1 λ ) for each electronic component (4 5 λ ) and the electronic components (4 5 λ ) can be arranged in this cavity (K) in such a way that their connection to each other is closing pins (4a x to 4c 5a x to 5c x ) in the direction of a
Oberflächenseite (Ol λ oder 02 λ) der Leiterplatte (1λ) gerichtet sind und diese zu verbindenden Anschluss-Pins (4ax bis 4c 5ax bis 5cx) mit einer der Leiterbahnen (2λ, 3 10) einer Leiterlage (LI bis Ln) miteinander verbunden und befestigt werden. Surface side (Ol λ or 02 λ ) of the circuit board (1 λ ) are directed and these connecting pins (4a x to 4c 5a x to 5c x ) with one of the tracks (2 λ , 3 10) of a conductor layer (LI to Ln) are connected and fixed together.
9. Verfahren nach Anspruch 8, 9. The method according to claim 8,
wobei über das Bauteil (9) zu verbindende Anschluss-Pins (4a λ bis 4c 5ax bis 5cx) der elektronischen Bauteile (4 5λ) auf einer gegenüberliegenden Oberflächenseite (01 02 λ ) der Leiterplatte (1λ) mit Leiterbahnen (2λ, 3 10) einer Lei¬ terlage (LI bis Ln) verbunden werden und mittels eines Bau¬ teils (9λ) zwischen diesen Leiterbahnen (2λ, 3 10) miteinander verbunden werden. wherein over the component (9) to be connected to connection pins (4a λ to 4c 5a x-5c x) of the electronic parts (4 5 λ) on an opposite surface side (01 02 λ) of the circuit board (1 λ) (with conductor tracks 2 λ , 3 10) a Lei ¬ terlage (LI to Ln) are connected and by means of a Bau ¬ part (9 λ ) between these interconnects (2 λ , 3 10) are interconnected.
PCT/EP2014/059632 2013-06-20 2014-05-12 Circuit board WO2014202282A1 (en)

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