DE102005003125A1 - High-frequency electrical circuit for multi-chip module, has electrical components mechanically connected with each other by sealing compound and provided with conductive strip layers, which electrically connects components with each other - Google Patents
High-frequency electrical circuit for multi-chip module, has electrical components mechanically connected with each other by sealing compound and provided with conductive strip layers, which electrically connects components with each other Download PDFInfo
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- DE102005003125A1 DE102005003125A1 DE102005003125A DE102005003125A DE102005003125A1 DE 102005003125 A1 DE102005003125 A1 DE 102005003125A1 DE 102005003125 A DE102005003125 A DE 102005003125A DE 102005003125 A DE102005003125 A DE 102005003125A DE 102005003125 A1 DE102005003125 A1 DE 102005003125A1
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- 150000001875 compounds Chemical class 0.000 title claims abstract description 32
- 238000007789 sealing Methods 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 238000004382 potting Methods 0.000 claims description 33
- 239000004020 conductor Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 18
- 238000005553 drilling Methods 0.000 claims description 10
- 239000011888 foil Substances 0.000 claims description 4
- 229940126214 compound 3 Drugs 0.000 description 10
- 239000004033 plastic Substances 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 6
- 238000001746 injection moulding Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 238000007650 screen-printing Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
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- 238000001465 metallisation Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000007649 pad printing Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000005266 casting Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
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- 229920001721 polyimide Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910001338 liquidmetal Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Die vorliegende Erfindung betrifft eine elektrische Schaltung sowie ein Verfahren zur Herstellung einer elektrischen Schaltung, wobei die Schaltung elektrische Bauelemente aufweist und wobei die Bauelemente mechanisch nur durch eine Vergussmasse miteinander verbunden sind und auf mindestens einer Seite der Vergussmasse mindestens eine Schicht Leiterbahnen aufweist, die die Bauelemente elektrisch miteinander verbinden. Das Herstellungsverfahren sieht vor, die Bauelemente auf eine Trägerfolie aufzubringen und die Bauelemente auf der Trägerfolie mit einer Vergussmasse oder moulding compound zu umgießen und anschließend die Trägerfolie zu entfernen und auf der Seite der mit der Vergussmasse umgossenen Bauelemente, die mit der Trägerfolie verbunden war, eine oder mehrere Schichten von Leiterbahnen aufzubringen, die die Bauelemente elektrisch miteinander verbinden.The The present invention relates to an electrical circuit as well a method for producing an electrical circuit, wherein the circuit comprises electrical components and wherein the components mechanically connected to each other only by a potting compound and on at least one side of the potting compound at least one layer Has printed conductors, which electrically connect the components with each other connect. The manufacturing process provides the components on a carrier foil apply and the components on the carrier film with a potting compound or molding compound and subsequently the carrier film too Remove and on the side of the encapsulated with the potting compound Components connected to the carrier film was connected to apply one or more layers of conductor tracks, which electrically interconnect the components.
Aus
der
Die
Aus
der
Derartige Multi-Chip-Module, die aus dem Stand der Technik bekannt sind, werden derart aufgebaut, dass auf einer Leiterplatte bzw. einem Substrat, das als mechanischer Träger dient, Bauelemente aufgebracht und elektrisch miteinander verbunden werden. Zur Kontaktierung der Bauelemente wird häufig die Drahtbondtechnik eingesetzt, bei der mittels kurzer, elektrisch leitfähiger Bonddrähte Kontakte elektrisch miteinander verbunden werden. Hierbei werden die Bonddrähte zwischen den beiden Kontakten meist bogenförmig geformt, wodurch sogenannte Loops entstehen. Beim Einsatz in Hochfrequenzschaltungen weisen diese in Drahtbondtechnik hergestellten Loops parasitäre Induktivitäten und Kapazitäten auf, die kompensiert werden müssen. Da die Bonddrähte im Fertigungsprozess nicht alle exakt gleich lang sind und nicht alle Bonddrähte die gleiche, bogenförmige Form erhalten, sind die parasitären Induktivitäten und Kapazitäten, die durch Verbindung in Drahtbondtechnik entstehen, bei ansonsten gleichen Schaltungen unterschiedlich groß, so dass eine vollständige Kompensation dieser parasitären Effekte nicht möglich ist.such Multi-chip modules that are known in the art are constructed such that on a printed circuit board or a substrate, as a mechanical support serves, applied components and electrically connected to each other. For contacting the components wire bonding is often used, in the case of short, electrically conductive bonding wires contacts electrically connected to each other. Here are the bonding wires between the two contacts usually arcuately shaped, causing so-called Loops arise. When used in high frequency circuits have these loops produced in wire bond technology parasitic inductances and capacities that need to be compensated. Because the bonding wires not all of the same length in the manufacturing process and not all bonding wires the same, arcuate Getting shape are the parasitic ones inductors and capacities, which arise by connection in Drahtbondtechnik, otherwise the same Circuits of different sizes, so that a complete Compensation of these parasitic effects not possible is.
Kern und Vorteile der ErfindungCore and benefits of invention
Der Kern der vorliegenden Erfindung ist es dementsprechend, eine elektrische Schaltung sowie ein Verfahren zur Herstellung dieser elektrischen Schaltung anzugeben, bei dem elektrische Verbindungen zwischen Bauelementen reproduzierbare parasitäre Effekte aufweisen und bei dem empfindliche Bauelemente eine hohe mechanische Beanspruchung aushalten können und dennoch kostengünstig hergestellt werden können.Of the Correspondingly, the core of the present invention is an electrical Circuit and a method for producing this electrical circuit specify at the electrical connections between components reproducible parasitic Have effects and the sensitive components a high can withstand mechanical stress and yet produced inexpensively can be.
Erfindungsgemäß wird dieses durch die Merkmale der unabhängigen Ansprüche gelöst. Vorteilhafte Weiterbildungen und Ausgestaltungen ergeben sich aus den Unteransprüchen.According to the invention this by the characteristics of the independent claims solved. Advantageous developments and refinements emerge the dependent claims.
Vorteilhafter Weise ist vorgesehen, dass die Bauelemente in der Vergussmasse derart versenkt sind, dass die elektrischen Anschlüsse der Bauelemente nicht mit Vergussmasse bedeckt sind. Durch die Versenkung der Bauelemente in der Vergussmasse erreicht man, dass diese mechanisch miteinander verbunden werden und auch empfindliche Bauelemente gegen mechanische Beanspruchung geschützt sind. Da die Bauelemente derart versenkt sind, dass die Seite der Bauelemente mit den elektrischen Anschlüssen möglichst plan aus der Vergussmasse herausragen, ist es möglich, mittels einer Schicht von elektrischen Leiterbahnen die elektrischen Anschlüsse der Bauelemente miteinander zu verbinden.Favorable It is provided that the components in the potting compound so sunk that the electrical connections of the components are not with Casting compound are covered. By sinking the components in the potting compound it is achieved that these mechanically with each other be connected and sensitive components against mechanical Stress protected are. Since the components are sunk in such a way that the side of the Components with the electrical connections as plan as possible from the potting compound stand out, it is possible by means of a layer of electrical conductors, the electrical connections connect the components together.
Weiterhin ist es vorteilhaft, dass mittels mechanischem Bohren und/oder mittels Laserbohren Sacklöcher und/oder durchgehende Löcher in die Vergussmasse gebohrt werden, die zur Herstellung elektrischer Kontakte metallisiert werden. Durch mechanisches Bohren oder durch Laserbohren ist es möglich, mittels Sacklöcher oder mittels durchgehender Löcher, die anschließend mit elektrisch leitendem Material, vorteilhafter Weise mittels eines flüssigen Metalls, metallisiert oder aufgefüllt werden, elektrische Verbindungen, oft auch als Vias bezeichnet, mit tiefer liegenden Schichten oder mit der Rückseite des Vergussmassestückes herzustellen.Farther it is advantageous that by means of mechanical drilling and / or by means of Laser drilling blind holes and / or through holes be drilled into the potting compound, which is used for the production of electrical Metalized contacts. By mechanical drilling or by Laser drilling it is possible by means of blind holes or by means of through holes, the following with electrically conductive material, advantageously by means of a liquid metal, metallized or filled electrical connections, often referred to as vias, with deeper layers or with the back of the Vergussmassestückes produce.
Weiterhin ist es vorteilhaft, dass auf mindestens einer Schicht Leiterbahnen, die zur Verbindung der in der Vergussmasse versenkten Bauelemente aufgebracht wird, mindestens eine Schicht aus Dielektrikum aufzubringen. Durch die Schicht aus Dielektrikum, die in vorteilhafter Weise als Kunststoff mit angepasster Dielektrizitätszahl εr ausgeführt sein kann, werden sowohl die elektrischen Leiterbahnen mechanisch geschützt, aber auch die Betriebsfrequenz der elektrischen Leiterbahnen für die Hochfrequenzsignale an die entsprechende Betriebsfrequenz angepasst, indem die Dicke der Dielektrikumsschicht auf die Betriebsfrequenz abgestimmt wird. Die angepasste Dielektrizitätszahl εr liegt vorteilhafterweise zwischen 2 und 4.Furthermore, it is advantageous that at least one layer of dielectric material is applied to at least one layer of printed conductors which is applied to connect the components embedded in the casting compound. Due to the layer of dielectric, which can be embodied advantageously as plastic with a suitable dielectric constant ε r , both the electrical interconnects are mechanically protected, but also the operating frequency of the electrical interconnects for the high-frequency signals adapted to the corresponding operating frequency by the thickness of the dielectric layer is tuned to the operating frequency. The adapted dielectric constant ε r is advantageously between 2 and 4.
Weiterhin ist es vorteilhaft, dass zur elektrischen Kontaktierung der Bauelemente mehrere Leiterbahnschichten übereinander vorgesehen sind, die durch Schichten aus Dielektrikum voneinander getrennt sind. Durch das Vorsehen mehrerer Leiterbahnschichten übereinander ist es möglich, beispielsweise eine Kontaktschicht zur Massekontaktierung vorzusehen und weitere Leiterbahnschichten zur Verbindung der elektrischen Anschlüsse der Bauelemente vorzusehen. Durch Schichten aus Dielektrikum, das vorteilhafter Weise als Kunststoff mit angepasster Dielektrizitätszahl εr ausgeführt sein kann, werden die Metallisierungsebenen, die durch Strukturierung der Metallisierung zu Leiterbahnen strukturiert wurden, elektrisch gegeneinander isoliert sowie eine Ausbreitung hoher Betriebsfrequenzen auf den Leitungen ermöglicht. Da bei dieser Technik auf Drahtbondtechnik verzichtet werden kann, entstehen keinerlei Drahtloops, die individuell verschiedene parasitäre induktive oder kapazitive Effekte aufweisen, die in Folge unterschiedlicher Formen der Drahtloops auch unterschiedlich stark ausfallen können.Furthermore, it is advantageous that several interconnect layers are provided one above the other for electrical contacting of the components, which are separated from one another by layers of dielectric. By providing a plurality of interconnect layers one above the other, it is possible to provide, for example, a contact layer for grounding and to provide further interconnect layers for connecting the electrical connections of the components. By layers of dielectric, which can be advantageously carried out as a plastic with an adapted dielectric constant ε r , the metallization levels, which were structured by structuring the metallization into conductor tracks, are electrically insulated from each other and enable a propagation of high operating frequencies on the lines. Since wire bonding technology can be dispensed with in this technique, there are no wire loops that individually exhibit different parasitic inductive or capacitive effects, which can also vary in severity as a result of different forms of the wire loops.
Weiterhin ist es vorteilhaft, dass auf der obersten Leiterbahnschicht zusätzliche elektrische Bauelemente vorsehbar sind. Auf der obersten Leiterbahnschicht können Kontaktflächen vorgesehen sein, auf denen zusätzliche Bauelemente, beispielsweise mittels Löten oder Kleben befestigt werden können, wodurch die Anzahl der Bauelemente nicht durch den räumlichen Platz der Vergussmasse begrenzt ist.Farther it is advantageous that additional on the top conductor layer electrical components are providable. On the topmost conductor layer can contact surfaces be provided on which additional Components can be attached, for example by means of soldering or gluing, whereby the number of components not by the spatial space of the potting compound is limited.
Weiterhin ist vorteilhaft, dass vor dem Aufbringen der Leiterbahnen Löcher oder Vertiefungen für Durchkontaktierungen in der Vergussmasse herstellbar sind.Farther is advantageous that before applying the conductor tracks holes or Wells for Through holes can be produced in the potting compound.
Weiterhin ist es vorteilhaft, dass auf die Leiterbahnen und/oder zwischen den Leiterbahnschichten ein Dielektrikum aufgebracht wird. Dieses Dielektrikum ist beispielsweise ein Kunststoff mit angepasster Dielektrizitätszahl εr, deren Dicke entsprechend der vorgesehenen Betriebsfrequenz der elektrischen Leitungen ausgelegt ist.Furthermore, it is advantageous that a dielectric is applied to the interconnects and / or between the interconnect layers. This dielectric is, for example, a plastic with an adapted dielectric constant ε r , the thickness of which is designed in accordance with the intended operating frequency of the electrical lines.
Vorteilhafter Weise sind auf der einen oder den mehreren Schichten von Leiterbahnen weitere Bauelemente aufbringbar.Favorable Way are on one or more layers of tracks additional components can be applied.
Weitere Merkmale, Anwendungsmöglichkeiten und Vorteile der Erfindung ergeben sich aus der nachfolgenden Beschreibung von Ausführungsbeispielen der Erfindung, die in den Figuren der Zeichnung dargestellt sind. Dabei bilden alle beschriebenen oder dargestellten Merkmale für sich oder in beliebiger Kombination den Gegenstand der Erfindung, unabhängig von ihrer Zusammenfassung in den Patentansprüchen oder deren Rückbeziehung sowie unabhängig von ihrer Formulierung bzw. Darstellung in der Beschreibung bzw. in den Zeichnungen.Further Features, applications and advantages of the invention will become apparent from the following description of exemplary embodiments of the invention, which are illustrated in the figures of the drawing. All described or illustrated features form for themselves or in any combination, the subject matter of the invention, regardless of their summary in the claims or their dependency as well as independently from their formulation or presentation in the description or in the drawings.
Zeichnungendrawings
Nachfolgend wird ein Ausführungsbeispiel der Erfindung anhand von Zeichnungen erläutert. Es zeigenfollowing is an embodiment of Invention explained with reference to drawings. Show it
Beschreibung von Ausführungsbeispielendescription of exemplary embodiments
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Claims (11)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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DE102005003125A DE102005003125A1 (en) | 2005-01-21 | 2005-01-21 | High-frequency electrical circuit for multi-chip module, has electrical components mechanically connected with each other by sealing compound and provided with conductive strip layers, which electrically connects components with each other |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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DE102005003125A DE102005003125A1 (en) | 2005-01-21 | 2005-01-21 | High-frequency electrical circuit for multi-chip module, has electrical components mechanically connected with each other by sealing compound and provided with conductive strip layers, which electrically connects components with each other |
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DE102005003125A1 true DE102005003125A1 (en) | 2006-07-27 |
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DE102005003125A Withdrawn DE102005003125A1 (en) | 2005-01-21 | 2005-01-21 | High-frequency electrical circuit for multi-chip module, has electrical components mechanically connected with each other by sealing compound and provided with conductive strip layers, which electrically connects components with each other |
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DE (1) | DE102005003125A1 (en) |
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