WO2014202282A1 - Carte de circuits imprimés - Google Patents

Carte de circuits imprimés Download PDF

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Publication number
WO2014202282A1
WO2014202282A1 PCT/EP2014/059632 EP2014059632W WO2014202282A1 WO 2014202282 A1 WO2014202282 A1 WO 2014202282A1 EP 2014059632 W EP2014059632 W EP 2014059632W WO 2014202282 A1 WO2014202282 A1 WO 2014202282A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
electronic components
printed circuit
conductor
connection
Prior art date
Application number
PCT/EP2014/059632
Other languages
German (de)
English (en)
Inventor
Michael Pechtold
Thomas Hofmann
Johannes Bock
Original Assignee
Conti Temic Microelectronic Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conti Temic Microelectronic Gmbh filed Critical Conti Temic Microelectronic Gmbh
Publication of WO2014202282A1 publication Critical patent/WO2014202282A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10166—Transistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10477—Inverted
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10522—Adjacent components

Definitions

  • the invention relates to a circuit carrier, such as a printed circuit board, with inner and outer conductor tracks and at least two electronic components. Furthermore, the invention relates to a method for producing a printed circuit board.
  • Circuit boards as circuit carriers of electronic circuits and components, such as control devices, sensors, in the
  • FIG. 1 For a better overview, the illustration of a single MOSFET can be seen in FIG.
  • Such an equidirectional orientation of the transistors 4, 5 in the circuit board 1 in the interconnection of this to a semiconductor bridge H has the disadvantage that the upper source terminal 4b of a transistor 4 to the lower gate terminal 5c of other transistor 5 only by means of a compound 8 of the upper surface side Ol with the lower surface side 02 (for example in the form of a
  • the transistors 4 and 5 are connected via further leads 11 to the terminals 4d, 5d in the upper conductor tracks 2.
  • the invention has for its object to provide a very compact circuit board with at least two electronic components with the shortest possible links. Moreover, it is an object of the invention to provide a method for producing such a printed circuit board.
  • the printed circuit board according to the invention comprises inner and outer conductor tracks, which are arranged on at least one conductor layer, and at least two internal, electronic components whose connection pins are connected to one of the conductor tracks, wherein the at least two electronic components are arranged in the circuit board in that their connection pins to be connected to one another are directed in the direction of a surface side of the printed circuit board.
  • the known from the prior art vias and long links of the electronic components can be significantly reduced or even avoided.
  • the electrical paths or links are shorter by "flipping" one of the two electronic components, such as a transistor
  • the interconnection of the electronic components is on the same board level ("ply") and / or on the same surface side of the board ⁇ terplatte possible.
  • an embodiment of the invention provides that further connection pins of the at least two electronic components to be connected to one another, in particular transistors of a bridge circuit, by means of a component or a component, such as a ceramic capacitor, from another circuit part, eg Supply voltage, are decoupled.
  • the connection pins to be decoupled and the connection pins of the at least two electronic components to be directly connected to one another on opposite surface sides of the circuit board are decoupled or connected. This allows a simple and fast assembly and contacting during manufacture.
  • the at least two electronic components are each arranged in an associated molded cavity and are electrically connected to conductor tracks of at least one conductor layer, wherein the connection pins of the two electronic components to be connected to one another are connected in a conductor layer to a conductor track.
  • the electronic components are spaced from each other.
  • the respective connection pin of the electronic component (s) is designed as a bonding connection, which branches off in the manner of an arm from the associated electronic component and whose free end is contacted with one of the conductor tracks.
  • the connection pins are contacted in particular in connection with several Lei ⁇ terbahnen in a conductor layer with the conductor tracks, in order to avoid plated-through holes.
  • At least one carrier layer in particular a copper carrier above and / or below the electronic Be arranged component.
  • a carrier layer formed of copper can serve as a conductor track and / or connection element, whereby the electrical connection links are further reduced.
  • the inventive method for producing a printed circuit board with internal and / or external conductor tracks and at least two internal electronic components provides that in the circuit board for each electronic component introduced a cavity, in particular lasered, and the electronic components in this cavity can be arranged such that their connection pins to be connected together are directed in the direction of a surface side of the circuit board and that these connecting pins to be connected to one of the conductor tracks of a conductor layer are connected and fixed together and then optionally the cavities with the positioned therein and electrically connected electronic components.
  • Printed circuit board connected to conductor tracks of a conductor layer and decoupled by means of a component between these interconnects.
  • the method is particularly simple and inexpensive and avoids vias.
  • FIG. 4 to 9 show schematically different sectional views.
  • the interconnects 2 ⁇ , 3 ⁇ are formed as copper surfaces or tracks, layers and serve the electrical connection of at least two electronic components 4 ⁇ and 5 ⁇ .
  • the electronic components 4 ⁇ and 5 ⁇ are inside lying in the circuit board 1 ⁇ in ⁇ tegrated.
  • further electronic components not shown in detail may be arranged inside and / or outside.
  • the printed circuit board 1 ⁇ may be formed as a single-layer or multi- layered printed circuit board with inner and / or outer conductor tracks 2 ⁇ and 3 ⁇ .
  • the electronic components 4 ⁇ , 5 ⁇ may be Halbleitererbauele ⁇ elements, such as transistors, power transistors, sensors, diodes, capacitors and / or control devices.
  • the electronic components 4 ⁇ , 5 for connecting the two internal electronic components 4 ⁇ , 5 in particular their connection pins 4a x to 4c 5a ⁇ to 5c with the outer conductor tracks 2 ⁇ , 3 in particular with terminals 4d 4e 5e 5d x in the outer tracks 2 ⁇ , 3 are inner conductor tracks 10 or leads 11 ⁇ provided.
  • the two internal electronic components 4 ⁇ and 5 ⁇ are in the embodiment of Figure 4 transistors which are connected to a Half bridge ⁇ ⁇ by means of the outer conductor tracks 2 ⁇ , 3 ⁇ and the inner leads 11 ⁇ are connected, as shown by the circuit in Figure 5.
  • the transistors are power transistors, in particular so-called MOSFETs.
  • connection pins 4b ⁇ and 5c ⁇ to be electrically connected are by means of the inner lead 11 ⁇ or an electrically conductive layer 6, in particular an electrically conductive adhesive, with the relevant terminals 4e ⁇ or 5f ⁇ in the conductor 3 ⁇ of a conductor layer L2 electrically connected.
  • the electrically conductive layer 6 ⁇ serves the material-conclusive attachment of the respective electronic component 4 ⁇ , 5 ⁇ on the copper layer of the conductor 2 ⁇ or 3 ⁇ .
  • the electronic components 4 5 ⁇ may be integrated in the circuit substrate or circuit board 1 ⁇ both as packaged as well as a "bare the" components.
  • Figure 6 shows in detail the connection of the connecting pins 4c ⁇ and 5b ⁇ of at least two electronic components 4 ⁇ or 5 ⁇ by means of the component 9 ⁇ or a decoupling element, in ⁇ particular of a capacitor on the outside of the surface ⁇ side Ol ⁇ on the associated terminals 4f ⁇ and 5f ⁇ of upper tracks 2 ⁇ in the one conductor layer LI is attached by means of an electrically conductive layer 6 in particular a elekt ⁇ driven conductive adhesive.
  • connection pins 4c ⁇ and 5b ⁇ to be decoupled and their terminals 4f ⁇ and 5e ⁇ in the upper interconnects 2 ⁇ and the connection pins 4b ⁇ and 5c ⁇ and their interconnected directly to one another Terminals 4e ⁇ and 5f x arranged on opposite surface sides of Ol ⁇ and 02 ⁇ of the circuit board 1 ⁇ .
  • the following component carrier is in particular at least one conductor layer, which is arranged above and / or below the electronic component 4 ⁇ and 5 ⁇ and at least one of the interconnects 2 3 ⁇ or 10 and one of the adjacent printed circuit board insulating LPl to LPm is formed.
  • Figure 7 shows an embodiment for a multilayer printed circuit board 1 ⁇ having a plurality of insulating layers LPL to LPm and a plurality of outer strip conductors 2 ⁇ 3 ⁇ and internal interconnects 10, in particular so-called copper intermediate layers in multiple conductor layers LI to Ln.
  • the at least two internal electronic components 4 5 ⁇ are integrated into the second insulating layer LP2.
  • the electronic components 4 ⁇ and 5 ⁇ are arranged spaced from each other.
  • connection pin 4a ⁇ to 4c ⁇ and 5a ⁇ to 5c ⁇ of the electronic components 4 ⁇ and 5 ⁇ is formed as a bond connection, which in the manner of an arm of the associated electronic component 4 ⁇ and 5 ⁇ goes off and whose free end is contacted with one of the conductor tracks 2 ⁇ , 3 ⁇ or 10.
  • the electronic components 4 ⁇ , 5 ⁇ on a component carrier for example a copper carrier
  • the component carrier is aligned and pressed "face up” or “face down” during the laying / stacking of the conductor layers LI to Lm and the insulating layers LP1 to LPm.
  • the component carrier is contacted by drilling and etching processes using micro-vias.
  • the electronic components 4 ⁇ , 5 ⁇ be anorialiert also by drilling and etching processes by micro-vias (supply lines 11 and ⁇ connections 4d x to 4f ⁇ and 5d x to 5f ⁇ .
  • Figure 8 shows an alternative embodiment for a multilayer printed circuit board 1 ⁇ .
  • the at least two internal electronic components 4 5 ⁇ are integrated into the second conductor layer L2.
  • the electronic components 4 ⁇ and 5 ⁇ are introduced into an associated cavity K of a component carrier and assembled and fixed electrically conductive, for example by soldering, sintering, Leitkleben.
  • the component carrier is aligned and pressed "face up” or “face down” when laying / stacking the conductor layers LI to Ln and the insulating layers LP1 to LPm.
  • the at least two electronic components 4 ⁇ and 5 ⁇ may be arranged in each case in an associated molded cavity K and electrically connected to inner and / or outer conductor tracks 2 ⁇ , 3 ⁇ and 10 at least one conductor layer LI to Ln.
  • the connection pins 4b ⁇ and 5c ⁇ of the two electronic components 4 ⁇ and 5 ⁇ to be connected to one another are connected in a conductor layer L3 to a conductor track 4e ⁇ .
  • the exemplary embodiment according to FIG. 8 has the advantage over the exemplary embodiment according to FIG. 7 that no openings / "windows" in the laminate of the insulating layers LP1 to LPm in the area of the electronic components 4 are present when the prepreg layers or insulating layers LP1 to LPm are laid ⁇ , 5, for example, a chip must be.
  • the disadvantage is that the components or electronic components 4 ⁇ , 5 ⁇ in the embodiment of Figure 8 in a cavity K of one of the inner conductor tracks 10 of the respective conductor layer L2 and thus the copper must be assembled.
  • FIG. 9 shows a further alternative exemplary embodiment of a multilayer printed circuit board 1 ⁇ with three insulating layers LP1 to LP3, of which two insulating layers LP1 and LP2 directly adjoin each other without intermediate conductor tracks, and with inner and outer conductor tracks 2 3 10 in three conductor layers LI to L3 are connected.
  • an electrically insulating adhesive 7 or other suitable electrically insulating material in the manner of a layer ordered on ⁇ .
  • the electronic components 4 ⁇ , 5 ⁇ are glued "face up” or “face down” on a Cu carrier film as a component carrier.
  • the structure of the inner layers and thus the iso ⁇ lierlagen LP1 and LP2 are laid and pressed.
  • the core is drilled at the contact points and by chemical processes, the micro-via connections between the inner layers, the insulating layers LP1 to LP2 and the components 4 ⁇ , 5 ⁇ (top and bottom) generated.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne une carte de circuits imprimés (1`) pourvue de tracés conducteurs (2`, 3`, 10) situés à l'intérieur et à l'extérieur, lesquels sont disposés sur au moins une couche conductrice (L1 à Ln), et d'au moins deux composants électroniques (4`, 5`) situés à l'intérieur et reliés à l'un des tracés conducteurs (2`, 3`, 10) au moyen d'au moins une broche de raccordement (4a` à 4c`, 5a` à 5c`). Les deux composants électroniques (4`, 5`) ou plus sont disposés dans la carte de circuits imprimés (1`) de telle manière que leurs broches de raccordement (4a` à 4c` 5a` bis 5c`) destinées à être reliées entre elles sont orientées en direction d'une face superficielle (O1` ou O2`) de la carte de circuits imprimés (1`).
PCT/EP2014/059632 2013-06-20 2014-05-12 Carte de circuits imprimés WO2014202282A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102013211667.5 2013-06-20
DE102013211667 2013-06-20

Publications (1)

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WO2014202282A1 true WO2014202282A1 (fr) 2014-12-24

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016150662A1 (fr) * 2015-03-26 2016-09-29 Epcos Ag Support à fonction de refroidissement passif pour un composant semi-conducteur
DE102018111989A1 (de) * 2018-05-18 2019-11-21 Rogers Germany Gmbh Elektronikmodul und Verfahren zur Herstellung desselben
EP3907760A1 (fr) * 2020-05-08 2021-11-10 Infineon Technologies Austria AG Module semi-conducteur
DE102020207279A1 (de) 2020-06-10 2021-12-16 Vitesco Technologies Germany Gmbh Leiterplatte mit einem eingebetteten Halbleiterbauelement, Verfahren zum Herstellen einer Leiterplatte
EP4181636A4 (fr) * 2020-07-07 2024-02-28 Shennan Circuits Co., Ltd. Carte de circuit imprimé et son procédé de fabrication

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US20050161785A1 (en) * 2004-01-28 2005-07-28 Tetsuya Kawashima Semiconductor device
US20070057366A1 (en) * 2005-09-14 2007-03-15 Masashi Katsumata Semiconductor IC-embedded module
US20110069448A1 (en) * 2008-05-30 2011-03-24 Weichslberger Guenther Method for integrating at least one electronic component into a printed circuit board, and printed circuit board
US20110108971A1 (en) * 2009-11-10 2011-05-12 Infineon Technologies Ag Laminate electronic device
US20130003309A1 (en) * 2011-06-30 2013-01-03 Stmicroelectronics S.R.L. Half-bridge electronic device with common auxiliary heat sink

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050161785A1 (en) * 2004-01-28 2005-07-28 Tetsuya Kawashima Semiconductor device
US20070057366A1 (en) * 2005-09-14 2007-03-15 Masashi Katsumata Semiconductor IC-embedded module
US20110069448A1 (en) * 2008-05-30 2011-03-24 Weichslberger Guenther Method for integrating at least one electronic component into a printed circuit board, and printed circuit board
US20110108971A1 (en) * 2009-11-10 2011-05-12 Infineon Technologies Ag Laminate electronic device
US20130003309A1 (en) * 2011-06-30 2013-01-03 Stmicroelectronics S.R.L. Half-bridge electronic device with common auxiliary heat sink

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016150662A1 (fr) * 2015-03-26 2016-09-29 Epcos Ag Support à fonction de refroidissement passif pour un composant semi-conducteur
US10980105B2 (en) 2015-03-26 2021-04-13 TDK Electroncis AG Carrier with a passive cooling function for a semiconductor component
DE102018111989A1 (de) * 2018-05-18 2019-11-21 Rogers Germany Gmbh Elektronikmodul und Verfahren zur Herstellung desselben
DE102018111989B4 (de) 2018-05-18 2024-05-08 Rogers Germany Gmbh Elektronikmodul und Verfahren zur Herstellung desselben
EP3907760A1 (fr) * 2020-05-08 2021-11-10 Infineon Technologies Austria AG Module semi-conducteur
US11973071B2 (en) 2020-05-08 2024-04-30 Infineon Technologies Austria Ag Semiconductor module
DE102020207279A1 (de) 2020-06-10 2021-12-16 Vitesco Technologies Germany Gmbh Leiterplatte mit einem eingebetteten Halbleiterbauelement, Verfahren zum Herstellen einer Leiterplatte
EP4181636A4 (fr) * 2020-07-07 2024-02-28 Shennan Circuits Co., Ltd. Carte de circuit imprimé et son procédé de fabrication

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