CN105448880A - Multi-core single-lapping, tiling and core-sandwiching packaging structure and technological method thereof - Google Patents

Multi-core single-lapping, tiling and core-sandwiching packaging structure and technological method thereof Download PDF

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Publication number
CN105448880A
CN105448880A CN201510991138.7A CN201510991138A CN105448880A CN 105448880 A CN105448880 A CN 105448880A CN 201510991138 A CN201510991138 A CN 201510991138A CN 105448880 A CN105448880 A CN 105448880A
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China
Prior art keywords
lead frame
horizontal segment
chip
frame
encapsulating structure
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CN201510991138.7A
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Inventor
刘恺
梁志忠
王赵云
陈益新
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CN201510991138.7A priority Critical patent/CN105448880A/en
Publication of CN105448880A publication Critical patent/CN105448880A/en
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract

The invention relates to a multi-core single-lapping, tiling and core-sandwiching packaging structure and a technological method thereof. The technological method comprises the following steps of step 1, providing a first lead frame; step 2, coating solder paste on the first lead frame; step 3, implanting a first core on the solder paste of the first lead frame; step 4, providing a second lead frame and coating the solder paste on the second lead frame; step 5, enabling the second lead frame to be in press fit with the first core; step 6, performing reflow soldering; step 7, coating the solder paste on the second lead frame; step 8, implanting a second core on the second lead frame; step 9, providing a third lead frame and coating the solder paste on the third lead frame; step 10, enabling the third lead frame to be in press fit with the second chip; step 11, performing reflow soldering; step 12, packaging by using a molding compound; and step 13, cutting or punching. The multi-core single-lapping, tiling and core-sandwiching packaging structure and the technological method thereof have the beneficial effects that the heat dissipation capability of a product is increased, the packaging resistance of the product is reduced, the whole product can be molded integrally, and the production efficiency is high.

Description

A kind of multi-chip list takes tiling sandwich encapsulating structure and process thereof
Technical field
The present invention relates to a kind of multi-chip list and take tiling sandwich encapsulating structure and process thereof, belong to technical field of semiconductor encapsulation.
Background technology
In recent years, along with electronic product is constantly pursued power density, no matter be Diode(diode) or Transistor(triode) encapsulation, the MOS product especially in Transistor is just towards more high-power, smaller szie, more fast, better trend of dispelling the heat is in development.The disposable manufacture also slowly even more disposable encapsulation technology spurt of the highly difficult low cost of the high density of large regions and the challenge towards zonule by single encapsulation technology of encapsulation.
Therefore, also more requirement has been had to the structure of the various electrical properties being encapsulated in parasitic resistance, electric capacity, inductance etc. of MOS product, encapsulation, the dissipation of heat sexuality of encapsulation, the reliability aspect of encapsulation and highly difficult disposable encapsulation technology aspect.
Traditional Diode(diode) and Transistor(triode) or the encapsulation of MOS product is general according to product performance, the difference of power and the Consideration of cost, the bonding wire mode that make use of gold thread, silver alloy wire, copper cash, aluminum steel and aluminium strip as the main interconnection technique of chip and interior pin, thus realizes electrical connection.But the performance of the technical approach of bonding wire to product is present in restriction and the defect of the following aspects:
One, encapsulation and the restriction of manufacture view and defect:
1), Weldability (Bondability) aspect: usually can change because of the parameter sheet of the change of Metal wire material, metal pins material and equipment and instrument, the change of performance and precision and maintain and correct manage and the rosin joint of the first solder joint of causing and the second solder joint faying face, come off, puzzlement that breakpoint, neck crack, collapse line and short circuit etc. are all, yield cannot promote, cost cannot decline, the instability of reliability to result in encapsulation;
2), disposable high-density encapsulation technology aspect: traditional mutual contact mode is nearly all adopt the welding manner that single chips one chips repeats load, high temperature ultrasonic single line single line adopted by wire in matrix type die-attach area.And be like this loader of specialty in situation, ball bonding wire bonder, bonding aluminum steel/machinery equipment such as aluminium strip machine or copper sheet overlapping machine repetitive operation more at a high speed all cannot improving production efficiency, unit cost cannot be reduced, also because equipment constantly promotes the same unsteadiness also improving manufacture of speed of production.
Two, the restriction of the special aspect of performance of encapsulating products and defect:
1), dissipation of heat aspect: traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS, general is all coated by plastic packaging material, external pin is only stayed to be exposed to outside plastic-sealed body, due to the material that plastic packaging material itself is not a kind of thermal conductance, so traditional Diode(diode) and Transistor(triode) or operationally the produced heat of MOS product is difficult to dissipate by plastic packaging material the packaging body of plastic packaging material material, fine wire can only be relied on to be interconnected at the dissipation that heat energy helped by metal pins material, but the dissipation capability of the approach of this dissipation of heat to heat is very limited, form the resistance of the dissipation of heat on the contrary,
2), resistivity (Resistivity) aspect: resistivity (resistivity) is used to the physical quantity representing various material resistance characteristic as you know.When temperature is certain, have formula R=ρ l/s ρ to be wherein exactly resistivity, l is the length of material, and s is area.Can find out, the resistance sizes of material is proportional to the length of material, and is inversely proportional to its area.Definition by the known resistivity of above formula: ρ=Rs/l.Traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS, bonding wire is adopted to be formed interconnected, can clearly know thus wire for performing power supply or signal can because, the length of conductor material and the change of sectional area and have influence on the size of resistivity and the loss of contact resistance, the product impact being especially applied in power aspect is obvious especially.
For solving the problem, industry is to traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS improves, replace bonding wire with metal tape, metal splint, reduce the ability that packaged resistance, inductance and expectation improve the dissipation of heat.
As shown in Figure 1, be the existing MOS encapsulating structure of one, in this structure, lead frame 11 comprises pipe core welding disc and pin, and the pipe core welding disc of lead frame 11 is implanted the first chip 12, second chip 13.The source electrode of the first chip 12 is electrically coupled to lead frame 11 by the first metal splint 14, and the grid of the first chip 12 is electrically coupled to lead frame 11 by the first metal bonding wire 16.The source electrode of the second chip 13 is electrically coupled to lead frame 11 by the second metal splint 15, and the grid of the second chip 13 is electrically coupled to lead frame 11 by the second metal bonding wire 17.Carry out again encapsulating, cut, the subsequent handling such as test.This MOS encapsulating structure metal splint instead of the bonding wire in conventional MOS encapsulation, reduce partial encapsulation resistance, but still there is following defect: first, the drain electrode of this MOS encapsulating structure chips, source electrode and grid and lead frame are formed interconnectedly will use different equipment respectively, processing procedure is complicated, and the acquisition cost of equipment is higher; Secondly, this MOS encapsulating structure, when metal splint and metal bonding wire are coupled on chip and pin, can only carry out by a chips, cannot whole piece one-body molded, manufacture efficiency is lower.
Summary of the invention
Technical problem to be solved by this invention provides a kind of multi-chip list to take tiling sandwich encapsulating structure and process thereof for above-mentioned prior art, whole piece product can be one-body molded, production efficiency is high, technique is simple, can reduce costs, and there is good thermal diffusivity and lower packaged resistance and inductance.
The present invention's adopted technical scheme that solves the problem is: tiling sandwich encapsulating structure taken by a kind of multi-chip list, it comprises the first lead frame, second lead frame, 3rd lead frame, first chip and the second chip, described second lead frame and the 3rd lead frame are Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, first middle linkage section and first time horizontal segment, described the 3rd Z-shaped lead frame comprises horizontal segment on second, second middle linkage section and second time horizontal segment, described first chip gripper to be located on the first lead frame and first between horizontal segment, the front and back of described first chip is electrically connected respectively by horizontal segment on tin cream and first and the first lead frame, described second chip gripper to be located on first time horizontal segment and second between horizontal segment, the front and back of described second chip is respectively by horizontal segment on tin cream and second and first time horizontal segment and electric connection, described first lead frame, second lead frame and the 3rd lead frame outer encapsulating have plastic packaging material, described first lead frame lower surface and first time horizontal segment lower surface flush and are all exposed to outside plastic packaging material, described second time horizontal segment lower surface is set up on the first lead frame upper surface.
Described first lead frame, the second lead frame and the 3rd lead frame are general frame.
A process for tiling sandwich encapsulating structure taken by multi-chip list, and described method comprises the steps:
Step one, provide the first lead frame;
Step 2, apply tin cream in the first lead frame Ji Dao region by the mode of screen printing;
The tin cream of step 3, the first lead frame Ji Dao region coating in step 2 implants the first chip;
Step 4, provide the second lead frame, described second lead frame is Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, the first middle linkage section and first time horizontal segment, and on first of the second lead frame, the lower surface of horizontal segment applies tin cream by the mode of screen printing;
Step 5, horizontal segment on first of the second lead frame is pressed together on the first chip of the first lead frame upper surface, after pressing, the first lead frame and the second lead frame form general frame, and the first lead frame lower surface and the second lead frame first time horizontal segment lower surface flushes;
Step 6, by step 5 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 7, complete Reflow Soldering after, apply tin cream at the upper surface of first time horizontal segment of the second lead frame by the mode of screen printing;
The tin cream of step 8, first time horizontal segment upper surface coating of the second lead frame in step 7 implants the second chip;
Step 9, provide the 3rd lead frame, described 3rd lead frame is Z-shaped, described the 3rd Z-shaped lead frame comprises horizontal segment on second, the second middle linkage section and second time horizontal segment, and on second of the 3rd lead frame, horizontal segment lower surface and second time horizontal segment lower surface apply tin cream by the mode of screen printing;
Step 10, horizontal segment on second of the 3rd lead frame is pressed together on the second chip of first time horizontal segment upper surface of the second lead frame, and second time horizontal segment lower surface of the 3rd lead frame is set up on the first lead frame upper surface, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame;
Step 11, by step 10 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 12, plastic packaging material is adopted to carry out plastic packaging the general frame of step 11 after Reflow Soldering;
Step 13, semi-finished product step 12 being completed plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, and tiling sandwich encapsulating structure taken by obtained multi-chip list.
Described first lead frame pressing second lead frame forms general frame, can implement after the second lead frame implants the second chip.
The material of described first lead frame, the second lead frame and the 3rd lead frame can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.
Described first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
The thermal coefficient of expansion CTE of the thermal coefficient of expansion CTE of described pressing plate material and the first lead frame, the second lead frame and the 3rd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
Described step 2, step 4 and step 9 are carried out by different platform simultaneously.
Compared with prior art, the invention has the advantages that:
1, a kind of multi-chip list of the present invention is taken the source electrode of the second lead frame of tiling sandwich encapsulating structure and MOS chip direct with the 3rd lead frame and grid and is formed and be electrically connected, instead of in conventional MOS chip package and utilize metal welding line to form interconnected technique, substantially reduce packaged resistance, technology of the present invention can reduce more than at least 30% than the packaged resistance of conventional package design;
2, a kind of multi-chip list of the present invention is taken the second lead frame of tiling sandwich encapsulating structure and the 3rd lead frame and is directly formed by the source electrode of tin cream and MOS chip and grid and be electrically connected, reduce or remit the interconnected operation of metal bonding wire completely, save the cost such as the equipment purchasing of the interconnected operation of metal bonding wire, operation material completely.And the second lead frame of the present invention and the 3rd lead frame are all that whole piece is integrated, form with chip that to be electrically connected also be that whole piece one step completes, compared with forming interconnected technique with conventional metals bonding wire, the interconnected chip one by one of sheet metal, technique is comparatively simple, and production efficiency is significantly improved;
3, a kind of multi-chip list of the present invention is taken tiling sandwich encapsulating structure due to upper and lower two surfaces of chip and is all directly contacted with lead frame, the heat produced during chip operation sheds by lead frame, and the first lead frame lower surface of the present invention and the second leadframe part lower surface are directly exposed to outside plastic packaging material, multi-chip list of the present invention is taken tiling sandwich encapsulating structure and is had good heat dispersion; And the present invention can again according to product power, heat conduction or the difference of heat radiation additional radiator on lead frame freely, in order to increase the ability of the product dissipation of heat further;
4, a kind of multi-chip list of the present invention is taken tiling sandwich encapsulating structure and is used upper lower platen to push down general frame to carry out Reflow Soldering, framework to be not easily heated the cohesion institute jack-up of cooling procedure after melting by tin cream when Reflow Soldering, ensure the total height of frame structure, prevent movement or the rotation of chip, and can guarantee that framework exposes the coplanarity of outer pin.
Accompanying drawing explanation
Fig. 1 is a kind of known MOS encapsulating structure schematic diagram.
Fig. 2 is the side view that tiling sandwich encapsulating structure taken by a kind of multi-chip list that the present invention manufactures.
Fig. 3 is the vertical view that tiling sandwich encapsulating structure taken by a kind of multi-chip list that the present invention manufactures.
Fig. 4 is the three-dimensional view of the first lead frame in the present invention.
Fig. 5 is the three-dimensional view of the second lead frame in the present invention.
Fig. 6 is the three-dimensional view of the 3rd lead frame in the present invention.
Fig. 7 (a) to Fig. 7 (m) takes the flow chart of tiling sandwich encapsulating structure process for a kind of multi-chip list of the present invention.
Wherein:
Lead frame 11
First chip 12
Second chip 13
First metal splint 14
Second metal splint 15
First metal bonding wire 16
Second metal bonding wire 17
First lead frame 21
Second lead frame 22
Horizontal segment 221 on first
First middle linkage section 222
First time horizontal segment 223
3rd lead frame 23
Horizontal segment 231 on second
Second middle linkage section 232
Second time horizontal segment 233
First chip 24
Second chip 25
Tin cream 26
Plastic packaging material 27.
Embodiment
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
As shown in Fig. 7 (a) ~ Fig. 7 (m), the process of tiling sandwich encapsulating structure taken by a kind of multi-chip list in the present embodiment, and its concrete technology step is as follows:
Step one, see Fig. 7 (a), provide the first lead frame, the material of the first lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C;
Step 2, see Fig. 7 (b), tin cream is applied by the mode of screen printing in the first lead frame Ji Dao region, object engages for realizing follow-up first implanted chip Hou Yuji island, can control the thickness of tin cream, area and position accurately by the adjustment thickness of web plate and the area of opening;
Step 3, see Fig. 7 (c), in step 2 first lead frame Ji Dao region coating tin cream on implant the first chip;
Step 4, see Fig. 7 (d), second lead frame is provided, described second lead frame is Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, the first middle linkage section and first time horizontal segment, the material of the second lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.On first of the second lead frame, the lower surface of horizontal segment applies tin cream by the mode of screen printing, can control the thickness of tin cream, area and position accurately by the adjustment thickness of web plate and the area of opening;
Step 5, see Fig. 7 (e), horizontal segment on first of second lead frame is pressed together on the first chip of the first lead frame upper surface, first chip and the second lead frame are formed by the tin cream of horizontal segment lower surface on first be electrically connected, after pressing, the first lead frame and the second lead frame form general frame, and the first lead frame lower surface and the second lead frame first time horizontal segment lower surface flushes;
Step 6, see Fig. 7 (f), by step 5 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering.The material of pressing plate requires deformation is less likely to occur and has good heat-conductive characteristic, and the thermal coefficient of expansion CTE of its thermal coefficient of expansion CTE and the first lead frame and the second lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C;
Step 7, see Fig. 7 (g), after completing Reflow Soldering, apply tin cream at the upper surface of first time horizontal segment of the second lead frame by the mode of screen printing;
Step 8, see Fig. 7 (h), the tin cream of first time horizontal segment upper surface coating of the second lead frame in step 7 implants the second chip;
Step 9, see Fig. 7 (i), 3rd lead frame is provided, described 3rd lead frame is Z-shaped, described the 3rd Z-shaped lead frame comprises horizontal segment on second, the second middle linkage section and second time horizontal segment, the material of the 3rd lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.On second of the 3rd lead frame, horizontal segment lower surface and second time horizontal segment lower surface apply tin cream by the mode of screen printing, object is electrically connected for realizing follow-up 3rd lead frame second is formed between horizontal segment and the second chip front side and between the 3rd lead frame second time horizontal segment and the first lead frame upper surface, can control the thickness of tin cream, area and position accurately by the adjustment thickness of web plate and the area of opening;
Step 10, see Fig. 7 (j), horizontal segment on second of 3rd lead frame is pressed together on the second chip of first time horizontal segment upper surface of the second lead frame, second chip and the 3rd lead frame are formed by the tin cream of horizontal segment lower surface on second be electrically connected, and second time horizontal segment lower surface of the 3rd lead frame is set up on the first lead frame upper surface, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame;
Step 11, see Fig. 7 (k), by step 10 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering.The material of pressing plate requires deformation is less likely to occur and has good heat-conductive characteristic, the thermal coefficient of expansion CTE of its thermal coefficient of expansion CTE and the first lead frame, the second lead frame and the 3rd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C;
Step 12, see Fig. 7 (l), plastic packaging material is adopted to carry out plastic packaging the general frame of step 11 after Reflow Soldering;
Step 13, see Fig. 7 (m), semi-finished product step 12 being completed plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, and tiling sandwich encapsulating structure taken by obtained multi-chip list.
In above-mentioned steps, step 5 and step 6 first lead frame pressing second lead frame form general frame and use pressing plate to carry out Reflow Soldering, can implement after step 8 second lead frame implants the second chip.
In above-mentioned steps, step 2, step 4 and step 9 are carried out by different platform simultaneously.
See Fig. 2 ~ Fig. 6, tiling sandwich encapsulating structure taken by a kind of multi-chip list of the present invention, it comprises the first lead frame 21, second lead frame 22, 3rd lead frame 23, first chip 24 and the second chip 25, described second lead frame 22 and the 3rd lead frame 23 are in Z-shaped, described the second Z-shaped lead frame 22 comprises horizontal segment 221 on first, first middle linkage section 222 and first time horizontal segment 223, described the 3rd Z-shaped lead frame 23 comprises horizontal segment 231 on second, second middle linkage section 232 and second time horizontal segment 233, described first chip 24 to be folded on the first lead frame 21 and first between horizontal segment 221, the front and back of described first chip 24 is electrically connected respectively by horizontal segment 221 and the first lead frame 21 on tin cream 26 and first, described second chip 25 to be folded on first time horizontal segment 223 and second between horizontal segment 231, the front and back of described second chip 25 is respectively by horizontal segment 231 and first time horizontal segment 223 on tin cream 26 and second and be electrically connected, described first lead frame 21, second lead frame 22 and the 3rd lead frame 23 outer encapsulating have plastic packaging material 27, described first lead frame 21 lower surface and first time horizontal segment 223 lower surface flush and are all exposed to outside plastic packaging material 27, described second time horizontal segment 233 lower surface is set up on the first lead frame 21 upper surface.
Described first lead frame 21, second lead frame 22 and the 3rd lead frame 23 are general frame, its material can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.
Described first chip 24 and the second chip 25 are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
In addition to the implementation, the present invention also includes other execution modes, the technical scheme that all employing equivalents or equivalent substitute mode are formed, within the protection range that all should fall into the claims in the present invention.

Claims (8)

1. tiling sandwich encapsulating structure taken by a multi-chip list, it is characterized in that: it comprises the first lead frame (21), second lead frame (22), 3rd lead frame (23), first chip (24) and the second chip (25), described second lead frame (22) and the 3rd lead frame (23) are in Z-shaped, described Z-shaped the second lead frame (22) comprises horizontal segment on first (221), first middle linkage section (222) and first time horizontal segment (223), described the 3rd Z-shaped lead frame (23) comprises horizontal segment on second (231), second middle linkage section (232) and second time horizontal segment (233), described first chip (24) to be folded on the first lead frame (21) and first between horizontal segment (221), the front and back of described first chip (24) is electrically connected respectively by horizontal segment (221) on tin cream (26) and first and the first lead frame (21), described second chip (25) to be folded on first time horizontal segment (223) and second between horizontal segment (231), the front and back of described second chip (25) is respectively by horizontal segment (231) on tin cream (26) and second and first time horizontal segment (223) and be electrically connected, described first lead frame (21), second lead frame (22) and the 3rd lead frame (23) outer encapsulating have plastic packaging material (27), described first lead frame (21) lower surface and first time horizontal segment (223) lower surface flush and are all exposed to outside plastic packaging material (27), described second time horizontal segment (233) lower surface is set up on the first lead frame (21) upper surface.
2. tiling sandwich encapsulating structure taken by a kind of multi-chip list according to claim 1, it is characterized in that: described first lead frame (21), the second lead frame (22) and the 3rd lead frame (23) are general frame.
3. a process for tiling sandwich encapsulating structure taken by multi-chip list, it is characterized in that described method comprises the steps:
Step one, provide the first lead frame;
Step 2, apply tin cream in the first lead frame Ji Dao region by the mode of screen printing;
The tin cream of step 3, the first lead frame Ji Dao region coating in step 2 implants the first chip;
Step 4, provide the second lead frame, described second lead frame is Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, the first middle linkage section and first time horizontal segment, and on first of the second lead frame, the lower surface of horizontal segment applies tin cream by the mode of screen printing;
Step 5, horizontal segment on first of the second lead frame is pressed together on the first chip of the first lead frame upper surface, after pressing, the first lead frame and the second lead frame form general frame, and the first lead frame lower surface and the second lead frame first time horizontal segment lower surface flushes;
Step 6, by step 5 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 7, complete Reflow Soldering after, apply tin cream at the upper surface of first time horizontal segment of the second lead frame by the mode of screen printing;
The tin cream of step 8, first time horizontal segment upper surface coating of the second lead frame in step 7 implants the second chip;
Step 9, provide the 3rd lead frame, described 3rd lead frame is Z-shaped, described the 3rd Z-shaped lead frame comprises horizontal segment on second, the second middle linkage section and second time horizontal segment, and on second of the 3rd lead frame, horizontal segment lower surface and second time horizontal segment lower surface apply tin cream by the mode of screen printing;
Step 10, horizontal segment on second of the 3rd lead frame is pressed together on the second chip of first time horizontal segment upper surface of the second lead frame, and second time horizontal segment lower surface of the 3rd lead frame is set up on the first lead frame upper surface, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame;
Step 11, by step 10 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 12, plastic packaging material is adopted to carry out plastic packaging the general frame of step 11 after Reflow Soldering;
Step 13, semi-finished product step 12 being completed plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, and tiling sandwich encapsulating structure taken by obtained multi-chip list.
4. the process of tiling sandwich encapsulating structure taken by a kind of multi-chip list according to claim 3, it is characterized in that: the material of described first lead frame, the second lead frame and the 3rd lead frame can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.
5. the process of tiling sandwich encapsulating structure taken by a kind of multi-chip list according to claim 3, it is characterized in that: described first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
6. the process of tiling sandwich encapsulating structure taken by a kind of multi-chip list according to claim 3, it is characterized in that: the thermal coefficient of expansion CTE of the thermal coefficient of expansion CTE of described pressing plate material and the first lead frame, the second lead frame and the 3rd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
7. the process of tiling sandwich encapsulating structure taken by a kind of multi-chip list according to claim 3, it is characterized in that: described step 2, step 4 and step 9 are carried out by different platform simultaneously.
8. the process of tiling sandwich encapsulating structure taken by a kind of multi-chip list according to claim 3, it is characterized in that: step 5 and step 6 first lead frame pressing second lead frame form general frame and use pressing plate to carry out Reflow Soldering, can implement after step 8 second lead frame implants the second chip.
CN201510991138.7A 2015-12-24 2015-12-24 Multi-core single-lapping, tiling and core-sandwiching packaging structure and technological method thereof Pending CN105448880A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515551A (en) * 2008-02-22 2009-08-26 株式会社瑞萨科技 Manufacturing method of semiconductor device
US20090212405A1 (en) * 2008-02-26 2009-08-27 Yong Liu Stacked die molded leadless package
CN101567367A (en) * 2004-01-28 2009-10-28 株式会社瑞萨科技 Semiconductor device
CN102237343A (en) * 2010-05-05 2011-11-09 万国半导体有限公司 Semiconductor package realizing connection by connecting sheets and manufacturing method for semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101567367A (en) * 2004-01-28 2009-10-28 株式会社瑞萨科技 Semiconductor device
CN101515551A (en) * 2008-02-22 2009-08-26 株式会社瑞萨科技 Manufacturing method of semiconductor device
US20090212405A1 (en) * 2008-02-26 2009-08-27 Yong Liu Stacked die molded leadless package
CN102237343A (en) * 2010-05-05 2011-11-09 万国半导体有限公司 Semiconductor package realizing connection by connecting sheets and manufacturing method for semiconductor package

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Application publication date: 20160330