CN105551983A - Multi-chip upright stack sandwich package structure with exposed frame and technique for multi-chip upright stack sandwich package structure - Google Patents
Multi-chip upright stack sandwich package structure with exposed frame and technique for multi-chip upright stack sandwich package structure Download PDFInfo
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- CN105551983A CN105551983A CN201510995888.1A CN201510995888A CN105551983A CN 105551983 A CN105551983 A CN 105551983A CN 201510995888 A CN201510995888 A CN 201510995888A CN 105551983 A CN105551983 A CN 105551983A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49534—Multi-layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a multi-chip upright stack sandwich package structure with an exposed frame and a technique for the multi-chip upright stack sandwich package structure. The technique comprises the following steps: (1) providing a first lead frame; (2) coating the first lead frame with a solder paste; (3) implanting a first chip into the solder paste of the first lead frame; (4) providing a second lead frame; (5) coating the second lead frame with the solder paste; (6) laminating the second lead frame on the first chip; (7) carrying out reflow soldering; (8) coating the second lead frame with the solder paste; (9) implanting a second chip into the second lead frame; (10) providing a third lead frame; (11) coating the third lead frame with the solder paste; (12) laminating the third lead frame on the second chip; (13) carrying out reflux soldering; (14) carrying out plastic package by a molding compound; and (15) carrying out cutting or punching operation. The technique has the beneficial effects that the heat dissipation capacity of a product is improved and the package resistance of the product is reduced.
Description
Technical field
The present invention relates to a kind of framework and expose the stacking sandwich encapsulating structure of multi-chip formal dress and process thereof, belong to technical field of semiconductor encapsulation.
Background technology
In recent years, along with electronic product is constantly pursued power density, no matter be Diode(diode) or Transistor(triode) encapsulation, the MOS product especially in Transistor is just towards more high-power, smaller szie, more fast, better trend of dispelling the heat is in development.The disposable manufacture also slowly even more disposable encapsulation technology spurt of the highly difficult low cost of the high density of large regions and the challenge towards zonule by single encapsulation technology of encapsulation.
Therefore, also more requirement has been had to the structure of the various electrical properties being encapsulated in parasitic resistance, electric capacity, inductance etc. of MOS product, encapsulation, the dissipation of heat sexuality of encapsulation, the reliability aspect of encapsulation and highly difficult disposable encapsulation technology aspect.
Traditional Diode(diode) and Transistor(triode) or the encapsulation of MOS product is general according to product performance, the difference of power and the Consideration of cost, the bonding wire mode that make use of gold thread, silver alloy wire, copper cash, aluminum steel and aluminium strip as the main interconnection technique of chip and interior pin, thus realizes electrical connection.But the performance of the technical approach of bonding wire to product is present in restriction and the defect of the following aspects:
One, encapsulation and the restriction of manufacture view and defect:
1), Weldability (Bondability) aspect: usually can change because of the parameter sheet of the change of Metal wire material, metal pins material and equipment and instrument, the change of performance and precision and maintain and correct manage and the rosin joint of the first solder joint of causing and the second solder joint faying face, come off, puzzlement that breakpoint, neck crack, collapse line and short circuit etc. are all, yield cannot promote, cost cannot decline, the instability of reliability to result in encapsulation;
2), disposable high-density encapsulation technology aspect: traditional mutual contact mode is nearly all adopt the welding manner that single chips one chips repeats load, high temperature ultrasonic single line single line adopted by wire in matrix type die-attach area.And be like this loader of specialty in situation, ball bonding wire bonder, bonding aluminum steel/machinery equipment such as aluminium strip machine or copper sheet overlapping machine repetitive operation more at a high speed all cannot improving production efficiency, unit cost cannot be reduced, also because equipment constantly promotes the same unsteadiness also improving manufacture of speed of production.
Two, the restriction of the special aspect of performance of encapsulating products and defect:
1), dissipation of heat aspect: traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS, general is all coated by plastic packaging material, external pin is only stayed to be exposed to outside plastic-sealed body, due to the material that plastic packaging material itself is not a kind of thermal conductance, so traditional Diode(diode) and Transistor(triode) or operationally the produced heat of MOS product is difficult to dissipate by plastic packaging material the packaging body of plastic packaging material material, fine wire can only be relied on to be interconnected at the dissipation that heat energy helped by metal pins material, but the dissipation capability of the approach of this dissipation of heat to heat is very limited, form the resistance of the dissipation of heat on the contrary,
2), resistivity (Resistivity) aspect: resistivity (resistivity) is used to the physical quantity representing various material resistance characteristic as you know.When temperature is certain, have formula R=ρ l/s ρ to be wherein exactly resistivity, l is the length of material, and s is area.Can find out, the resistance sizes of material is proportional to the length of material, and is inversely proportional to its area.Definition by the known resistivity of above formula: ρ=Rs/l.Traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS, bonding wire is adopted to be formed interconnected, can clearly know thus wire for performing power supply or signal can because, the length of conductor material and the change of sectional area and have influence on the size of resistivity and the loss of contact resistance, the product impact being especially applied in power aspect is obvious especially.
For solving the problem, industry is to traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS improves, replace bonding wire with metal tape, metal splint, reduce the ability that packaged resistance, inductance and expectation improve the dissipation of heat.
As shown in Figure 1, be the existing MOS stack package structure of one, in this structure, lead frame 11 comprises pipe core welding disc and pin, and the pipe core welding disc of lead frame 11 is implanted the first chip 12.The source electrode of the first chip 12 is electrically coupled to pin by the first metal splint 14, and the grid of the first chip 12 is electrically coupled to pin by the first metal bonding wire 16.Then the source electrode implanting the second chip 13, second chip 13 on the first metal splint 14 is electrically coupled to pin by the second metal splint 15, and the grid of the second chip 13 is electrically coupled to pin by the second metal bonding wire 17.Carry out again encapsulating, cut, the subsequent handling such as test.This MOS encapsulating structure metal splint instead of the bonding wire in conventional MOS encapsulation, reduces partial encapsulation resistance, but still there is following defect:
1.) the drain electrode of this MOS encapsulating structure chips, source electrode and grid and lead frame are formed interconnectedly will use different equipment respectively, and processing procedure is complicated, and the acquisition cost of equipment is higher.
2.) this MOS encapsulating structure is when being coupled to metal splint and metal bonding wire on chip and pin, can only carry out by a chips, cannot whole piece one-body molded, manufacture efficiency lower.
3. the inside and outside pin that) this MOS encapsulates is not integrally formed, but is welded by solder, so inside and outside pin junction (i.e. metal splint, metal tape and lead frame contact position) still exists higher contact resistance.
4. when) using metal splint to be coupled on chip and metal pins, because of when its chip board figure is different or chip area is different, die-cut and the carrying mould of metal splint and metal splint and mechanism, just must redesign, again manufacture, and these change and often cause the waste of waste, again the framework time cost purchasing money, the waste of business opportunity cost and the waste of personnel depaly.
5. when) using metal splint to be coupled on chip and metal pins, because of its metal splint very little production die-cut, carrying and in welding process, drop when usually there is metal splint transport, topple over and failure welding when welding, cause the impaired of yield and reliability.
Summary of the invention
Technical problem to be solved by this invention provides a kind of framework to expose the stacking sandwich encapsulating structure of multi-chip formal dress and process thereof for above-mentioned prior art, and its technique is simple, and production cost is lower.
Another object of the present invention is to provide a kind of framework to expose the stacking sandwich encapsulating structure of multi-chip formal dress and process thereof, its whole piece product can be one-body molded, and production efficiency is high.
Another object of the present invention is to provide a kind of framework to expose the stacking sandwich encapsulating structure of multi-chip formal dress and process thereof, and its a kind of framework produced exposes multi-chip formal dress stacking sandwich encapsulating structure and has lower packaged resistance and package inductance.
Another object of the present invention is to provide a kind of framework to expose the stacking sandwich encapsulating structure of multi-chip formal dress and process thereof, and its a kind of framework produced exposes multi-chip formal dress stacking sandwich encapsulating structure and has good thermal diffusivity.
The present invention's adopted technical scheme that solves the problem is: a kind of framework exposes the stacking sandwich encapsulating structure of multi-chip formal dress, it comprises the first lead frame, second lead frame, 3rd lead frame, first chip and the second chip, described second lead frame and the 3rd lead frame are Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, first middle linkage section and first time horizontal segment, described the 3rd Z-shaped lead frame comprises horizontal segment on second, second middle linkage section and second time horizontal segment, described first chip gripper to be located on the first lead frame and first between horizontal segment, the front and back of described first core is electrically connected respectively by horizontal segment on tin cream and first and the first lead frame, described second chip gripper to be located on first on horizontal segment and second between horizontal segment, the front and back of described second chip is electrically connected respectively by horizontal segment on horizontal segment and first on tin cream and second, described first lead frame, second lead frame and the 3rd lead frame outer encapsulating have plastic packaging material, described first lead frame lower surface, first time horizontal segment lower surface and second time horizontal segment lower surface flush, described first lead frame lower surface, first time horizontal segment lower surface, on second time horizontal segment lower surface and second, horizontal segment upper surface is all exposed to outside plastic packaging material
Described first lead frame, the second lead frame and the 3rd lead frame are general frame.
Framework exposes a process for the stacking sandwich encapsulating structure of multi-chip formal dress, and described method comprises the steps:
Step one, provide the first lead frame;
Step 2, apply tin cream in the first lead frame Ji Dao region by the mode of screen printing;
The tin cream of step 3, the first lead frame Ji Dao region coating in step 2 implants the first chip;
Step 4, provide the second lead frame, described second lead frame is Z-shaped, and described the second Z-shaped lead frame comprises horizontal segment on first, the first middle linkage section and first time horizontal segment;
Step 5, on first of the second lead frame, the lower surface of horizontal segment applies tin cream by the mode of screen printing;
Step 6, horizontal segment on first of the second lead frame is pressed together on the first chip of the first lead frame upper surface, after pressing, the first lead frame and the second lead frame form general frame, and the first lead frame lower surface and the second lead frame first time horizontal segment lower surface flushes;
Step 7, by step 6 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 8, complete Reflow Soldering after, on first of the second lead frame, the upper surface of horizontal segment applies tin cream by the mode of screen printing;
Step 9, in step 8 the second lead frame first on horizontal segment upper surface coating tin cream on implant the second chip;
Step 10, provide the 3rd lead frame, described 3rd lead frame is Z-shaped, and described the 3rd Z-shaped lead frame comprises horizontal segment on second, the second middle linkage section and second time horizontal segment;
Step 11, on second of the 3rd lead frame, the lower surface of horizontal segment applies tin cream by the mode of screen printing;
Step 12, horizontal segment on second of the 3rd lead frame is pressed together on the second lead frame first on horizontal segment upper surface the second chip on, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame, and the first lead frame lower surface, the second lead frame first time horizontal segment lower surface and the 3rd lead frame second time horizontal segment lower surface flush;
Step 13, by step 12 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 14, adopt plastic packaging material to carry out plastic packaging the general frame of step 13 after Reflow Soldering, after plastic packaging the 3rd lead frame second on the upper surface of horizontal segment be exposed to outside plastic packaging material;
Step 15, semi-finished product step 14 being completed plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, and obtained framework exposes the stacking sandwich encapsulating structure of multi-chip formal dress.
Described first lead frame pressing second lead frame forms general frame, can implement after the second lead frame implants the second chip.
The material of described first lead frame, the second lead frame and the 3rd lead frame can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.
Described first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
The thermal coefficient of expansion CTE of the thermal coefficient of expansion CTE of described pressing plate material and the first lead frame, the second lead frame and the 3rd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
Described step 2, step 5 and step 11 are carried out by different platform simultaneously.
Compared with prior art, the invention has the advantages that:
1, a kind of framework of the present invention expose the second lead frame of the stacking sandwich encapsulating structure of multi-chip formal dress and the 3rd lead frame directly and the source electrode of MOS chip and grid formed and be electrically connected, instead of in conventional MOS chip package and utilize metal welding line to form interconnected technique, substantially reduce packaged resistance.Formed because pin in lead frame and outer pin are formed in one simultaneously, further reduce packaged resistance, technology of the present invention can reduce more than at least 30% than the packaged resistance of conventional package design;
2, a kind of framework of the present invention is exposed the second lead frame of the stacking sandwich encapsulating structure of multi-chip formal dress and the 3rd lead frame and is directly formed by the source electrode of tin cream and MOS chip and grid and be electrically connected, reduce or remit the interconnected operation of metal bonding wire completely, save the cost such as the equipment purchasing of the interconnected operation of metal bonding wire, operation material completely.And the second lead frame of the present invention and the 3rd lead frame are all that whole piece is integrated, form with chip that to be electrically connected also be that whole piece one step completes, compared with forming interconnected technique with conventional metals bonding wire, the interconnected chip one by one of sheet metal, technique is comparatively simple, and production efficiency is significantly improved;
3, a kind of framework of the present invention exposes the stacking sandwich encapsulating structure of multi-chip formal dress and process thereof, because upper and lower two surfaces of chip all directly contact with lead frame, the heat produced during chip operation sheds by lead frame, and the first lead frame lower surface of the present invention and the 3rd leadframe part upper surface are all directly exposed to outside plastic packaging material, framework of the present invention exposes multi-chip formal dress stacking sandwich encapsulating structure and has good heat dispersion; And the present invention can again according to product power, heat conduction or the difference of heat radiation additional radiator on lead frame freely, in order to increase the ability of the product dissipation of heat further;
4, a kind of framework of the present invention exposes the stacking sandwich encapsulating structure of multi-chip formal dress and uses upper lower platen to push down general frame to carry out Reflow Soldering, framework to be not easily heated the cohesion institute jack-up of cooling procedure after melting by tin cream when Reflow Soldering, ensure the total height of frame structure, prevent movement or the rotation of chip, and can guarantee that framework exposes the coplanarity of outer pin.
Accompanying drawing explanation
Fig. 1 is a kind of known MOS stack package structure schematic diagram.
Fig. 2 is the side view that a kind of framework that the present invention manufactures exposes the stacking sandwich encapsulating structure of multi-chip formal dress.
Fig. 3 is the vertical view that a kind of framework that the present invention manufactures exposes the stacking sandwich encapsulating structure of multi-chip formal dress.
Fig. 4 is the three-dimensional view of the first lead frame in the present invention.
Fig. 5 is the three-dimensional view of the second lead frame in the present invention.
Fig. 6 is the three-dimensional view of the 3rd lead frame in the present invention.
Fig. 7 is the exploded perspective schematic diagram of the first lead frame in the present invention, the first chip, the second lead frame, the second chip and the 3rd lead frame.
Fig. 8 (a) to Fig. 8 (o) exposes the flow chart of multi-chip formal dress stacking sandwich encapsulating structure process for a kind of framework of the present invention.
Wherein:
Lead frame 11
First chip 12
Second chip 13
First metal splint 14
Second metal splint 15
First metal bonding wire 16
Second metal bonding wire 17
First lead frame 21
Second lead frame 22
Horizontal segment 221 on first
First middle linkage section 222
First time horizontal segment 223
3rd lead frame 23
Horizontal segment 231 on second
Second middle linkage section 232
Second time horizontal segment 233
First chip 24
Second chip 25
Tin cream 26
Plastic packaging material 27.
Embodiment
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
As shown in Fig. 8 (a) ~ Fig. 8 (n), a kind of framework in the present embodiment exposes the process of the stacking sandwich encapsulating structure of multi-chip formal dress, and its concrete technology step is as follows:
Step one, see Fig. 8 (a), provide the first lead frame, the material of the first lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C;
Step 2, see Fig. 8 (b), tin cream is applied by the mode of screen printing in the first lead frame Ji Dao region, object engages for realizing follow-up first implanted chip Hou Yuji island, can control the thickness of tin cream, area and position accurately by the adjustment thickness of web plate and the area of opening;
Step 3, see Fig. 8 (c), in step 2 first lead frame Ji Dao region coating tin cream on implant the first chip;
Step 4, see Fig. 8 (d), second lead frame is provided, described second lead frame is Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, the first middle linkage section and first time horizontal segment, the material of the second lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C;
Step 5, see Fig. 8 (e), on first of the second lead frame, the lower surface of horizontal segment applies tin cream by the mode of screen printing, can control the thickness of tin cream, area and position accurately by the adjustment thickness of web plate and the area of opening;
Step 6, see Fig. 8 (f), horizontal segment on first of second lead frame is pressed together on the first chip of the first lead frame upper surface, first chip and the second lead frame are formed by the tin cream of horizontal segment lower surface on first be electrically connected, after pressing, the first lead frame and the second lead frame form general frame, and the first lead frame lower surface and the second lead frame first time horizontal segment lower surface flushes;
Step 7, see Fig. 8 (g), by step 6 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering.The material of pressing plate requires deformation is less likely to occur and has good heat-conductive characteristic, and the thermal coefficient of expansion CTE of its thermal coefficient of expansion CTE and the first lead frame and the second lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C;
Step 8, see Fig. 8 (h), after completing Reflow Soldering, on first of the second lead frame, the upper surface of horizontal segment applies tin cream by the mode of screen printing;
Step 9, see Fig. 8 (i), in step 8 the second lead frame first on the coating of horizontal segment upper surface tin cream on implant the second chip;
Step 10, see Fig. 8 (j), 3rd lead frame is provided, described 3rd lead frame is Z-shaped, described the 3rd Z-shaped lead frame comprises horizontal segment on second, the second middle linkage section and second time horizontal segment, the material of the 3rd lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C;
Step 11, see Fig. 8 (k), on second of the 3rd lead frame, the lower surface of horizontal segment applies tin cream by the mode of screen printing, can control the thickness of tin cream, area and position accurately by the adjustment thickness of web plate and the area of opening;
Step 12, see Fig. 8 (l), horizontal segment on second of 3rd lead frame is pressed together on the second lead frame first on horizontal segment upper surface the second chip on, second chip and the 3rd lead frame are formed by the tin cream of horizontal segment lower surface on second be electrically connected, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame, and the first lead frame lower surface, the second lead frame first time horizontal segment lower surface and the 3rd lead frame second time horizontal segment lower surface flush;
Step 13, see Fig. 8 (m), by step 12 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering.The material of pressing plate requires deformation is less likely to occur and has good heat-conductive characteristic, the thermal coefficient of expansion CTE of its thermal coefficient of expansion CTE and the first lead frame, the second lead frame and the 3rd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C;
Step 14, see Fig. 8 (n), adopt plastic packaging material to carry out plastic packaging the general frame of step 13 after Reflow Soldering, after plastic packaging the 3rd lead frame second on the upper surface of horizontal segment be exposed to outside plastic packaging material;
Step 15, see Fig. 8 (o), semi-finished product step 14 being completed plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, and obtained framework exposes the stacking sandwich encapsulating structure of multi-chip formal dress.
In above-mentioned steps, step 6 and step 7 first lead frame pressing second lead frame form general frame and use pressing plate to carry out Reflow Soldering, can implement after step 9 second lead frame implants the second chip.
In above-mentioned steps, step 2, step 5 and step 11 are carried out by different platform simultaneously.
See Fig. 2 ~ Fig. 7, a kind of framework of the present invention exposes the stacking sandwich encapsulating structure of multi-chip formal dress, it comprises the first lead frame 21, second lead frame 22, 3rd lead frame 23, first chip 24 and the second chip 25, described second lead frame 22 and the 3rd lead frame 23 are in Z-shaped, described the second Z-shaped lead frame 22 comprises horizontal segment 221 on first, first middle linkage section 222 and first time horizontal segment 223, described the 3rd Z-shaped lead frame 23 comprises horizontal segment 231 on second, second middle linkage section 232 and second time horizontal segment 233, described first chip 24 to be folded on the first lead frame 21 and first between horizontal segment 221, the front and back of described first chip 24 is electrically connected respectively by horizontal segment 221 and the first lead frame 21 on tin cream 26 and first, described second chip 25 to be folded on first on horizontal segment 221 and second between horizontal segment 231, the front and back of described second chip 25 is electrically connected respectively by horizontal segment 221 on horizontal segment on tin cream 26 and second 231 and first, described first lead frame 21, second lead frame 22 and the 3rd lead frame 23 outer encapsulating have plastic packaging material 27, described first lead frame 21 lower surface, first time horizontal segment 223 lower surface and second time horizontal segment 233 lower surface flush, described first lead frame 21 lower surface, first time horizontal segment 223 lower surface, on second time horizontal segment 233 lower surface and second, horizontal segment 231 upper surface is all exposed to outside plastic packaging material 27.
Described first lead frame 21, second lead frame 22 and the 3rd lead frame 23 are general frame, its material can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.
Described first chip 24 and the second chip 25 are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
In addition to the implementation, the present invention also includes other execution modes, the technical scheme that all employing equivalents or equivalent substitute mode are formed, within the protection range that all should fall into the claims in the present invention.
Claims (8)
1. a framework exposes the stacking sandwich encapsulating structure of multi-chip formal dress, it is characterized in that: it comprises the first lead frame (21), second lead frame (22), 3rd lead frame (23), first chip (24) and the second chip (25), described second lead frame (22) and the 3rd lead frame (23) are in Z-shaped, described Z-shaped the second lead frame (22) comprises horizontal segment on first (221), first middle linkage section (222) and first time horizontal segment (223), described the 3rd Z-shaped lead frame (23) comprises horizontal segment on second (231), second middle linkage section (232) and second time horizontal segment (233), described first chip (24) to be folded on the first lead frame (21) and first between horizontal segment (221), the front and back of described first core (24) is electrically connected respectively by horizontal segment (221) on tin cream (26) and first and the first lead frame (21), described second chip (25) to be folded on horizontal segment on first (221) and second between horizontal segment (231), the front and back of described second chip (25) is electrically connected respectively by horizontal segment (221) on horizontal segment (231) and first on tin cream (26) and second, described first lead frame (21), second lead frame (22) and the 3rd lead frame (23) outer encapsulating have plastic packaging material (27), described first lead frame (21) lower surface, first time horizontal segment (223) lower surface and second time horizontal segment (233) lower surface flush, described first lead frame (21) lower surface, first time horizontal segment (223) lower surface, on second time horizontal segment (233) lower surface and second, horizontal segment (231) upper surface is all exposed to outside plastic packaging material (27).
2. a kind of framework according to claim 1 exposes the stacking sandwich encapsulating structure of multi-chip formal dress, it is characterized in that: described first lead frame (21), the second lead frame (22) and the 3rd lead frame (23) are general frame.
3. framework exposes a process for the stacking sandwich encapsulating structure of multi-chip formal dress, it is characterized in that described method comprises the steps:
Step one, provide the first lead frame;
Step 2, apply tin cream in the first lead frame Ji Dao region by the mode of screen printing;
The tin cream of step 3, the first lead frame Ji Dao region coating in step 2 implants the first chip;
Step 4, provide the second lead frame, described second lead frame is Z-shaped, and described the second Z-shaped lead frame comprises horizontal segment on first, the first middle linkage section and first time horizontal segment;
Step 5, on first of the second lead frame, the lower surface of horizontal segment applies tin cream by the mode of screen printing;
Step 6, horizontal segment on first of the second lead frame is pressed together on the first chip of the first lead frame upper surface, after pressing, the first lead frame and the second lead frame form general frame, and the first lead frame lower surface and the second lead frame first time horizontal segment lower surface flushes;
Step 7, by step 6 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 8, complete Reflow Soldering after, on first of the second lead frame, the upper surface of horizontal segment applies tin cream by the mode of screen printing;
Step 9, in step 8 the second lead frame first on horizontal segment upper surface coating tin cream on implant the second chip;
Step 10, provide the 3rd lead frame, described 3rd lead frame is Z-shaped, and described the 3rd Z-shaped lead frame comprises horizontal segment on second, the second middle linkage section and second time horizontal segment;
Step 11, on second of the 3rd lead frame, the lower surface of horizontal segment applies tin cream by the mode of screen printing;
Step 12, horizontal segment on second of the 3rd lead frame is pressed together on the second lead frame first on horizontal segment upper surface the second chip on, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame, the first lead frame lower surface, the second lead frame first time horizontal segment lower surface and the 3rd lead frame second time horizontal segment lower surface flush;
Step 13, by step 12 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 14, adopt plastic packaging material to carry out plastic packaging the general frame of step 13 after Reflow Soldering, after plastic packaging the 3rd lead frame second on the upper surface of horizontal segment be exposed to outside plastic packaging material;
Step 15, semi-finished product step 14 being completed plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, and obtained framework exposes the stacking sandwich encapsulating structure of multi-chip formal dress.
4. a kind of framework according to claim 3 exposes the process of the stacking sandwich encapsulating structure of multi-chip formal dress, it is characterized in that: the material of described first lead frame, the second lead frame and the 3rd lead frame can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.
5. a kind of framework according to claim 3 exposes the process of the stacking sandwich encapsulating structure of multi-chip formal dress, it is characterized in that: described first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
6. a kind of framework according to claim 3 exposes the process of the stacking sandwich encapsulating structure of multi-chip formal dress, it is characterized in that: the thermal coefficient of expansion CTE of the thermal coefficient of expansion CTE of described pressing plate material and the first lead frame, the second lead frame and the 3rd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
7. a kind of framework according to claim 3 exposes the process of the stacking sandwich encapsulating structure of multi-chip formal dress, it is characterized in that: described step 2, step 5 and step 11 are carried out by different platform simultaneously.
8. a kind of framework according to claim 3 exposes the process of the stacking sandwich encapsulating structure of multi-chip formal dress, it is characterized in that: step 6 and step 7 first lead frame pressing second lead frame form general frame and use pressing plate to carry out Reflow Soldering, can implement after step 9 second lead frame implants the second chip.
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| CN201510995888.1A CN105551983A (en) | 2015-12-24 | 2015-12-24 | Multi-chip upright stack sandwich package structure with exposed frame and technique for multi-chip upright stack sandwich package structure |
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| CN201510995888.1A CN105551983A (en) | 2015-12-24 | 2015-12-24 | Multi-chip upright stack sandwich package structure with exposed frame and technique for multi-chip upright stack sandwich package structure |
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| CN109791925A (en) * | 2016-10-28 | 2019-05-21 | 英特尔公司 | Use the 3D chip assembly for stacking lead frame |
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Application publication date: 20160504 |