CN205355032U - Frame exposes multicore piece singly to be taken flip -chip and piles up double -layered core packaging structure - Google Patents
Frame exposes multicore piece singly to be taken flip -chip and piles up double -layered core packaging structure Download PDFInfo
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- CN205355032U CN205355032U CN201521098006.3U CN201521098006U CN205355032U CN 205355032 U CN205355032 U CN 205355032U CN 201521098006 U CN201521098006 U CN 201521098006U CN 205355032 U CN205355032 U CN 205355032U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model relates to a frame exposes multicore piece singly to be taken flip -chip and piles up double -layered core packaging structure, it includes first lead frame (21), second lead frame (22), third lead frame (23), first chip (24) and second chip (25), first chip (24) press from both sides and establish between first lead frame (21) and second lead frame (22), second chip (25) press from both sides and establish between second lead frame (22) and third lead frame (23), first chip (24) openly with second chip (25) front dispose respectively in on first lead frame (21) and the first section of improving level (221), first lead frame (21) lower surface and first horizontal segment (223) lower surface flush and expose outside the plastic envelope material. The beneficial effects of the utility model are that: have lower encapsulation resistance and package inductance, have better thermal diffusivity, whole piece product integrated into one piece, production efficiency is high.
Description
Technical field
This utility model relates to a kind of framework to be exposed multi-chip list and takes the stacking sandwich encapsulating structure of upside-down mounting, belongs to technical field of semiconductor encapsulation.
Background technology
In recent years, along with power density is constantly pursued by electronic product, no matter be Diode(diode) or Transistor(audion) encapsulation, especially the MOS product in Transistor just towards greater power, smaller szie, more rapid, better trend of dispelling the heat in development.The also slowly even disposable encapsulation technology spurt of the highly difficult low cost of the high density of larger area and the challenge towards zonule by single encapsulation technology of the disposable manufacture of encapsulation.
Therefore, be also the encapsulated in resistance of parasitism, electric capacity, the various electrical properties of inductance etc., the structure of encapsulation, the dissipation of heat sexuality of encapsulation, the reliability aspect of encapsulation and the highly difficult disposable encapsulation technology aspect of MOS product there is more requirement.
Traditional Diode(diode) and Transistor(audion) or the general Consideration according to product attribute, the difference of power and cost of the encapsulation of MOS product, make use of the bonding wire mode of gold thread, silver alloy wire, copper cash, aluminum steel and aluminium strip as the main interconnection technique of chip and interior pin, thus realizing electrical connection.But the performance of product is present in restriction and the defect of the following aspects by the technical approach of bonding wire:
One, encapsulation and the restriction of manufacture view and defect:
1), Weldability (Bondability) aspect: usually can because of the rosin joint of the first solder joint that the parameter sheet change of Metal wire material, the change of metal pins material and equipment and instrument, performance and the change of precision and maintenance manage with correction and cause and the second solder joint faying face, come off, puzzlement that breakpoint, cervical region crack, collapse line and short circuit etc. are all, result in and encapsulate that yield cannot promote, cost cannot decline, the instability of reliability；
2), disposable high-density encapsulation technology aspect: traditional mutual contact mode be nearly all adopt single one chips of chips to repeat load in matrix type die-attach area, the welding manner of high temperature ultrasonic single line single line adopted by tinsel.And in situation be so the palikinesia at a high speed again of the loader of specialty, ball bonding wire bonder, bonding aluminum steel/machinery equipment such as aluminium strip machine or copper sheet overlapping machine all cannot improving production efficiency, unit cost cannot be reduced, also because equipment constantly promotes the unstability also improving manufacture that speed of production is same.
Two, the restriction of the special aspect of performance of encapsulating products and defect:
1), dissipation of heat aspect: traditional Diode(diode) and Transistor(audion) or the encapsulating products of MOS, it is typically all and is coated with by plastic packaging material, external pin is only stayed to be exposed to outside plastic-sealed body, owing to plastic packaging material itself is not the material of a kind of thermal conductance, so traditional Diode(diode) and Transistor(audion) or the packaging body of the very difficult plastic packaging material material that dissipates by plastic packaging material of MOS product operationally produced heat, fine tinsel can only be relied on to be interconnected at metal pins material to help the dissipation of heat energy, but the dissipation capability of heat is very limited amount of by the approach of this dissipation of heat, form the resistance of the dissipation of heat on the contrary；
2), resistivity (Resistivity) aspect: resistivity (resistivity) is used to indicate that the physical quantity of various material resistance characteristic as you know.When temperature is certain, having formula R=ρ l/s ρ therein is exactly resistivity, and l is the length of material, and s is area.It can be seen that the resistance sizes of material is proportional to the length of material, and it is inversely proportional to its area.Definition by the known resistivity of above formula: ρ=Rs/l.Traditional Diode(diode) and Transistor(audion) or the encapsulating products of MOS, bonding wire is adopted to form interconnection, thus can be apparent from tinsel for performing power supply or signal can because, the length of conductor material and the change of sectional area and have influence on the size of resistivity and the loss of contact resistance, the product impact being especially applied in power aspect is obvious especially.
For solving the problems referred to above, industry is to traditional Diode(diode) and Transistor(audion) or the encapsulating products of MOS has improved, replace bonding wire with metal tape, metal splint, reduce packaged resistance, inductance and expectation and improve the ability of the dissipation of heat.
As it is shown in figure 1, be a kind of existing MOS stack package structure, in this structure, lead frame 11 comprises pipe core welding disc and pin, implants the first chip 12 on the pipe core welding disc of lead frame 11.The source electrode of the first chip 12 is electrically coupled to pin by the first metal splint 14, and the grid of the first chip 12 is electrically coupled to pin by the first metal wire 16.Then implanting the second chip 13 on the first metal splint 14, the source electrode of the second chip 13 is electrically coupled to pin by the second metal splint 15, and the grid of the second chip 13 is electrically coupled to pin by the second metal wire 17.Carry out again encapsulating, cut, the subsequent handling such as test.This MOS encapsulating structure metal splint instead of the bonding wire in conventional MOS encapsulation, reduce partial encapsulation resistance, but still there is following defect: first, the drain electrode of this MOS encapsulating structure chips, source electrode and grid form interconnection from lead frame to use different equipment respectively, processing procedure is complicated, and the acquisition cost of equipment is higher；Secondly, this MOS encapsulating structure, when metal splint and metal wire are coupled on chip and pin, can only carry out by a chips, it is impossible to whole piece is one-body molded, manufactures inefficient.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of framework to expose multi-chip list for above-mentioned prior art to take the stacking sandwich encapsulating structure of upside-down mounting, its technique is simple, production cost is relatively low, there is relatively low packaged resistance and package inductance, there is good thermal diffusivity, whole piece product can be one-body molded, and production efficiency is high.
The technical scheme in the invention for solving the above technical problem is: a kind of framework exposes multi-chip list takes the stacking sandwich encapsulating structure of upside-down mounting, it includes the first lead frame, second lead frame, 3rd lead frame, first chip and the second chip, described second lead frame and the 3rd lead frame are Z-shape, described the second Z-shaped lead frame includes horizontal segment on first, first middle linkage section and first time horizontal segment, described the 3rd Z-shaped lead frame includes horizontal segment on second, second middle linkage section and second time horizontal segment, described first chip gripper is located on the first lead frame and first between horizontal segment, described first chip front side is configured on described first lead frame, the front and back of described first chip is electrically connected respectively through horizontal segment on tin cream and the first lead frame and first, described second chip gripper is located on first on horizontal segment and second between horizontal segment, described second chip front side is configured on described first on horizontal segment, the front and back of described second chip is electrically connected respectively through horizontal segment on horizontal segment and second on tin cream and first, described first lead frame, second lead frame and the 3rd lead frame outer encapsulating have plastic packaging material, described first lead frame lower surface and first time horizontal segment lower surface flush, described first lead frame lower surface, on first time horizontal segment lower surface and second, horizontal segment upper surface is both exposed to outside plastic packaging material, described second time horizontal segment lower surface rides upon on the first lead frame upper surface.
The material of described first lead frame, the second lead frame and the 3rd lead frame can be alloyed copper material, fine copper material, aluminum copper facing material, zinc copper facing material, dilval material, it is also possible to is the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope.
Described first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
Compared with prior art, the utility model has the advantage of:
1, a kind of framework of this utility model exposes multi-chip list and takes the second lead frame of the stacking sandwich encapsulating structure of upside-down mounting and the 3rd lead frame is directly electrically connected with source electrode and the grid of MOS chip, instead of the technique utilizing metal wire to form interconnection in conventional MOS chip package, substantially reducing packaged resistance, technology of the present utility model can reduce more than at least 30% than the packaged resistance of conventional package design；
2, a kind of framework of this utility model exposes multi-chip list and takes the second lead frame of the stacking sandwich encapsulating structure of upside-down mounting and the 3rd lead frame and be electrically connected either directly through the tin cream source electrode with MOS chip and grid, reduce or remit the interconnection operation of metal wire completely, save the metal wire interconnection cost such as the equipment purchasing of operation, operation material completely.And the second lead frame of the present utility model and the 3rd lead frame are all that whole piece is integrated, be electrically connected with chip is also that whole piece one step completes, interconnect chip one by one with conventional metals bonding wire, sheet metal and formed compared with the technique of interconnection, technique is relatively simple, and production efficiency is significantly improved；
3, a kind of framework of the present utility model exposes multi-chip list and takes upside-down mounting stacking sandwich encapsulating structure and all directly contact with lead frame due to upper and lower two surfaces of chip, the heat produced during chip operation can be shed by lead frame, and the first lead frame lower surface of the present utility model and the 3rd leadframe part upper surface are directly exposed to outside plastic packaging material, framework of the present utility model exposes multi-chip list to be taken upside-down mounting stacking sandwich encapsulating structure and has good heat dispersion；And this utility model can again according to product power, heat conduction or the difference of heat radiation additional radiator on lead frame freely, in order to increase the ability of the product dissipation of heat further；
4, a kind of framework of the present utility model exposes multi-chip list and takes the stacking sandwich encapsulating structure of upside-down mounting and use upper lower platen to push down general frame to carry out Reflow Soldering, framework is not easily heated the cohesion institute jack-up of cooling procedure after melting by tin cream when Reflow Soldering, ensure the total height of frame structure, prevent movement or the rotation of chip, and can ensure that framework exposes the coplanarity of outer foot.
Accompanying drawing explanation
Fig. 1 is a kind of known MOS stack package structure schematic diagram.
Fig. 2 is that a kind of framework of this utility model exposes multi-chip list and takes the side view of the stacking sandwich encapsulating structure of upside-down mounting.
Fig. 3 (a) to Fig. 3 (m) exposes multi-chip list for a kind of framework of this utility model and takes the flow chart of the stacking sandwich encapsulating structure process of upside-down mounting.
Wherein:
Lead frame 11
First chip 12
Second chip 13
First metal splint 14
Second metal splint 15
First metal wire 16
Second metal wire 17
First lead frame 21
Second lead frame 22
Horizontal segment 221 on first
First middle linkage section 222
First time horizontal segment 223
3rd lead frame 23
Horizontal segment 231 on second
Second middle linkage section 232
Second time horizontal segment 233
First chip 24
Second chip 25
Tin cream 26
Plastic packaging material 27.
Detailed description of the invention
Below in conjunction with accompanying drawing embodiment, this utility model is described in further detail.
Referring to Fig. 2, this utility model one framework exposes multi-chip list takes the stacking sandwich encapsulating structure of upside-down mounting, it includes the first lead frame 21, second lead frame 22, 3rd lead frame 23, first chip 24 and the second chip 25, described second lead frame 22 and the 3rd lead frame 23 are Z-shape, described the second Z-shaped lead frame 22 includes horizontal segment 221 on first, first middle linkage section 222 and first time horizontal segment 223, described the 3rd Z-shaped lead frame 23 includes horizontal segment 231 on second, second middle linkage section 232 and second time horizontal segment 233, described first chip 24 is folded on the first lead frame 21 and first between horizontal segment 221, described first chip 24 front is configured on described first lead frame 21, the front and back of described first chip 24 is electrically connected respectively through horizontal segment 221 on tin cream 26 and the first lead frame 21 and first, described second chip 25 is folded on first on horizontal segment 221 and second between horizontal segment 231, described second chip 25 front is configured on described first on horizontal segment 221, the front and back of described second chip 25 is electrically connected respectively through horizontal segment 231 on horizontal segment 221 and second on tin cream 26 and first, described first lead frame 21, second lead frame 22 and the 3rd lead frame 23 outer encapsulating have plastic packaging material 27, described first lead frame 21 lower surface and first time horizontal segment 223 lower surface flush, described first lead frame 21 lower surface, on first time horizontal segment 223 lower surface and second, horizontal segment 231 upper surface is both exposed to outside plastic packaging material 27, described second time horizontal segment 233 lower surface rides upon on the first lead frame 21 upper surface.
Described first lead frame the 21, second lead frame 22 and the 3rd lead frame 23 are general frame, its material can be alloyed copper material, fine copper material, aluminum copper facing material, zinc copper facing material, dilval material, it is also possible to is the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope.
Described first chip 24 and the second chip 25 are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
Its process is as follows:
Step one, referring to Fig. 3 (a), it is provided that the first lead frame, the material of the first lead frame is alloy copper material, fine copper material, aluminum copper facing material, zinc copper facing material, dilval material, it is also possible to be the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope；
Step 2, referring to Fig. 3 (b), it is coated with tin cream by the mode of screen printing in the first lead frame Ji Dao region, purpose is that the area of thickness and opening by adjusting web plate can be accurately controlled the thickness of tin cream, area and position in order to realize follow-up first implanted chip Hou Yuji island joint；
Step 3, referring to Fig. 3 (c), in step 2, the tin cream of the first lead frame Ji Dao region coating implants the first chip, the front of the first chip is by tin cream and the electric connection of the first lead frame；
Step 4, referring to Fig. 3 (d), second lead frame is provided, described second lead frame is Z-shaped, described the second Z-shaped lead frame includes horizontal segment on first, the first middle linkage section and first time horizontal segment, the material of the second lead frame is alloy copper material, fine copper material, aluminum copper facing material, zinc copper facing material, dilval material, it is also possible to be the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope.On the first of the second lead frame, the lower surface of horizontal segment is coated with tin cream by the mode of screen printing, purpose is to be electrically connected for realizing the pin of follow-up second lead frame and the first chip back, and the area of thickness and opening by adjusting web plate can be accurately controlled the thickness of tin cream, area and position；
Step 5, referring to Fig. 3 (e), horizontal segment on the first of second lead frame is pressed together on the first chip of the first lead frame upper surface, making the first chip back and the second lead frame are electrically connected by the tin cream of horizontal segment lower surface on first, after pressing, the first lead frame and the second lead frame form general frame；
Step 6, referring to Fig. 3 (f), the general frame upper and lower surface pressing plate that step 6 is formed is pushed down, carries out Reflow Soldering.The material of pressing plate requires deformation is less likely to occur and has good heat-conductive characteristic, and the thermal coefficient of expansion CTE of its thermal coefficient of expansion CTE and the first lead frame and the second lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C；
Step 7, referring to Fig. 3 (g), after completing Reflow Soldering, on the first of the second lead frame, the upper surface of horizontal segment is coated with tin cream by the mode of screen printing；
Step 8, referring to Fig. 3 (h), in step 8, the tin cream of horizontal segment upper surface coating implants the second chip on the first of the second lead frame, the front of the second chip is by horizontal segment electric connection on tin cream and first；
Step 9, referring to Fig. 3 (i), 3rd lead frame is provided, described 3rd lead frame is Z-shaped, described the 3rd Z-shaped lead frame includes horizontal segment on second, the second middle linkage section and second time horizontal segment, the material of the 3rd lead frame is alloy copper material, fine copper material, aluminum copper facing material, zinc copper facing material, dilval material, it is also possible to be the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope.On the second of the 3rd lead frame, the lower surface of horizontal segment is coated with tin cream by the mode of screen printing, purpose is to be electrically connected for realizing the pin of the subsequent third lead frame and the second chip back, and the area of thickness and opening by adjusting web plate can be accurately controlled the thickness of tin cream, area and position；
Step 10, referring to Fig. 3 (j), horizontal segment on the second of 3rd lead frame is pressed together on the second chip of horizontal segment upper surface on the first of the second lead frame, the second chip back and the 3rd lead frame is made to be electrically connected by the tin cream of horizontal segment lower surface on second, and the 3rd second time horizontal segment lower surface of lead frame ride upon on the first lead frame upper surface, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame；
Step 11, referring to Fig. 3 (k), the general frame upper and lower surface pressing plate that step 10 is formed is pushed down, carries out Reflow Soldering.The material of pressing plate requires deformation is less likely to occur and has good heat-conductive characteristic, and the thermal coefficient of expansion CTE of its thermal coefficient of expansion CTE and the first lead frame, the second lead frame and the 3rd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C；
Step 12, referring to Fig. 3 (l), adopt plastic packaging material to carry out plastic packaging step 11 general frame after Reflow Soldering, after plastic packaging, the upper surface of horizontal segment is exposed to outside plastic packaging material on the second of the 3rd lead frame；
Step 13, referring to Fig. 3 (m), the semi-finished product that step 12 completes plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cut or die-cut independent, and prepared framework exposes multi-chip list takes the stacking sandwich encapsulating structure of upside-down mounting.
In above-mentioned steps, step 5 forms general frame with step 6 the first lead frame pressing the second lead frame and uses pressing plate to carry out Reflow Soldering, it is possible to be carried out after step 8 the second lead frame implants the second chip.
In above-mentioned steps, step 2, step 4 and step 9 can be passed through different platform and carry out simultaneously.
In addition to the implementation, this utility model also includes the technical scheme that other embodiments, all employing equivalents or equivalence substitute mode are formed, and all should fall within this utility model scope of the claims.
Claims (2)
1. a framework exposes multi-chip list and takes the stacking sandwich encapsulating structure of upside-down mounting, it is characterized in that: it includes the first lead frame (21), second lead frame (22), 3rd lead frame (23), first chip (24) and the second chip (25), described second lead frame (22) and the 3rd lead frame (23) are Z-shape, described Z-shaped the second lead frame (22) includes horizontal segment on first (221), first middle linkage section (222) and first time horizontal segment (223), described the 3rd Z-shaped lead frame (23) includes horizontal segment on second (231), second middle linkage section (232) and second time horizontal segment (233), described first chip (24) is folded on the first lead frame (21) and first between horizontal segment (221), described first chip (24) front is configured on described first lead frame (21), the front and back of described first chip (24) is electrically connected with horizontal segment (221) on the first lead frame (21) and first respectively through tin cream (26), described second chip (25) is folded on first on horizontal segment (221) and second between horizontal segment (231), described second chip (25) front is configured on described first on horizontal segment (221), the front and back of described second chip (25) is electrically connected respectively through horizontal segment (231) on horizontal segment (221) and second on tin cream (26) and first, described first lead frame (21), second lead frame (22) and the 3rd lead frame (23) outer encapsulating have plastic packaging material (27), described first lead frame (21) lower surface and first time horizontal segment (223) lower surface flush, described first lead frame (21) lower surface, on first time horizontal segment (223) lower surface and second, horizontal segment (231) upper surface is both exposed to outside plastic packaging material (27), described second time horizontal segment (233) lower surface rides upon on the first lead frame (21) upper surface.
2. a kind of framework according to claim 1 exposes multi-chip list and takes the stacking sandwich encapsulating structure of upside-down mounting, it is characterized in that: the material of described first lead frame, the second lead frame and the 3rd lead frame can be alloyed copper material, fine copper material, aluminum copper facing material, zinc copper facing material, dilval material, it is also possible to is the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521098006.3U CN205355032U (en) | 2015-12-24 | 2015-12-24 | Frame exposes multicore piece singly to be taken flip -chip and piles up double -layered core packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521098006.3U CN205355032U (en) | 2015-12-24 | 2015-12-24 | Frame exposes multicore piece singly to be taken flip -chip and piles up double -layered core packaging structure |
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| Publication Number | Publication Date |
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| CN205355032U true CN205355032U (en) | 2016-06-29 |
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| CN201521098006.3U Active CN205355032U (en) | 2015-12-24 | 2015-12-24 | Frame exposes multicore piece singly to be taken flip -chip and piles up double -layered core packaging structure |
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| Country | Link |
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