CN105633051A - Multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and process method of structure - Google Patents
Multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and process method of structure Download PDFInfo
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- CN105633051A CN105633051A CN201510995934.8A CN201510995934A CN105633051A CN 105633051 A CN105633051 A CN 105633051A CN 201510995934 A CN201510995934 A CN 201510995934A CN 105633051 A CN105633051 A CN 105633051A
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/37124—Aluminium [Al] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and a process method of the structure. The method comprises the following steps of 1, providing a first lead frame; 2, coating the first lead frame with solder paste; 3, implanting a first die and a second die onto the solder paste coating a paddle region of the first lead frame in the step 2; 4, providing a second lead frame, and coating the second lead frame with the solder paste; 5, laminating the second lead frame on the first die and the second die on the upper surface of the first lead frame, wherein the first lead frame and the second lead frame form an integrated framework after lamination; 6, pressing the upper surface and the lower surface of the integrated framework formed in the step 5 with press plates to carry out reflow soldering; 7, carrying out plastic package with a plastic package material; and 8, carrying out cutting or punching operation. The structure and the method have the advantages that the heat dissipation capability of a product is improved, and the package resistance of the product is reduced; and moreover, the whole product can be integratedly formed, and the production efficiency is high.
Description
Technical field
The present invention relates to a kind of part frame to expose multi-chip and take tiling sandwich encapsulation structure and processing method thereof more, belong to technical field of semiconductor encapsulation.
Background technology
In recent years, along with power density is constantly pursued by electronic product, no matter be Diode(diode) or Transistor(triode) encapsulation, especially the MOS product in Transistor is just towards more high-power, smaller szie, more fast, better trend of dispelling the heat is in development. The also slowly even more disposable encapsulation technology spurt of the highly difficult low cost of the high-density of large regions and the challenge towards zonule by single encapsulation technology of the disposable manufacture of encapsulation.
Therefore, also the structure of the various electrical properties being encapsulated in parasitic resistance, electric capacity, inductance etc. of MOS product, encapsulation, the heat dissipation sexuality of encapsulation, the trust aspect of encapsulation and highly difficult disposable encapsulation technology aspect there is more requirement.
Traditional Diode(diode) and Transistor(triode) or the encapsulation of MOS product is general according to product performance, the difference of power and the Consideration of cost, the bonding wire mode of gold thread, silver alloy wire, copper cash, aluminum steel and aluminium band that make use of is as the main interconnection technique of chip and interior pin, thus realizes electrical connection. But the performance of product is present in restriction and the defect of the following aspects by the technical approach of bonding wire:
One, encapsulation and the restriction of manufacture view and defect:
1), Weldability (Bondability) aspect: the puzzlement that the first solder joint that usually can cause because of the change of the parameter sheet change of the change of Metal wire material, metal pins material and equipment and instrument, performance and precision and maintenance and correction management and the void of the 2nd solder joint bonding surface are welded, come off, breakpoint, neck crack, collapse line and short circuit etc. are all, result in and encapsulate that good rate cannot promote, cost cannot decline, the instability of reliability;
2), disposable high-density encapsulation technology aspect: traditional mutual contact mode is nearly all adopt single welding process that chips one chips repeats load, high temperature ultrasonic single line single line adopted by wire on matrix shaped metal lead frame. And in situation be like this load machine of specialty, ball bonding wire bonder, bonding aluminum steel/machinery equipment such as aluminium band machine or copper sheet overlapping machine palikinesia more at a high speed all cannot promote production efficiency, unit cost cannot be reduced, also because equipment constantly promotes the same unstable also improving manufacture of production rate.
Two, the restriction of the characteristic energy aspect of encapsulating products and defect:
1), heat dissipation aspect: traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS, general is all coated by plastic cement, outside only staying external pin to be exposed to plastic packaging body, owing to plastic cement itself is not the material of a kind of thermal conductance, so traditional Diode(diode) and Transistor(triode) or the heat that operationally produces of MOS product is difficult to dissipate by plastic cement the package of plastic cement material, fine wire can only be relied on to be interconnected at the dissipation that heat energy helped by metal pins material, but the dissipation capability of heat is very limited by the approach of this kind of heat dissipation, form the resistance of heat dissipation on the contrary,
2), resistivity (Resistivity) aspect: everybody knows that resistivity (resistivity) is used to represent the physical quantity of various material resistance characteristic. When temperature is certain, having formula R=�� l/s �� to be wherein exactly resistivity, l is the length of material, and s is area. It may be seen that the resistance sizes direct ratio of material is in the length of material, and it is inversely proportional to its area. By the definition of the known resistivity of upper formula: ��=Rs/l. Traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS, bonding wire is adopted to be formed interconnected, thus can clearly know the wire for performing power supply or signal can because, the length of conductor material and the change of sectional area and have influence on the size of resistivity and the loss of contact resistance, the product impact being especially applied in power aspect is obvious especially.
For solving the problem, industry is to traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS has improved, replace bonding wire with metal strip, metal clamping plate, reduce the ability that packaged resistance, inductance and expectation improve heat dissipation.
As shown in Figure 1, for the existing MOS of one encapsulates structure, in this structure, lead frame 11 comprises pipe core welding disc and pin, implants the first chip 12, the 2nd chip 13 on the pipe core welding disc of lead frame 11. The source electrode of the first chip 12 is electrically coupled to lead frame 11 by the first metal clamping plate 14, and the grid of the first chip 12 is electrically coupled to lead frame 11 by the first metal wire 16. The source electrode of the 2nd chip 13 is electrically coupled to lead frame 11 by the 2nd metal clamping plate 15, and the grid of the 2nd chip 13 is electrically coupled to lead frame 11 by the 2nd metal wire 17. Carry out encapsulating again, cut, the subsequent handling such as test. This MOS encapsulates structure metal clamping plate and instead of the bonding wire in conventional MOS encapsulation, reduce part packaged resistance, but still there is following defect: first, this MOS encapsulates the drain electrode of structure chips, source electrode and grid and is formed from lead frame and interconnected to be used different equipment respectively, processing procedure is complicated, and the acquisition cost of equipment is higher; Secondly, this MOS encapsulates structure when metal clamping plate and metal wire being coupled on chip and pin, can only carry out by a chips, cannot whole bar one-body molded, manufacture efficiency is lower.
Summary of the invention
More technical problem to be solved by this invention provides a kind of part frame to expose multi-chip for above-mentioned prior art to take tiling sandwich encapsulation structure and processing method thereof, whole bar product can be one-body molded, production efficiency height, technique is simple, can reduce costs, and there is good thermal diffusivity and lower packaged resistance and inductance.
The present invention's technical scheme adopted that solves the problem is: a kind of part frame exposes multi-chip takes tiling sandwich encapsulation structure more, it comprises the first lead frame, 2nd lead frame, first chip and the 2nd chip, described 2nd lead frame comprises horizontal section on first, section is connected in the middle of first, first time horizontal section, horizontal section on 2nd, section and the 2nd time horizontal section is connected in the middle of 2nd, described first chip and the 2nd chip are folded on the first of the first lead frame and the 2nd lead frame on horizontal section and the 2nd between horizontal section respectively, the front and back of described first chip is respectively by horizontal section and the electric connection of the first lead frame on the first of tin cream and the 2nd lead frame, the front and back of the 2nd chip is respectively by horizontal section and the electric connection of the first lead frame on the 2nd of tin cream and the 2nd lead frame the, described first lead frame and the 2nd lead frame outer encapsulating have plastic cement, on the first of described 2nd lead frame, on horizontal section upper surface and the 2nd, horizontal section upper surface is not put down together, outside described first lead frame lower surface is exposed to plastic cement, outside on the first of described 2nd lead frame, on horizontal section upper surface or the 2nd, in horizontal section upper surface is exposed to plastic cement, first time horizontal section lower surface and the 2nd time horizontal section lower surface of described 2nd lead frame are set up respectively on the first lead frame upper surface.
Described first lead frame and the 2nd lead frame are overall framework.
Part frame exposes the processing method that multi-chip takes tiling sandwich encapsulation structure more, and described method comprises the steps:
Step one, provide the first lead frame;
Step 2, the mode tin coating cream passing through screen printing in the first lead frame Ji Dao region;
Step 3, implants the first chip and the 2nd chip on the tin cream of the first lead frame Ji Dao region coating in step 2;
Step 4,2nd lead frame is provided, described 2nd lead frame comprises horizontal section on first, connects section in the middle of first, connect section and the 2nd time horizontal section in the middle of horizontal section, the 2nd on first time horizontal section, the 2nd, on the first of the 2nd lead frame on horizontal section lower surface, first time horizontal section lower surface, the 2nd horizontal section lower surface and the 2nd time horizontal section lower surface by the mode tin coating cream of screen printing;
Step 5, on the first chip that horizontal section on horizontal section and the 2nd on the first of 2nd lead frame is pressed together on the first lead frame upper surface respectively and the 2nd chip, and the 2nd lead frame first time horizontal section lower surface and the 2nd time horizontal section lower surface set up respectively on the first lead frame upper surface, after pressing, the first lead frame and the 2nd lead frame form overall framework;
Step 6, pushes down the overall framework upper and lower surface pressing plate that step 5 is formed, carries out Reflow Soldering;
Step 7, adopts plastic cement to carry out plastic packaging the overall framework of step 6 after Reflow Soldering, outside after plastic packaging, on horizontal section upper surface and the 2nd, in horizontal section upper surface is exposed to plastic cement on the first of the 2nd lead frame;
Step 8, the work in-process that step 7 completes plastic packaging carry out cutting or die-cut operation, make originally array plastic packaging body, cutting or die-cut independent, and obtained part frame exposes multi-chip takes tiling sandwich encapsulation structure more.
The material of described first lead frame and the 2nd lead frame can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, Rhometal material, it is possible to thinks that other CTE scope is the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
Described first chip and the 2nd chip are two pole chips, three pole chips or the multipole chip that can be combined with metallic tin.
The thermal expansivity CTE of the thermal expansivity CTE of described pressing plate material and the first lead frame, the 2nd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
Described step 2 and step 4 carry out by different platform simultaneously.
Compared with prior art, it is an advantage of the current invention that:
1, a kind of part frame of the present invention expose the 2nd lead frame that multi-chip takes tiling sandwich encapsulation structure more directly source electrode and grid with MOS chip form electric connection, instead of and conventional MOS Chip Packaging utilizes metal wire form interconnected technique, substantially reducing packaged resistance, the technology of the present invention can reduce more than at least 30% than the packaged resistance of conventional package design;
2, a kind of part frame of the present invention exposes the 2nd lead frame that multi-chip takes tiling sandwich encapsulation structure more and directly forms electric connection by the source electrode of tin cream and MOS chip and grid, reduce or remit the interconnected operation of metal wire completely, save the costs such as the equipment purchasing of the interconnected operation of metal wire, operation material completely. And the 2nd lead frame of the present invention be whole article integrated, forming electric connection with chip is also that whole bar one step completes, compared with forming interconnected technique with conventional metals bonding wire, the interconnected chip one by one of tinsel, technique is comparatively simple, and production efficiency is significantly improved;
3, a kind of part frame of the present invention exposes multi-chip and takes tiling sandwich encapsulation structure more and all directly contact with lead frame due to upper and lower two surfaces of chip, the heat produced during chip operation falls apart by lead frame, and outside the first lead frame lower surface of the present invention is directly exposed to plastic cement, the part frame of the present invention exposes multi-chip to be taken tiling sandwich encapsulation structure more and has good heat dispersion; And the present invention can again according to product power, heat conduction or the difference of heat radiation additional scatterer on lead frame freely, in order to increase the ability of product heat dissipation further;
4, a kind of part frame of the present invention exposes multi-chip and takes tiling sandwich encapsulation structure more and use upper press table to push down overall framework to carry out Reflow Soldering, framework is not easily heated the cohesion institute jack-up of process of cooling after melting by tin cream when Reflow Soldering, ensure the total height of skeleton construction, prevent movement or the rotation of chip, and can guarantee that framework exposes the coplanarity of outer pin.
Accompanying drawing explanation
Fig. 1 is that a kind of known MOS encapsulates structural representation.
A kind of part frame of Fig. 2 manufacture of the present invention exposes the side elevational view that multi-chip takes tiling sandwich encapsulation structure more.
A kind of part frame of Fig. 3 manufacture of the present invention exposes the vertical view that multi-chip takes tiling sandwich encapsulation structure more.
Fig. 4 is the three-dimensional view that the present invention has completed the first lead frame of load.
Fig. 5 is the three-dimensional view of the 2nd lead frame in the present invention.
Fig. 6 (a) to Fig. 6 (h) takes, for a kind of part frame of the present invention exposes multi-chip, the schema that tiling sandwich encapsulates structural manufacturing process method more.
Wherein:
Lead frame 11
First chip 12
2nd chip 13
First metal clamping plate 14
2nd metal clamping plate 15
First metal wire 16
2nd metal wire 17
First lead frame 21
2nd lead frame 22
Horizontal section 221 on first
Section 222 is connected in the middle of first
First time horizontal section 223
Horizontal section 224 on 2nd
Section 225 is connected in the middle of 2nd
2nd time horizontal section 226
First chip 23
Tin cream 24
Plastic cement 25
2nd chip 26.
Embodiment
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
As shown in Fig. 6 (a) ~ Fig. 6 (h), a kind of part frame in the present embodiment exposes the processing method that multi-chip takes tiling sandwich encapsulation structure more, and its concrete processing step is as follows:
Step one, see Fig. 6 (a), it is provided that the first lead frame, the material of the first lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, Rhometal material, it is possible to think that other CTE scope is the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C;
Step 2, see Fig. 6 (b), in the first lead frame Ji Dao region by the mode tin coating cream of screen printing, object engages for realizing follow-up first implanted chip Hou Yuji island, can control the thickness of tin cream, area and position accurately by adjusting the area of the thickness of web plate and opening;
Step 3, see Fig. 6 (c), implants the first chip and the 2nd chip on the tin cream of the first lead frame Ji Dao region coating in step 2;
Step 4, see Fig. 6 (d), 2nd lead frame is provided, described 2nd lead frame comprises horizontal section on first, connects section in the middle of first, connect section and the 2nd time horizontal section in the middle of horizontal section, the 2nd on first time horizontal section, the 2nd, the material of the 2nd lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, Rhometal material, it is possible to think that other CTE scope is the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C. On the first of the 2nd lead frame, on horizontal section lower surface, first time horizontal section lower surface, the 2nd, horizontal section lower surface and the 2nd time horizontal section lower surface, by the mode tin coating cream of screen printing, can control the thickness of tin cream, area and position accurately by the area of the thickness and opening that adjust web plate;
Step 5, see Fig. 6 (e), on the first chip that horizontal section on horizontal section and the 2nd on the first of 2nd lead frame is pressed together on the first lead frame upper surface respectively and the 2nd chip, first chip and the 2nd chip are formed by the tin cream of horizontal section lower surface on horizontal section lower surface and the 2nd on first with the 2nd lead frame respectively be electrically connected, and the 2nd lead frame first time horizontal section lower surface and the 2nd time horizontal section lower surface set up respectively on the first lead frame upper surface, after pressing, the first lead frame and the 2nd lead frame form overall framework;
Step 6, see Fig. 6 (f), pushes down the overall framework upper and lower surface pressing plate that step 5 is formed, carries out Reflow Soldering. The material of pressing plate requires deformation to be less likely to occur and has good heat-conductive characteristic, and the thermal expansivity CTE of its thermal expansivity CTE and the first lead frame and the 2nd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C;
Step 7, see Fig. 6 (g), adopts plastic cement to carry out plastic packaging the overall framework of step 6 after Reflow Soldering, outside after plastic packaging, on horizontal section upper surface and the 2nd, in horizontal section upper surface is exposed to plastic cement on the first of the 2nd lead frame;
Step 8, see Fig. 6 (h), the work in-process that step 7 completes plastic packaging carry out cutting or die-cut operation, make originally array plastic packaging body, cutting or die-cut independent, and obtained part frame exposes multi-chip takes tiling sandwich encapsulation structure more.
In above-mentioned steps, step 2 and step 4 carry out by different platform simultaneously.
See Fig. 2 ~ Fig. 5, a kind of part frame of the present invention exposes multi-chip takes tiling sandwich encapsulation structure more, it comprises the first lead frame 21, 2nd lead frame 22, first chip 23 and the 2nd chip 26, described 2nd lead frame 22 comprises horizontal section 221 on first, section 222 is connected in the middle of first, first time horizontal section 223, horizontal section 224 on 2nd, section 225 and the 2nd time horizontal section 226 is connected in the middle of 2nd, described first chip 23 and the 2nd chip 26 are folded on the first of the first lead frame 21 and the 2nd lead frame 22 on horizontal section 221 and the 2nd between horizontal section 224 respectively, the front and back of described first chip 23 is electrically connected by horizontal section 221 on the first of tin cream 24 and the 2nd lead frame 22 and the first lead frame 21 respectively, the front and back of the 2nd chip 26 is electrically connected by horizontal section 224 on the 2nd of tin cream 24 and the 2nd lead frame 22 the and the first lead frame 21 respectively, described first lead frame 21 and the 2nd lead frame 22 outer encapsulating have plastic cement 25, on the first of described 2nd lead frame 22, on horizontal section 221 upper surface and the 2nd, horizontal section 224 upper surface is not put down together, outside described first lead frame 21 lower surface is exposed to plastic cement 25, outside on the first of described 2nd lead frame 22, on horizontal section 221 upper surface and the 2nd, in horizontal section 224 upper surface is exposed to plastic cement 25, first time horizontal section 223 lower surface and the 2nd time horizontal section 226 lower surface of described 2nd lead frame 22 are set up respectively on the first lead frame 21 upper surface.
Described first lead frame 21 and the 2nd lead frame 22 are overall framework, and its material can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, Rhometal material, it is possible to thinks that other CTE scope is the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
Described first chip 23 and the 2nd chip 26 are two pole chips, three pole chips or the multipole chip that can be combined with metallic tin.
In addition to the implementation, the present invention also includes other enforcement modes, the technical scheme that all employing equivalents or equivalence replacement mode are formed, and all should fall within the protection domain of the claims in the present invention.
Claims (7)
1. a part frame exposes multi-chip and takes tiling sandwich encapsulation structure more, it is characterized in that: it comprises the first lead frame (21), 2nd lead frame (22), first chip (23) and the 2nd chip (26), described 2nd lead frame (22) comprises horizontal section on first (221), section (222) is connected in the middle of first, first time horizontal section (223), horizontal section (224) on 2nd, section (225) and the 2nd time horizontal section (226) is connected in the middle of 2nd, described first chip (23) and the 2nd chip (26) are folded on the first of the first lead frame (21) and the 2nd lead frame (22) on horizontal section (221) and the 2nd between horizontal section (224) respectively, the front and back of described first chip (23) is electrically connected by horizontal section (221) on tin cream (24) and the first of the 2nd lead frame (22) and the first lead frame (21) respectively, the front and back of the 2nd chip (26) is electrically connected by horizontal section (224) on tin cream (24) and the 2nd of the 2nd lead frame (22) the and the first lead frame (21) respectively, described first lead frame (21) and the 2nd lead frame (22) outer encapsulating have plastic cement (25), on the first of described 2nd lead frame (22), on horizontal section (221) upper surface and the 2nd, horizontal section (224) upper surface is not put down together, outside described first lead frame (21) lower surface is exposed to plastic cement (25), outside on the first of described 2nd lead frame (22), on horizontal section (221) upper surface or the 2nd, in horizontal section (224) upper surface is exposed to plastic cement (25), first time horizontal section (223) lower surface and the 2nd time horizontal section (226) lower surface of described 2nd lead frame (22) are set up respectively on the first lead frame (21) upper surface.
2. a kind of part frame according to claim 1 exposes multi-chip and takes tiling sandwich encapsulation structure more, it is characterised in that: described first lead frame (21) and the 2nd lead frame (22) are entirety framework.
3. a part frame exposes the processing method that multi-chip takes tiling sandwich encapsulation structure more, it is characterised in that described method comprises the steps:
Step one, provide the first lead frame;
Step 2, the mode tin coating cream passing through screen printing in the first lead frame Ji Dao region;
Step 3, implants the first chip and the 2nd chip on the tin cream of the first lead frame Ji Dao region coating in step 2;
Step 4,2nd lead frame is provided, described 2nd lead frame comprises horizontal section on first, connects section in the middle of first, connect section and the 2nd time horizontal section in the middle of horizontal section, the 2nd on first time horizontal section, the 2nd, on the first of the 2nd lead frame on horizontal section lower surface, first time horizontal section lower surface, the 2nd horizontal section lower surface and the 2nd time horizontal section lower surface by the mode tin coating cream of screen printing;
Step 5, on the first chip that horizontal section on horizontal section and the 2nd on the first of 2nd lead frame is pressed together on the first lead frame upper surface respectively and the 2nd chip, and the 2nd lead frame first time horizontal section lower surface and the 2nd time horizontal section lower surface set up respectively on the first lead frame upper surface, after pressing, the first lead frame and the 2nd lead frame form overall framework;
Step 6, pushes down the overall framework upper and lower surface pressing plate that step 5 is formed, carries out Reflow Soldering;
Step 7, adopts plastic cement to carry out plastic packaging the overall framework of step 6 after Reflow Soldering,
Outside after plastic packaging, on horizontal section upper surface and the 2nd, in horizontal section upper surface is exposed to plastic cement on the first of the 2nd lead frame;
Step 8, the work in-process that step 7 completes plastic packaging carry out cutting or die-cut operation, make originally array plastic packaging body, cutting or die-cut independent, and obtained part frame exposes multi-chip takes tiling sandwich encapsulation structure more.
4. a kind of part frame according to claim 3 exposes the processing method that multi-chip takes tiling sandwich encapsulation structure more, it is characterized in that: described first lead frame and the 2nd lead frame are overall framework, its material can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, Rhometal material, it is possible to thinks that other CTE scope is the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
5. a kind of part frame according to claim 3 exposes the processing method that multi-chip takes tiling sandwich encapsulation structure more, it is characterised in that: described first chip and the 2nd chip are two pole chips, three pole chips or the multipole chip that can be combined with metallic tin.
6. a kind of part frame according to claim 3 exposes the processing method that multi-chip takes tiling sandwich encapsulation structure more, it is characterized in that: the thermal expansivity CTE of the thermal expansivity CTE of described pressing plate material and the first lead frame, the 2nd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
7. a kind of part frame according to claim 3 exposes the processing method that multi-chip takes tiling sandwich encapsulation structure more, it is characterised in that: described step 2 and step 4 carry out by different platform simultaneously.
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| CN110164775A (en) * | 2019-06-04 | 2019-08-23 | 无锡中微高科电子有限公司 | High power MOS chip and control chip portfolio encapsulating structure and packaging method |
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