CN105405833A - Multi-chip multi-overlap flat-paved sandwich encapsulation structure and technological process thereof - Google Patents

Multi-chip multi-overlap flat-paved sandwich encapsulation structure and technological process thereof Download PDF

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Publication number
CN105405833A
CN105405833A CN201510990247.7A CN201510990247A CN105405833A CN 105405833 A CN105405833 A CN 105405833A CN 201510990247 A CN201510990247 A CN 201510990247A CN 105405833 A CN105405833 A CN 105405833A
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China
Prior art keywords
lead frame
chip
horizontal segment
encapsulating structure
takes
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CN201510990247.7A
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Inventor
刘恺
梁志忠
王赵云
陈益新
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CN201510990247.7A priority Critical patent/CN105405833A/en
Publication of CN105405833A publication Critical patent/CN105405833A/en
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract

The invention relates to a multi-chip multi-overlap flat-paved sandwich encapsulation structure and a technological process thereof. The method comprises the following steps: (1), providing a first lead frame; (2), coating a solder paste on the first lead frame; (3), implanting a first chip and a second chip in the solder paste coated in the base island area of the first lead frame in the step (2); (4), providing a second lead frame, and coating the solder paste on the second lead frame; (5), pressing the second lead frame on the first chip and the second chip on the upper surface of the first lead frame, wherein the first lead frame and the second lead frame form an integrated framework after being pressed; (6), pressing the upper and lower surface of the integrated framework formed in the step (5) by using a pressure plate, and performing reflow soldering; (7), plastically encapsulating by using a plastic encapsulating material; and (8), cutting or punching. The method disclosed by the invention has the benefits that: the heat dissipation capability of a product is increased; the encapsulation resistance of the product can be reduced; furthermore, the whole product can be integrally formed; and the production efficiency is high.

Description

A kind of multi-chip takes tiling sandwich encapsulating structure and process thereof more
Technical field
The present invention relates to a kind of multi-chip and take tiling sandwich encapsulating structure and process thereof more, belong to technical field of semiconductor encapsulation.
Background technology
In recent years, along with electronic product is constantly pursued power density, no matter be Diode(diode) or Transistor(triode) encapsulation, the MOS product especially in Transistor is just towards more high-power, smaller szie, more fast, better trend of dispelling the heat is in development.The disposable manufacture also slowly even more disposable encapsulation technology spurt of the highly difficult low cost of the high density of large regions and the challenge towards zonule by single encapsulation technology of encapsulation.
Therefore, also more requirement has been had to the structure of the various electrical properties being encapsulated in parasitic resistance, electric capacity, inductance etc. of MOS product, encapsulation, the dissipation of heat sexuality of encapsulation, the reliability aspect of encapsulation and highly difficult disposable encapsulation technology aspect.
Traditional Diode(diode) and Transistor(triode) or the encapsulation of MOS product is general according to product performance, the difference of power and the Consideration of cost, the bonding wire mode that make use of gold thread, silver alloy wire, copper cash, aluminum steel and aluminium strip as the main interconnection technique of chip and interior pin, thus realizes electrical connection.But the performance of the technical approach of bonding wire to product is present in restriction and the defect of the following aspects:
One, encapsulation and the restriction of manufacture view and defect:
1), Weldability (Bondability) aspect: usually can change because of the parameter sheet of the change of Metal wire material, metal pins material and equipment and instrument, the change of performance and precision and maintain and correct manage and the rosin joint of the first solder joint of causing and the second solder joint faying face, come off, puzzlement that breakpoint, neck crack, collapse line and short circuit etc. are all, yield cannot promote, cost cannot decline, the instability of reliability to result in encapsulation;
2), disposable high-density encapsulation technology aspect: traditional mutual contact mode is nearly all adopt the welding manner that single chips one chips repeats load, high temperature ultrasonic single line single line adopted by wire in matrix type die-attach area.And be like this loader of specialty in situation, ball bonding wire bonder, bonding aluminum steel/machinery equipment such as aluminium strip machine or copper sheet overlapping machine repetitive operation more at a high speed all cannot improving production efficiency, unit cost cannot be reduced, also because equipment constantly promotes the same unsteadiness also improving manufacture of speed of production.
Two, the restriction of the special aspect of performance of encapsulating products and defect:
1), dissipation of heat aspect: traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS, general is all coated by plastic packaging material, external pin is only stayed to be exposed to outside plastic-sealed body, due to the material that plastic packaging material itself is not a kind of thermal conductance, so traditional Diode(diode) and Transistor(triode) or operationally the produced heat of MOS product is difficult to dissipate by plastic packaging material the packaging body of plastic packaging material material, fine wire can only be relied on to be interconnected at the dissipation that heat energy helped by metal pins material, but the dissipation capability of the approach of this dissipation of heat to heat is very limited, form the resistance of the dissipation of heat on the contrary,
2), resistivity (Resistivity) aspect: resistivity (resistivity) is used to the physical quantity representing various material resistance characteristic as you know.When temperature is certain, have formula R=ρ l/s ρ to be wherein exactly resistivity, l is the length of material, and s is area.Can find out, the resistance sizes of material is proportional to the length of material, and is inversely proportional to its area.Definition by the known resistivity of above formula: ρ=Rs/l.Traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS, bonding wire is adopted to be formed interconnected, can clearly know thus wire for performing power supply or signal can because, the length of conductor material and the change of sectional area and have influence on the size of resistivity and the loss of contact resistance, the product impact being especially applied in power aspect is obvious especially.
For solving the problem, industry is to traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS improves, replace bonding wire with metal tape, metal splint, reduce the ability that packaged resistance, inductance and expectation improve the dissipation of heat.
As shown in Figure 1, be the existing MOS encapsulating structure of one, in this structure, lead frame 11 comprises pipe core welding disc and pin, and the pipe core welding disc of lead frame 11 is implanted the first chip 12, second chip 13.The source electrode of the first chip 12 is electrically coupled to lead frame 11 by the first metal splint 14, and the grid of the first chip 12 is electrically coupled to lead frame 11 by the first metal bonding wire 16.The source electrode of the second chip 13 is electrically coupled to lead frame 11 by the second metal splint 15, and the grid of the second chip 13 is electrically coupled to lead frame 11 by the second metal bonding wire 17.Carry out again encapsulating, cut, the subsequent handling such as test.This MOS encapsulating structure metal splint instead of the bonding wire in conventional MOS encapsulation, reduce partial encapsulation resistance, but still there is following defect: first, the drain electrode of this MOS encapsulating structure chips, source electrode and grid and lead frame are formed interconnectedly will use different equipment respectively, processing procedure is complicated, and the acquisition cost of equipment is higher; Secondly, this MOS encapsulating structure, when metal splint and metal bonding wire are coupled on chip and pin, can only carry out by a chips, cannot whole piece one-body molded, manufacture efficiency is lower.
Summary of the invention
More technical problem to be solved by this invention provides a kind of multi-chip to take tiling sandwich encapsulating structure and process thereof for above-mentioned prior art, whole piece product can be one-body molded, production efficiency is high, technique is simple, can reduce costs, and there is good thermal diffusivity and lower packaged resistance and inductance.
The present invention's adopted technical scheme that solves the problem is: a kind of multi-chip takes tiling sandwich encapsulating structure more, it comprises the first lead frame, two the second lead frames, first chip and the second chip, described second lead frame is Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, first middle linkage section and first time horizontal segment, described first chip and the second chip be folded in respectively the first lead frame and two the second lead frames first between horizontal segment, the front and back of described first chip and the front and back of the second chip are electrically connected respectively by horizontal segment on first of its corresponding second lead frame of tin cream and the first lead frame, described first lead frame and two the second lead frame outer encapsulatings have plastic packaging material, described first lead frame lower surface is all exposed to outside plastic packaging material, first time horizontal segment lower surface of described two the second lead frames is set up respectively on the first lead frame upper surface.
Described first lead frame and the second lead frame are general frame.
Multi-chip takes a process for tiling sandwich encapsulating structure more, and described method comprises the steps:
Step one, provide the first lead frame;
Step 2, apply tin cream in the first lead frame Ji Dao region by the mode of screen printing;
The tin cream of step 3, the first lead frame Ji Dao region coating in step 2 implants the first chip and the second chip;
Step 4, provide the second lead frame, second lead frame comprises horizontal segment, the second middle linkage section and second time horizontal segment on horizontal segment on first, the first middle linkage section, first time horizontal segment, second, and on first of the second lead frame, on horizontal segment lower surface, first time horizontal segment lower surface, second, horizontal segment lower surface and second time horizontal segment lower surface apply tin cream by the mode of screen printing;
On step 5, the first chip that horizontal segment on horizontal segment and second on first of the second lead frame is pressed together on the first lead frame upper surface respectively and the second chip, and first of the second lead frame time horizontal segment lower surface and second time horizontal segment lower surface are set up respectively on the first lead frame upper surface, after pressing, the first lead frame and the second lead frame form general frame;
Step 6, by step 5 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 7, adopts plastic packaging material to carry out plastic packaging the general frame of step 6 after Reflow Soldering;
Step 8, semi-finished product step 7 being completed plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, and obtained multi-chip takes tiling sandwich encapsulating structure more.
The material of described first lead frame and the second lead frame can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.
Described first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
The thermal coefficient of expansion CTE of the thermal coefficient of expansion CTE of described pressing plate material and the first lead frame, the second lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
Described step 2 and step 4 are carried out by different platform simultaneously.
Compared with prior art, the invention has the advantages that:
1, a kind of multi-chip of the present invention take tiling sandwich encapsulating structure more the second lead frame directly and the source electrode of MOS chip and grid formed and be electrically connected, instead of in conventional MOS chip package and utilize metal welding line to form interconnected technique, substantially reduce packaged resistance, technology of the present invention can reduce more than at least 30% than the packaged resistance of conventional package design;
2, the second lead frame that a kind of multi-chip of the present invention takes tiling sandwich encapsulating structure more is directly formed by the source electrode of tin cream and MOS chip and grid and is electrically connected, reduce or remit the interconnected operation of metal bonding wire completely, save the cost such as the equipment purchasing of the interconnected operation of metal bonding wire, operation material completely.And the second lead frame of the present invention is that whole piece is integrated, form with chip that to be electrically connected also be that whole piece one step completes, compared with forming interconnected technique with conventional metals bonding wire, the interconnected chip one by one of sheet metal, technique is comparatively simple, and production efficiency is significantly improved;
3, a kind of multi-chip of the present invention is taken tiling sandwich encapsulating structure due to upper and lower two surfaces of chip more and is all directly contacted with lead frame, the heat produced during chip operation sheds by lead frame, and the first lead frame lower surface of the present invention is directly exposed to outside plastic packaging material, multi-chip of the present invention is taken tiling sandwich encapsulating structure more and is had good heat dispersion; And the present invention can again according to product power, heat conduction or the difference of heat radiation additional radiator on lead frame freely, in order to increase the ability of the product dissipation of heat further;
4, a kind of multi-chip of the present invention is taken tiling sandwich encapsulating structure more and is used upper lower platen to push down general frame to carry out Reflow Soldering, framework to be not easily heated the cohesion institute jack-up of cooling procedure after melting by tin cream when Reflow Soldering, ensure the total height of frame structure, prevent movement or the rotation of chip, and can guarantee that framework exposes the coplanarity of outer pin.
Accompanying drawing explanation
Fig. 1 is a kind of known MOS encapsulating structure schematic diagram.
Fig. 2 is the side view that a kind of multi-chip that the present invention manufactures takes tiling sandwich encapsulating structure more.
Fig. 3 is the vertical view that a kind of multi-chip that the present invention manufactures takes tiling sandwich encapsulating structure more.
Fig. 4 is the three-dimensional view that the present invention has completed the first lead frame of load.
Fig. 5 is the three-dimensional view of the second lead frame in the present invention.
Fig. 6 (a) to Fig. 6 (h) takes the flow chart of tiling sandwich encapsulating structure process for a kind of multi-chip of the present invention more.
Wherein:
Lead frame 11
First chip 12
Second chip 13
First metal splint 14
Second metal splint 15
First metal bonding wire 16
Second metal bonding wire 17
First lead frame 21
Second lead frame 22
Horizontal segment 221 on first
First middle linkage section 222
First time horizontal segment 223
Horizontal segment 224 on second
Second middle linkage section 225
Second time horizontal segment 226
First chip 23
Tin cream 24
Plastic packaging material 25
Second chip 26.
Embodiment
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
As shown in Fig. 6 (a) ~ Fig. 6 (h), a kind of multi-chip in the present embodiment takes the process of tiling sandwich encapsulating structure more, and its concrete technology step is as follows:
Step one, see Fig. 6 (a), provide the first lead frame, the material of the first lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C;
Step 2, see Fig. 6 (b), tin cream is applied by the mode of screen printing in the first lead frame Ji Dao region, object engages for realizing follow-up first implanted chip Hou Yuji island, can control the thickness of tin cream, area and position accurately by the adjustment thickness of web plate and the area of opening;
Step 3, see Fig. 6 (c), in step 2 first lead frame Ji Dao region coating tin cream on implant the first chip and the second chip;
Step 4, see Fig. 6 (d), second lead frame is provided, second lead frame comprises horizontal segment, the second middle linkage section and second time horizontal segment on horizontal segment on first, the first middle linkage section, first time horizontal segment, second, the material of the second lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.On first of the second lead frame, on horizontal segment lower surface, first time horizontal segment lower surface, second, horizontal segment lower surface and second time horizontal segment lower surface apply tin cream by the mode of screen printing, can control the thickness of tin cream, area and position accurately by the adjustment thickness of web plate and the area of opening;
Step 5, see Fig. 6 (e), on the first chip that horizontal segment on horizontal segment and second on first of second lead frame is pressed together on the first lead frame upper surface respectively and the second chip, first chip and the second chip are formed by the tin cream of horizontal segment lower surface on horizontal segment lower surface and second on first with the second lead frame be respectively electrically connected, and first of the second lead frame time horizontal segment lower surface and second time horizontal segment lower surface are set up respectively on the first lead frame upper surface, after pressing, the first lead frame and the second lead frame form general frame;
Step 6, see Fig. 6 (f), by step 5 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering.The material of pressing plate requires deformation is less likely to occur and has good heat-conductive characteristic, and the thermal coefficient of expansion CTE of its thermal coefficient of expansion CTE and the first lead frame and the second lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C;
Step 7, see Fig. 6 (g), plastic packaging material is adopted to carry out plastic packaging the general frame of step 6 after Reflow Soldering;
Step 8, see Fig. 6 (h), semi-finished product step 7 being completed plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, and obtained multi-chip takes tiling sandwich encapsulating structure more.
In above-mentioned steps, step 2 and step 4 are carried out by different platform simultaneously.
See Fig. 2 ~ Fig. 5, a kind of multi-chip of the present invention takes tiling sandwich encapsulating structure more, it comprises the first lead frame 21, second lead frame 22, first chip 23 and the second chip 26, described second lead frame 22 comprises horizontal segment 221 on first, first middle linkage section 222, first time horizontal segment 223, horizontal segment 224 on second, second middle linkage section 225 and second time horizontal segment 226, described first chip 23 and the second chip 26 be folded in respectively the first lead frame 21 and the second lead frame 22 first on horizontal segment 221 and second between horizontal segment 224, the front and back of described first chip 23 is electrically connected respectively by horizontal segment 221 on first of tin cream 24 and the second lead frame 22 and the first lead frame 21, the front and back of the second chip 26 is electrically connected respectively by horizontal segment 224 on second of tin cream 24 and the second lead frame 22 and the first lead frame 21, described first lead frame 21 and the second lead frame 22 outer encapsulating have plastic packaging material 25, described first lead frame 21 lower surface is all exposed to outside plastic packaging material 25, first time horizontal segment 223 lower surface and second time horizontal segment 226 lower surface of described second lead frame 22 are set up respectively on the first lead frame 21 upper surface.
Described first lead frame 21 and the second lead frame 22 are general frame, and its material can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.
Described first chip 23 and the second chip 26 are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
In addition to the implementation, the present invention also includes other execution modes, the technical scheme that all employing equivalents or equivalent substitute mode are formed, within the protection range that all should fall into the claims in the present invention.

Claims (7)

1. a multi-chip takes tiling sandwich encapsulating structure more, it is characterized in that: it comprises the first lead frame (21), two the second lead frames (22), first chip (23) and the second chip (26), described second lead frame (22) is in Z-shaped, described Z-shaped the second lead frame (22) comprises horizontal segment on first (221), first middle linkage section (222) and first time horizontal segment (223), described first chip (23) and the second chip (26) be folded in respectively the first lead frame (21) and two the second lead frames (22) first between horizontal segment (221), the front and back of described first chip (23) and the front and back of the second chip (26) are electrically connected respectively by horizontal segment (221) on first of its corresponding second lead frame (22) of tin cream (24) and the first lead frame (21), described first lead frame (21) and two the second lead frame (22) outer encapsulatings have plastic packaging material (27), described first lead frame (21) lower surface is all exposed to outside plastic packaging material (27), first time horizontal segment (223) lower surface of described two the second lead frames (22) is set up respectively on the first lead frame (21) upper surface.
2. a kind of multi-chip according to claim 1 takes tiling sandwich encapsulating structure more, it is characterized in that: described first lead frame (21) and the second lead frame (22) are general frame.
3. multi-chip takes a process for tiling sandwich encapsulating structure more, it is characterized in that described method comprises the steps:
Step one, provide the first lead frame;
Step 2, apply tin cream in the first lead frame Ji Dao region by the mode of screen printing;
The tin cream of step 3, the first lead frame Ji Dao region coating in step 2 implants the first chip and the second chip;
Step 4, provide the second lead frame, described second lead frame comprises horizontal segment, the second middle linkage section and second time horizontal segment on horizontal segment on first, the first middle linkage section, first time horizontal segment, second, and on first of the second lead frame, on horizontal segment lower surface, first time horizontal segment lower surface, second, horizontal segment lower surface and second time horizontal segment lower surface apply tin cream by the mode of screen printing;
On step 5, the first chip that horizontal segment on horizontal segment and second on first of the second lead frame is pressed together on the first lead frame upper surface respectively and the second chip, and first of the second lead frame time horizontal segment lower surface and second time horizontal segment lower surface are set up respectively on the first lead frame upper surface, after pressing, the first lead frame and the second lead frame form general frame;
Step 6, by step 5 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 7, adopts plastic packaging material to carry out plastic packaging the general frame of step 6 after Reflow Soldering;
Step 8, semi-finished product step 7 being completed plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, and obtained multi-chip takes tiling sandwich encapsulating structure more.
4. a kind of multi-chip according to claim 3 takes the process of tiling sandwich encapsulating structure more, it is characterized in that: described first lead frame and the second lead frame are general frame, its material can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.
5. a kind of multi-chip according to claim 3 takes the process of tiling sandwich encapsulating structure more, it is characterized in that: described first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
6. a kind of multi-chip according to claim 3 takes the process of tiling sandwich encapsulating structure more, it is characterized in that: the thermal coefficient of expansion CTE of the thermal coefficient of expansion CTE of described pressing plate material and the first lead frame, the second lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
7. a kind of multi-chip according to claim 3 takes the process of tiling sandwich encapsulating structure more, it is characterized in that: described step 2 and step 4 are carried out by different platform simultaneously.
CN201510990247.7A 2015-12-24 2015-12-24 Multi-chip multi-overlap flat-paved sandwich encapsulation structure and technological process thereof Pending CN105405833A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098565A (en) * 2016-07-04 2016-11-09 重庆平伟实业股份有限公司 The production method of two-side radiation band pin thin flat encapsulation power semiconductor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515551A (en) * 2008-02-22 2009-08-26 株式会社瑞萨科技 Manufacturing method of semiconductor device
US20090212405A1 (en) * 2008-02-26 2009-08-27 Yong Liu Stacked die molded leadless package
CN101567367A (en) * 2004-01-28 2009-10-28 株式会社瑞萨科技 Semiconductor device
CN102237343A (en) * 2010-05-05 2011-11-09 万国半导体有限公司 Semiconductor package realizing connection by connecting sheets and manufacturing method for semiconductor package
US20140361419A1 (en) * 2013-06-10 2014-12-11 Yan Xun Xue Power control device and preparation method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101567367A (en) * 2004-01-28 2009-10-28 株式会社瑞萨科技 Semiconductor device
CN101515551A (en) * 2008-02-22 2009-08-26 株式会社瑞萨科技 Manufacturing method of semiconductor device
US20090212405A1 (en) * 2008-02-26 2009-08-27 Yong Liu Stacked die molded leadless package
CN102237343A (en) * 2010-05-05 2011-11-09 万国半导体有限公司 Semiconductor package realizing connection by connecting sheets and manufacturing method for semiconductor package
US20140361419A1 (en) * 2013-06-10 2014-12-11 Yan Xun Xue Power control device and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098565A (en) * 2016-07-04 2016-11-09 重庆平伟实业股份有限公司 The production method of two-side radiation band pin thin flat encapsulation power semiconductor

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