CN105405834A - Multi-chip and multi-shingle stacked sandwich package structure with exposed frames and technique of multi-chip and multi-shingle stacked sandwich package structure - Google Patents

Multi-chip and multi-shingle stacked sandwich package structure with exposed frames and technique of multi-chip and multi-shingle stacked sandwich package structure Download PDF

Info

Publication number
CN105405834A
CN105405834A CN201510995486.1A CN201510995486A CN105405834A CN 105405834 A CN105405834 A CN 105405834A CN 201510995486 A CN201510995486 A CN 201510995486A CN 105405834 A CN105405834 A CN 105405834A
Authority
CN
China
Prior art keywords
lead frame
chip
horizontal segment
frame
exposes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510995486.1A
Other languages
Chinese (zh)
Inventor
梁志忠
王亚琴
徐赛
朱悦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201510995486.1A priority Critical patent/CN105405834A/en
Publication of CN105405834A publication Critical patent/CN105405834A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49537Plurality of lead frames mounted in one device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L21/603Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074Stacked arrangements of non-apertured devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754Coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

The invention relates to a multi-chip and multi-shingle stacked sandwich package structure with exposed frames and a technique of the multi-chip and multi-shingle stacked sandwich package structure. The method comprises the following steps: (1) providing a first lead frame; (2) coating the first lead frame with a tin paste; (3) implanting a first chip into the tin paste of the first lead frame; (4) providing a second lead frame, coating the second lead frame with the tin paste; (5) laminating the second lead frame on the first chip; (6) carrying out reflow soldering; (7) coating the second lead frame with the tin paste; (8) implanting a second chip into the second lead frame; (9) providing a third lead frame, coating the third lead frame with the tin paste; (10) laminating the third lead frame on the second chip; (11) carrying out reflow soldering; (12) carrying out plastic packaging with a molding compound; and (13) carrying out a cutting or punching operation. The multi-chip and multi-shingle stacked sandwich package structure with the exposed frames have the beneficial effects that the heat dissipating ability of a product is increased; and the package resistance of the product is reduced.

Description

A kind of framework exposes multi-chip takes stacking sandwich encapsulating structure and process thereof more
Technical field
The present invention relates to a kind of framework to expose multi-chip and take stacking sandwich encapsulating structure and process thereof more, belong to technical field of semiconductor encapsulation.
Background technology
In recent years, along with electronic product is constantly pursued power density, no matter be Diode(diode) or Transistor(triode) encapsulation, the MOS product especially in Transistor is just towards more high-power, smaller szie, more fast, better trend of dispelling the heat is in development.The disposable manufacture also slowly even more disposable encapsulation technology spurt of the highly difficult low cost of the high density of large regions and the challenge towards zonule by single encapsulation technology of encapsulation.
Therefore, also more requirement has been had to the structure of the various electrical properties being encapsulated in parasitic resistance, electric capacity, inductance etc. of MOS product, encapsulation, the dissipation of heat sexuality of encapsulation, the reliability aspect of encapsulation and highly difficult disposable encapsulation technology aspect.
Traditional Diode(diode) and Transistor(triode) or the encapsulation of MOS product is general according to product performance, the difference of power and the Consideration of cost, the bonding wire mode that make use of gold thread, silver alloy wire, copper cash, aluminum steel and aluminium strip as the main interconnection technique of chip and interior pin, thus realizes electrical connection.But the performance of the technical approach of bonding wire to product is present in restriction and the defect of the following aspects:
One, encapsulation and the restriction of manufacture view and defect:
1), Weldability (Bondability) aspect: usually can change because of the parameter sheet of the change of Metal wire material, metal pins material and equipment and instrument, the change of performance and precision and maintain and correct manage and the rosin joint of the first solder joint of causing and the second solder joint faying face, come off, puzzlement that breakpoint, neck crack, collapse line and short circuit etc. are all, yield cannot promote, cost cannot decline, the instability of reliability to result in encapsulation;
2), disposable high-density encapsulation technology aspect: traditional mutual contact mode is nearly all adopt the welding manner that single chips one chips repeats load, high temperature ultrasonic single line single line adopted by wire in matrix type die-attach area.And be like this loader of specialty in situation, ball bonding wire bonder, bonding aluminum steel/machinery equipment such as aluminium strip machine or copper sheet overlapping machine repetitive operation more at a high speed all cannot improving production efficiency, unit cost cannot be reduced, also because equipment constantly promotes the same unsteadiness also improving manufacture of speed of production.
Two, the restriction of the special aspect of performance of encapsulating products and defect:
1), dissipation of heat aspect: traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS, general is all coated by plastic packaging material, external pin is only stayed to be exposed to outside plastic-sealed body, due to the material that plastic packaging material itself is not a kind of thermal conductance, so traditional Diode(diode) and Transistor(triode) or operationally the produced heat of MOS product is difficult to dissipate by plastic packaging material the packaging body of plastic packaging material material, fine wire can only be relied on to be interconnected at the dissipation that heat energy helped by metal pins material, but the dissipation capability of the approach of this dissipation of heat to heat is very limited, form the resistance of the dissipation of heat on the contrary,
2), resistivity (Resistivity) aspect: resistivity (resistivity) is used to the physical quantity representing various material resistance characteristic as you know.When temperature is certain, have formula R=ρ l/s ρ to be wherein exactly resistivity, l is the length of material, and s is area.Can find out, the resistance sizes of material is proportional to the length of material, and is inversely proportional to its area.Definition by the known resistivity of above formula: ρ=Rs/l.Traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS, bonding wire is adopted to be formed interconnected, can clearly know thus wire for performing power supply or signal can because, the length of conductor material and the change of sectional area and have influence on the size of resistivity and the loss of contact resistance, the product impact being especially applied in power aspect is obvious especially.
For solving the problem, industry is to traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS improves, replace bonding wire with metal tape, metal splint, reduce the ability that packaged resistance, inductance and expectation improve the dissipation of heat.
As shown in Figure 1, be the existing MOS stack package structure of one, in this structure, lead frame 11 comprises pipe core welding disc and pin, and the pipe core welding disc of lead frame 11 is implanted the first chip 12.The source electrode of the first chip 12 is electrically coupled to pin by the first metal splint 14, and the grid of the first chip 12 is electrically coupled to pin by the first metal bonding wire 16.Then the source electrode implanting the second chip 13, second chip 13 on the first metal splint 14 is electrically coupled to pin by the second metal splint 15, and the grid of the second chip 13 is electrically coupled to pin by the second metal bonding wire 17.Carry out again encapsulating, cut, the subsequent handling such as test.This MOS encapsulating structure metal splint instead of the bonding wire in conventional MOS encapsulation, reduce partial encapsulation resistance, but still there is following defect: first, the drain electrode of this MOS encapsulating structure chips, source electrode and grid and lead frame are formed interconnectedly will use different equipment respectively, processing procedure is complicated, and the acquisition cost of equipment is higher; Secondly, this MOS encapsulating structure, when metal splint and metal bonding wire are coupled on chip and pin, can only carry out by a chips, cannot whole piece one-body molded, manufacture efficiency is lower.
Summary of the invention
More technical problem to be solved by this invention provides a kind of framework to expose multi-chip for above-mentioned prior art to take stacking sandwich encapsulating structure and process thereof, whole piece product can be one-body molded, production efficiency is high, technique is simple, can reduce costs, and there is good thermal diffusivity and lower packaged resistance and inductance.
The present invention's adopted technical scheme that solves the problem is: a kind of framework exposes multi-chip takes stacking sandwich encapsulating structure more, it comprises the first lead frame, second lead frame, 3rd lead frame, first chip and the second chip, described second lead frame and the 3rd lead frame are Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, first middle linkage section and first time horizontal segment, described the 3rd Z-shaped lead frame comprises horizontal segment on second, second middle linkage section and second time horizontal segment, described first chip gripper to be located on the first lead frame and first between horizontal segment, the front and back of described first chip is electrically connected respectively by horizontal segment on tin cream and first and the first lead frame, described second chip gripper to be located on first on horizontal segment and second between horizontal segment, the front and back of described second chip is electrically connected respectively by horizontal segment on horizontal segment and first on tin cream and second, described first lead frame, second lead frame and the 3rd lead frame outer encapsulating have plastic packaging material, on described first lead frame lower surface and second, horizontal segment upper surface is all exposed to outside plastic packaging material, described first time horizontal segment lower surface and second time horizontal segment lower surface are set up on the first lead frame upper surface.
Described first lead frame, the second lead frame and the 3rd lead frame are general frame.
Framework exposes the process that multi-chip takes stacking sandwich encapsulating structure more, and described method comprises the steps:
Step one, provide the first lead frame;
Step 2, apply tin cream in the first lead frame Ji Dao region by the mode of screen printing;
The tin cream of step 3, the first lead frame Ji Dao region coating in step 2 implants the first chip;
Step 4, provide the second lead frame, described second lead frame is Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, the first middle linkage section and first time horizontal segment, and on first of the second lead frame, horizontal segment lower surface and first time horizontal segment lower surface apply tin cream by the mode of screen printing;
Step 5, horizontal segment on first of the second lead frame is pressed together on the first chip of the first lead frame upper surface, and first of the second lead frame time horizontal segment lower surface is set up on the first lead frame upper surface, after pressing, the first lead frame and the second lead frame form general frame;
Step 6, by step 5 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 7, complete Reflow Soldering after, on first of the second lead frame, the upper surface of horizontal segment applies tin cream by the mode of screen printing;
Step 8, in step 7 the second lead frame first on horizontal segment upper surface coating tin cream on implant the second chip;
Step 9, provide the 3rd lead frame, described 3rd lead frame is Z-shaped, described the 3rd Z-shaped lead frame comprises horizontal segment on second, the second middle linkage section and second time horizontal segment, and on second of the 3rd lead frame, horizontal segment lower surface and second time horizontal segment lower surface apply tin cream by the mode of screen printing;
Step 10, horizontal segment on second of the 3rd lead frame is pressed together on the second lead frame first on horizontal segment upper surface the second chip on, and second time horizontal segment lower surface of the 3rd lead frame is set up on the first lead frame upper surface, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame;
Step 11, by step 10 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 12, adopt plastic packaging material to carry out plastic packaging the general frame of step 11 after Reflow Soldering, after plastic packaging the 3rd lead frame second on the upper surface of horizontal segment be exposed to outside plastic packaging material;
Step 13, semi-finished product step 12 being completed plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, and obtained framework exposes multi-chip takes stacking sandwich encapsulating structure more.
Described first lead frame pressing second lead frame forms general frame, can implement after the second lead frame implants the second chip.
The material of described first lead frame, the second lead frame and the 3rd lead frame can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.
Described first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
The thermal coefficient of expansion CTE of the thermal coefficient of expansion CTE of described pressing plate material and the first lead frame, the second lead frame and the 3rd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
Described step 2, step 4 and step 9 are carried out by different platform simultaneously.
Compared with prior art, the invention has the advantages that:
1, a kind of framework of the present invention expose multi-chip take more the second lead frame of stacking sandwich encapsulating structure and the 3rd lead frame directly and the source electrode of MOS chip and grid formed and be electrically connected, instead of in conventional MOS chip package and utilize metal welding line to form interconnected technique, substantially reduce packaged resistance, technology of the present invention can reduce more than at least 30% than the packaged resistance of conventional package design;
2, a kind of framework of the present invention is exposed multi-chip and takes the second lead frame of stacking sandwich encapsulating structure and the 3rd lead frame more and directly formed by the source electrode of tin cream and MOS chip and grid and be electrically connected, reduce or remit the interconnected operation of metal bonding wire completely, save the cost such as the equipment purchasing of the interconnected operation of metal bonding wire, operation material completely.And the second lead frame of the present invention and the 3rd lead frame are all that whole piece is integrated, form with chip that to be electrically connected also be that whole piece one step completes, compared with forming interconnected technique with conventional metals bonding wire, the interconnected chip one by one of sheet metal, technique is comparatively simple, and production efficiency is significantly improved;
3, a kind of framework of the present invention exposes multi-chip and takes stacking sandwich encapsulating structure due to upper and lower two surfaces of chip more and all directly contact with lead frame, the heat produced during chip operation sheds by lead frame, and the first lead frame lower surface of the present invention and the 3rd leadframe part upper surface are directly exposed to outside plastic packaging material, framework of the present invention exposes multi-chip to be taken stacking sandwich encapsulating structure more and has good heat dispersion; And the present invention can again according to product power, heat conduction or the difference of heat radiation additional radiator on lead frame freely, in order to increase the ability of the product dissipation of heat further;
4, a kind of framework of the present invention exposes multi-chip and takes stacking sandwich encapsulating structure more and use upper lower platen to push down general frame to carry out Reflow Soldering, framework to be not easily heated the cohesion institute jack-up of cooling procedure after melting by tin cream when Reflow Soldering, ensure the total height of frame structure, prevent movement or the rotation of chip, and can guarantee that framework exposes the coplanarity of outer pin.
Accompanying drawing explanation
Fig. 1 is a kind of known MOS stack package structure schematic diagram.
Fig. 2 is that a kind of framework that the present invention manufactures exposes the side view that multi-chip takes stacking sandwich encapsulating structure more.
Fig. 3 is that a kind of framework that the present invention manufactures exposes the vertical view that multi-chip takes stacking sandwich encapsulating structure more.
Fig. 4 is the three-dimensional view of the first lead frame in the present invention.
Fig. 5 is the three-dimensional view of the second lead frame in the present invention.
Fig. 6 is the three-dimensional view of the 3rd lead frame in the present invention.
Fig. 7 (a) to Fig. 7 (m) exposes the flow chart that multi-chip takes stacking sandwich encapsulating structure process more for a kind of framework of the present invention.
Wherein:
Lead frame 11
First chip 12
Second chip 13
First metal splint 14
Second metal splint 15
First metal bonding wire 16
Second metal bonding wire 17
First lead frame 21
Second lead frame 22
Horizontal segment 221 on first
First middle linkage section 222
First time horizontal segment 223
3rd lead frame 23
Horizontal segment 231 on second
Second middle linkage section 232
Second time horizontal segment 233
First chip 24
Second chip 25
Tin cream 26
Plastic packaging material 27.
Embodiment
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
As shown in Fig. 7 (a) ~ Fig. 7 (m), a kind of framework in the present embodiment exposes the process that multi-chip takes stacking sandwich encapsulating structure more, and its concrete technology step is as follows:
Step one, see Fig. 7 (a), provide the first lead frame, the material of the first lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C;
Step 2, see Fig. 7 (b), tin cream is applied by the mode of screen printing in the first lead frame Ji Dao region, object engages for realizing follow-up first implanted chip Hou Yuji island, can control the thickness of tin cream, area and position accurately by the adjustment thickness of web plate and the area of opening;
Step 3, see Fig. 7 (c), in step 2 first lead frame Ji Dao region coating tin cream on implant the first chip;
Step 4, see Fig. 7 (d), second lead frame is provided, described second lead frame is Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, the first middle linkage section and first time horizontal segment, the material of the second lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.On first of the second lead frame, horizontal segment lower surface and first time horizontal segment lower surface apply tin cream by the mode of screen printing, object is that the pin and the first chip front side for realizing follow-up second lead frame is formed and be electrically connected, and can control the thickness of tin cream, area and position accurately by the adjustment thickness of web plate and the area of opening;
Step 5, see Fig. 7 (e), horizontal segment on first of second lead frame is pressed together on the first chip of the first lead frame upper surface, first chip and the second lead frame are formed by the tin cream of horizontal segment lower surface on first be electrically connected, and first of the second lead frame time horizontal segment lower surface is set up on the first lead frame upper surface, after pressing, the first lead frame and the second lead frame form general frame;
Step 6, see Fig. 7 (f), by step 5 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering.The material of pressing plate requires deformation is less likely to occur and has good heat-conductive characteristic, and the thermal coefficient of expansion CTE of its thermal coefficient of expansion CTE and the first lead frame and the second lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C;
Step 7, see Fig. 7 (g), after completing Reflow Soldering, on first of the second lead frame, the upper surface of horizontal segment applies tin cream by the mode of screen printing;
Step 8, see Fig. 7 (h), in step 7 the second lead frame first on horizontal segment upper surface coating tin cream on implant the second chip;
Step 9, see Fig. 7 (i), 3rd lead frame is provided, described 3rd lead frame is Z-shaped, described the 3rd Z-shaped lead frame comprises horizontal segment on second, the second middle linkage section and second time horizontal segment, the material of the 3rd lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.On second of the 3rd lead frame, horizontal segment lower surface and second time horizontal segment lower surface apply tin cream by the mode of screen printing, object is electrically connected for realizing follow-up 3rd lead frame second is formed between horizontal segment and the second chip front side and between the 3rd lead frame second time horizontal segment and the first lead frame upper surface, can control the thickness of tin cream, area and position accurately by the adjustment thickness of web plate and the area of opening;
Step 10, see Fig. 7 (j), horizontal segment on second of 3rd lead frame is pressed together on the second lead frame first on horizontal segment upper surface the second chip on, second chip and the 3rd lead frame are formed by the tin cream of horizontal segment lower surface on second be electrically connected, and second time horizontal segment lower surface of the 3rd lead frame is set up on the first lead frame upper surface, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame;
Step 11, see Fig. 7 (k), by step 10 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering.The material of pressing plate requires deformation is less likely to occur and has good heat-conductive characteristic, the thermal coefficient of expansion CTE of its thermal coefficient of expansion CTE and the first lead frame, the second lead frame and the 3rd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C;
Step 12, see Fig. 7 (l), adopt plastic packaging material to carry out plastic packaging the general frame of step 11 after Reflow Soldering, after plastic packaging the 3rd lead frame second on the upper surface of horizontal segment be exposed to outside plastic packaging material;
Step 13, see Fig. 7 (m), semi-finished product step 12 being completed plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, and obtained framework exposes multi-chip takes stacking sandwich encapsulating structure more.
In above-mentioned steps, step 5 and step 6 first lead frame pressing second lead frame form general frame and use pressing plate to carry out Reflow Soldering, can implement after step 8 second lead frame implants the second chip.
In above-mentioned steps, step 2, step 4 and step 9 are carried out by different platform simultaneously.
See Fig. 2 ~ Fig. 6, a kind of framework of the present invention exposes multi-chip takes stacking sandwich encapsulating structure more, it comprises the first lead frame 21, second lead frame 22, 3rd lead frame 23, first chip 24 and the second chip 25, described second lead frame 22 and the 3rd lead frame 23 are in Z-shaped, described the second Z-shaped lead frame 22 comprises horizontal segment 221 on first, first middle linkage section 222 and first time horizontal segment 223, described the 3rd Z-shaped lead frame 23 comprises horizontal segment 231 on second, second middle linkage section 232 and second time horizontal segment 233, described first chip 24 to be folded on the first lead frame 21 and first between horizontal segment 221, the front and back of described first chip 24 is electrically connected respectively by horizontal segment 221 and the first lead frame 21 on tin cream 26 and first, described second chip 25 to be folded on first on horizontal segment 221 and second between horizontal segment 231, the front and back of described second chip 25 is electrically connected respectively by horizontal segment 221 on horizontal segment on tin cream 26 and second 231 and first, described first lead frame 21, second lead frame 22 and the 3rd lead frame 23 outer encapsulating have plastic packaging material 27, on described first lead frame 21 lower surface and second, horizontal segment upper surface is all exposed to outside plastic packaging material 27, described first time horizontal segment 223 lower surface and second time horizontal segment 233 lower surface are set up on the first lead frame 21 upper surface.
Described first lead frame 21, second lead frame 22 and the 3rd lead frame 23 are general frame, its material can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.
Described first chip 24 and the second chip 25 are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
In addition to the implementation, the present invention also includes other execution modes, the technical scheme that all employing equivalents or equivalent substitute mode are formed, within the protection range that all should fall into the claims in the present invention.

Claims (8)

1. a framework exposes multi-chip and takes stacking sandwich encapsulating structure more, it is characterized in that: it comprises the first lead frame (21), second lead frame (22), 3rd lead frame (23), first chip (24) and the second chip (25), described second lead frame (22) and the 3rd lead frame (23) are in Z-shaped, described Z-shaped the second lead frame (22) comprises horizontal segment on first (221), first middle linkage section (222) and first time horizontal segment (223), described the 3rd Z-shaped lead frame (23) comprises horizontal segment on second (231), second middle linkage section (232) and second time horizontal segment (233), described first chip (24) to be folded on the first lead frame (21) and first between horizontal segment (221), the front and back of described first chip (24) is electrically connected respectively by horizontal segment (221) on tin cream (26) and first and the first lead frame (21), described second chip (25) to be folded on horizontal segment on first (221) and second between horizontal segment (231), the front and back of described second chip (25) is electrically connected respectively by horizontal segment (221) on horizontal segment (231) and first on tin cream (26) and second, described first lead frame (21), second lead frame (22) and the 3rd lead frame (23) outer encapsulating have plastic packaging material (27), on described first lead frame (21) lower surface and second, horizontal segment upper surface is all exposed to outside plastic packaging material (27), described first time horizontal segment (223) lower surface and second time horizontal segment (233) lower surface are set up on the first lead frame (21) upper surface.
2. a kind of framework according to claim 1 exposes multi-chip and takes stacking sandwich encapsulating structure more, it is characterized in that: described first lead frame (21), the second lead frame (22) and the 3rd lead frame (23) are general frame.
3. framework exposes the process that multi-chip takes stacking sandwich encapsulating structure more, it is characterized in that described method comprises the steps:
Step one, provide the first lead frame;
Step 2, apply tin cream in the first lead frame Ji Dao region by the mode of screen printing;
The tin cream of step 3, the first lead frame Ji Dao region coating in step 2 implants the first chip;
Step 4, provide the second lead frame, described second lead frame is Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, the first middle linkage section and first time horizontal segment, and on first of the second lead frame, horizontal segment lower surface and first time horizontal segment lower surface apply tin cream by the mode of screen printing;
Step 5, horizontal segment on first of the second lead frame is pressed together on the first chip of the first lead frame upper surface, and first of the second lead frame time horizontal segment lower surface is set up on the first lead frame upper surface, after pressing, the first lead frame and the second lead frame form general frame;
Step 6, by step 5 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 7, complete Reflow Soldering after, on first of the second lead frame, the upper surface of horizontal segment applies tin cream by the mode of screen printing;
Step 8, in step 7 the second lead frame first on horizontal segment upper surface coating tin cream on implant the second chip;
Step 9, provide the 3rd lead frame, described 3rd lead frame is Z-shaped, described the 3rd Z-shaped lead frame comprises horizontal segment on second, the second middle linkage section and second time horizontal segment, and on second of the 3rd lead frame, horizontal segment lower surface and second time horizontal segment lower surface apply tin cream by the mode of screen printing;
Step 10, horizontal segment on second of the 3rd lead frame is pressed together on the second lead frame first on horizontal segment upper surface the second chip on, and second time horizontal segment lower surface of the 3rd lead frame is set up on the first lead frame upper surface, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame;
Step 11, by step 10 formed general frame upper and lower surface pressing plate push down, carry out Reflow Soldering;
Step 12, adopt plastic packaging material to carry out plastic packaging the general frame of step 11 after Reflow Soldering, after plastic packaging the 3rd lead frame second on the upper surface of horizontal segment be exposed to outside plastic packaging material;
Step 13, semi-finished product step 12 being completed plastic packaging carry out cutting or die-cut operation, make array plastic-sealed body originally, cutting or die-cut independent, and obtained framework exposes multi-chip takes stacking sandwich encapsulating structure more.
4. a kind of framework according to claim 3 exposes the process that multi-chip takes stacking sandwich encapsulating structure more, it is characterized in that: the material of described first lead frame, the second lead frame and the 3rd lead frame can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also 8*10^-6/ DEG C for other CTE scope ~ conductive material of 25*10^-6/ DEG C.
5. a kind of framework according to claim 3 exposes the process that multi-chip takes stacking sandwich encapsulating structure more, it is characterized in that: described first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
6. a kind of framework according to claim 3 exposes the process that multi-chip takes stacking sandwich encapsulating structure more, it is characterized in that: the thermal coefficient of expansion CTE of the thermal coefficient of expansion CTE of described pressing plate material and the first lead frame, the second lead frame and the 3rd lead frame material is close, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
7. a kind of framework according to claim 3 exposes the process that multi-chip takes stacking sandwich encapsulating structure more, it is characterized in that: described step 2, step 4 and step 9 are carried out by different platform simultaneously.
8. a kind of framework according to claim 3 exposes the process that multi-chip takes stacking sandwich encapsulating structure more, it is characterized in that: step 5 and step 6 first lead frame pressing second lead frame form general frame and use pressing plate to carry out Reflow Soldering, can implement after step 8 second lead frame implants the second chip.
CN201510995486.1A 2015-12-24 2015-12-24 Multi-chip and multi-shingle stacked sandwich package structure with exposed frames and technique of multi-chip and multi-shingle stacked sandwich package structure Pending CN105405834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510995486.1A CN105405834A (en) 2015-12-24 2015-12-24 Multi-chip and multi-shingle stacked sandwich package structure with exposed frames and technique of multi-chip and multi-shingle stacked sandwich package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510995486.1A CN105405834A (en) 2015-12-24 2015-12-24 Multi-chip and multi-shingle stacked sandwich package structure with exposed frames and technique of multi-chip and multi-shingle stacked sandwich package structure

Publications (1)

Publication Number Publication Date
CN105405834A true CN105405834A (en) 2016-03-16

Family

ID=55471229

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510995486.1A Pending CN105405834A (en) 2015-12-24 2015-12-24 Multi-chip and multi-shingle stacked sandwich package structure with exposed frames and technique of multi-chip and multi-shingle stacked sandwich package structure

Country Status (1)

Country Link
CN (1) CN105405834A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449517A (en) * 2016-11-22 2017-02-22 华蓥旗邦微电子有限公司 Stack type single base island SIP (System in Package) packaging process
CN111090058A (en) * 2019-11-22 2020-05-01 珠海格力电器股份有限公司 Frame, preparation method thereof and high-temperature reverse bias test
CN112635428A (en) * 2020-12-30 2021-04-09 杰华特微电子(杭州)有限公司 Frame structure of chip package and semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515551A (en) * 2008-02-22 2009-08-26 株式会社瑞萨科技 Manufacturing method of semiconductor device
CN101859755A (en) * 2010-05-14 2010-10-13 上海凯虹科技电子有限公司 Power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) package body and package method thereof
CN102903692A (en) * 2011-07-26 2013-01-30 万国半导体股份有限公司 Stacked power semiconductor device with double-layer lead frame and production method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515551A (en) * 2008-02-22 2009-08-26 株式会社瑞萨科技 Manufacturing method of semiconductor device
CN101859755A (en) * 2010-05-14 2010-10-13 上海凯虹科技电子有限公司 Power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) package body and package method thereof
CN102903692A (en) * 2011-07-26 2013-01-30 万国半导体股份有限公司 Stacked power semiconductor device with double-layer lead frame and production method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449517A (en) * 2016-11-22 2017-02-22 华蓥旗邦微电子有限公司 Stack type single base island SIP (System in Package) packaging process
CN106449517B (en) * 2016-11-22 2018-08-28 华蓥旗邦微电子有限公司 A kind of islands stack Dan Ji SIP packaging technologies
CN111090058A (en) * 2019-11-22 2020-05-01 珠海格力电器股份有限公司 Frame, preparation method thereof and high-temperature reverse bias test
CN112635428A (en) * 2020-12-30 2021-04-09 杰华特微电子(杭州)有限公司 Frame structure of chip package and semiconductor device
CN112635428B (en) * 2020-12-30 2024-01-23 杰华特微电子股份有限公司 Frame structure of chip package and semiconductor device

Similar Documents

Publication Publication Date Title
CN206116387U (en) Big current power semiconductor device's packaging structure
CN105405834A (en) Multi-chip and multi-shingle stacked sandwich package structure with exposed frames and technique of multi-chip and multi-shingle stacked sandwich package structure
CN105448881A (en) Framework exposed multi-core multi-lapping, tiling and core-sandwiching packaging structure and technological method thereof
CN105551982A (en) Multi-chip upright tile sandwich package structure and technique therefor
CN205582931U (en) Part frame exposes multicore piece singly takes flip -chip tiling clamp core packaging structure
CN105428343A (en) Multi-chip single-lapped stacked sandwiched packaging structure and process method thereof
CN105609424A (en) Sandwich packaging technique with exposed frame
CN105633051A (en) Multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and process method of structure
CN205582923U (en) Frame exposes multicore piece to be taken flip -chip more and piles up double -layered core packaging structure
CN205355046U (en) Frame exposes multicore piece to be taken more and loading in mixture tiling and press from both sides core packaging structure
CN205582917U (en) Frame exposes multicore piece takes flip -chip tiling clamp core packaging structure more
CN105489508A (en) Sandwich packaging technique for preventing chip from deviating
CN201435388Y (en) Lead frame used for encapsulating MOSFET
CN205355045U (en) Frame exposes multicore piece and loads in mixture and pile up double -layered core packaging structure
CN205582928U (en) Multicore piece is taken flip -chip tiling more and is pressed from both sides core packaging structure
CN105551983A (en) Multi-chip upright stack sandwich package structure with exposed frame and technique for multi-chip upright stack sandwich package structure
CN105405833A (en) Multi-chip multi-overlap flat-paved sandwich encapsulation structure and technological process thereof
CN105609425A (en) Multi-chip and single-lap flat sandwich package structure with partially exposed frames and technique for multi-chip and single-lap flat sandwich package structure
CN105405831A (en) Frame exposed multi-chip forward-assembled flat-paved sandwich encapsulation structure and technological process thereof
CN105633050A (en) Multi-chip and multi-lap stack sandwich package structure and technique therefor
CN205355032U (en) Frame exposes multicore piece singly to be taken flip -chip and piles up double -layered core packaging structure
CN205376509U (en) Multicore piece is taken flip -chip more and is piled up double -layered core packaging structure
CN205355044U (en) Frame exposes multicore piece to be taken to load in mixture more and piles up double -layered core packaging structure
CN205582929U (en) Multicore piece is singly taken flip -chip and is piled up double -layered core packaging structure
CN205376510U (en) Part frame exposes multicore piece to be taken more and loading in mixture double -layered core packaging structure of tiling

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20160316