CN105609425A - Multi-chip and single-lap flat sandwich package structure with partially exposed frames and technique for multi-chip and single-lap flat sandwich package structure - Google Patents
Multi-chip and single-lap flat sandwich package structure with partially exposed frames and technique for multi-chip and single-lap flat sandwich package structure Download PDFInfo
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- CN105609425A CN105609425A CN201510991594.1A CN201510991594A CN105609425A CN 105609425 A CN105609425 A CN 105609425A CN 201510991594 A CN201510991594 A CN 201510991594A CN 105609425 A CN105609425 A CN 105609425A
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- 238000005476 soldering Methods 0.000 claims abstract description 18
- 238000004806 packaging method and process Methods 0.000 claims abstract description 13
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- 238000000576 coating method Methods 0.000 claims abstract description 8
- 238000005520 cutting process Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 55
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 35
- 239000006071 cream Substances 0.000 claims description 32
- 239000005022 packaging material Substances 0.000 claims description 21
- 238000003825 pressing Methods 0.000 claims description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
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- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 claims description 6
- 238000013459 approach Methods 0.000 claims description 6
- TVZPLCNGKSPOJA-UHFFFAOYSA-N copper zinc Chemical compound [Cu].[Zn] TVZPLCNGKSPOJA-UHFFFAOYSA-N 0.000 claims description 6
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- 239000011265 semifinished product Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 238000010030 laminating Methods 0.000 abstract 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 150000001875 compounds Chemical class 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 abstract 1
- 238000000465 moulding Methods 0.000 abstract 1
- 238000004080 punching Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 19
- 239000002184 metal Substances 0.000 description 19
- 239000000047 product Substances 0.000 description 15
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- 239000010959 steel Substances 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/37124—Aluminium [Al] as principal constituent
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- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention relates to a multi-chip and single-lap flat sandwich package structure with partially exposed frames and a technique for the multi-chip single-lap flat sandwich package structure. The technique comprises the following steps: (1) providing a first lead frame; (2) coating the first lead frame with a solder paste; (3) embedding a first chip into the solder paste of the first lead frame; (4) providing a second lead frame and coating the second lead frame with the solder paste; (5) laminating the second lead frame on the first chip; (6) carrying out reflow soldering; (7) coating the second lead frame with the solder paste; (8) embedding a second chip into the second lead frame; (9) providing a third lead frame and coating the third lead frame with the solder paste; (10) laminating the third lead frame on the second chip; (11) carrying out reflow soldering; (12) carrying out plastic packaging by a molding compound; and (13) carrying out cutting or punching operation. The multi-chip and single-lap flat sandwich package structure has the beneficial effect that the heat dissipation ability of a product is improved; the packaging resistance of the product is reduced; and the production efficiency is high.
Description
Technical field
The present invention relates to a kind of part frame and expose multi-chip list and take tiling sandwich encapsulating structure and process thereof, belong to semiconductor packaging field.
Background technology
In recent years, along with electronic product is constantly pursued power density, no matter be Diode(diode) or Transistor(triode) encapsulation, especially Transistor in MOS product just towards more high-power, smaller szie, more fast, the better trend of dispelling the heat is in development. The also slowly disposable encapsulation technology spurt of the highly difficult low cost of the high density in even larger region and challenge towards zonule by single encapsulation technology of the disposable manufacture of encapsulation.
Therefore, also there has been more requirement the various electrical properties to the parasitic resistance of being encapsulated in of MOS product, electric capacity, inductance etc., the structure of encapsulation, the dissipation of heat sexuality of encapsulation, reliability aspect and the highly difficult disposable encapsulation technology aspect of encapsulation.
Traditional Diode(diode) and Transistor(triode) or the encapsulation of MOS product generally according to the difference of product performance, power and the Consideration of cost, utilize the bonding wire mode of gold thread, silver alloy wire, copper cash, aluminum steel and aluminium strip as the main interconnection technique of chip and interior pin, thereby realized electrical connection. But there is restriction and the defect of the following aspects in the technical approach of bonding wire to the performance of product:
One, the restriction of encapsulation and manufacture view and defect:
1), Weldability (Bondability) aspect: usually can be because of the variation of the variation of parameter sheet, performance and the precision of the variation of wire material, metal pins material and equipment and instrument and maintenance the first solder joint of causing and the second solder joint faying face with proofreading and correct management rosin joint, come off, breakpoint, neck crack, all puzzlements such as collapse line and short circuit etc., caused encapsulating that yield cannot promote, cost cannot decline, reliability unstable;
2), disposable high-density encapsulation technology aspect: traditional mutual contact mode is nearly all the welding manner that adopts one chips of single chips to repeat load, wire to adopt high temperature ultrasonic single line single line in matrix type die-attach area. And in situation be like this machinery equipments such as professional loader, ball bonding wire bonder, bonding aluminum steel/aluminium strip machine or copper sheet overlapping machine repetitive operation more at a high speed all cannot improving production efficiency, cannot reduce unit cost, also because equipment constantly promote speed of production same also promoted the unstability of manufacturing.
Two, the restriction of the special aspect of performance of encapsulating products and defect:
1), dissipation of heat aspect: traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS, all generally to be coated by plastic packaging material, only stay external pin to be exposed to outside plastic-sealed body, because plastic packaging material itself is not a kind of material of thermal conductance, so traditional Diode(diode) and Transistor(triode) or the heat that produces in when work of MOS product is difficult to by plastic packaging material dissipate the packaging body of plastic packaging material material, can only rely on fine wire to be interconnected at metal pins material to help the dissipation of heat energy, but the approach of this dissipation of heat is very limited to hot dissipation capability, form on the contrary the resistance of the dissipation of heat,
2), resistivity (Resistivity) aspect: resistivity (resistivity) is the physical quantity for representing various material resistance characteristics as you know. In the situation that temperature is certain, having formula R=ρ l/s ρ is wherein exactly resistivity, the length that l is material, and s is area. Can find out, the resistance sizes of material is proportional to the length of material, and is inversely proportional to its area. Definition by the known resistivity of above formula: ρ=Rs/l. Traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS, adopt bonding wire to form interconnected, can clearly know thus for carry out power supply or the wire of signal can because, the length of conductor material and the variation of sectional area and have influence on the size of resistivity and the loss of contact resistance, the product impact that is especially applied in power aspect is obvious especially.
For addressing the above problem, industry is to traditional Diode(diode) and Transistor(triode) or the encapsulating products of MOS improves, replace bonding wire with metal tape, metal splint, reduce packaged resistance, inductance and expectation and improve the ability of the dissipation of heat.
As shown in Figure 1, be the existing MOS encapsulating structure of one, in this structure, lead frame 11 comprises pipe core welding disc and pin, implants the first chip 12, the second chip 13 on the pipe core welding disc of lead frame 11. The source electrode of the first chip 12 is electrically coupled to lead frame 11, the first chips 12 grid by the first metal splint 14 is electrically coupled to lead frame 11 by the first metal bonding wire 16. The source electrode of the second chip 13 is electrically coupled to lead frame 11, the second chips 13 grid by the second metal splint 15 is electrically coupled to lead frame 11 by the second metal bonding wire 17. Seal again, cut, the subsequent handling such as test. This MOS encapsulating structure has replaced the bonding wire in conventional MOS encapsulation with metal splint, reduce part packaged resistance, but still there is following defect: first, drain electrode, source electrode and the grid of this MOS encapsulating structure chips forms the interconnected different equipment of will using respectively from lead frame, processing procedure complexity, the acquisition cost of equipment is higher; Secondly, this MOS encapsulating structure, in the time that metal splint and metal bonding wire are coupled on chip and pin, can only carry out by a chips, and cannot whole piece one-body molded, manufacture efficiency be lower.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of part frame to expose multi-chip list for above-mentioned prior art to take tiling sandwich encapsulating structure and process thereof, whole piece product can be one-body molded, production efficiency is high, technique is simple, can reduce costs, and there is good thermal diffusivity and lower packaged resistance and inductance.
The present invention addresses the above problem adopted technical scheme: a kind of part frame exposes multi-chip list takes tiling sandwich encapsulating structure, it comprises the first lead frame, the second lead frame, the 3rd lead frame, the first chip and the second chip, described the second lead frame and the 3rd lead frame are Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, linkage section and first time horizontal segment in the middle of first, described the 3rd Z-shaped lead frame comprises horizontal segment on second, linkage section and second time horizontal segment in the middle of second, described the first chip gripper is located on the first lead frame and first between horizontal segment, the front and back of described the first chip is electrically connected by horizontal segment on tin cream and first and the first lead frame respectively, described the second chip gripper is located on first time horizontal segment and second between horizontal segment, the front and back of described the second chip is respectively by horizontal segment on tin cream and second and first time horizontal segment and electric connection, described the first lead frame, the second lead frame and the 3rd lead frame outer encapsulating have plastic packaging material, described the first lead frame lower surface and first time horizontal segment lower surface flush and are exposed to outside plastic packaging material, on described first, on horizontal segment upper surface and second, horizontal segment upper surface does not flush, on described first, on horizontal segment upper surface or second, horizontal segment upper surface is exposed to outside plastic packaging material, described second time horizontal segment lower surface set up on the first lead frame upper surface.
Described the first lead frame, the second lead frame and the 3rd lead frame are general frame.
The process that part frame exposes multi-chip list takes tiling sandwich encapsulating structure, described method comprises the steps:
Step 1, provide the first lead frame;
Step 2, apply tin cream in the first lead frame Ji Dao region by the mode of screen printing;
On the tin cream of step 3, the first lead frame Ji Dao region coating in step 2, implant the first chip;
Step 4, provide the second lead frame, described the second lead frame is Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, linkage section and first time horizontal segment in the middle of first, the second lead frame first on the lower surface of horizontal segment apply tin cream by the mode of screen printing;
Step 5, by the second lead frame first on horizontal segment be pressed together on the first chip of the first lead frame upper surface, after pressing, the first lead frame and the second lead frame form general frame, and first time horizontal segment lower surface of the first lead frame lower surface and the second lead frame flushes;
Step 6, the general frame upper and lower surface that step 5 is formed are pushed down with pressing plate, carry out Reflow Soldering;
Step 7, complete after Reflow Soldering, apply tin cream at the upper surface of first time horizontal segment of the second lead frame by the mode of screen printing;
On the tin cream of step 8, first time horizontal segment upper surface coating of the second lead frame in step 7, implant the second chip;
Step 9, provide the 3rd lead frame, described the 3rd lead frame is Z-shaped, described the 3rd Z-shaped lead frame comprises horizontal segment on second, linkage section and second time horizontal segment in the middle of second, the 3rd lead frame second on horizontal segment lower surface and second time horizontal segment lower surface apply tin cream by the mode of screen printing;
Step 10, by the 3rd lead frame second on horizontal segment be pressed together on second chip of first time horizontal segment upper surface of the second lead frame, and second time horizontal segment lower surface of the 3rd lead frame set up on the first lead frame upper surface, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame;
Step 11, the general frame upper and lower surface that step 10 is formed are pushed down with pressing plate, carry out Reflow Soldering;
Step 12, general frame by step 11 after Reflow Soldering adopt plastic packaging material to carry out plastic packaging, and after plastic packaging, horizontal segment upper surface is exposed to outside plastic packaging material on second of horizontal segment upper surface or the 3rd lead frame on first of the second lead frame;
Step 13, the semi-finished product that step 12 is completed to plastic packaging cut or die-cut operation, make array plastic-sealed body originally, and cutting or die-cut independent makes part frame and exposes multi-chip list and take tiling sandwich encapsulating structure.
Described first lead frame pressing the second lead frame forms general frame, can after the second lead frame is implanted the second chip, implement.
The material of described the first lead frame, the second lead frame and the 3rd lead frame can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope.
Described the first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
The thermal coefficient of expansion CTE of the thermal coefficient of expansion CTE of described pressing plate material and the first lead frame, the second lead frame and the 3rd lead frame material approaches, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
Described step 2, step 4 and step 9 can be carried out by different platform simultaneously.
Compared with prior art, the invention has the advantages that:
1, a kind of part frame of the present invention expose the second lead frame that multi-chip list takes tiling sandwich encapsulating structure and the 3rd lead frame directly with source electrode and the grid formation electric connection of MOS chip, having replaced in conventional MOS chip package utilizes metal welding line to form interconnected technique, fully reduced packaged resistance, technology of the present invention can reduce more than at least 30% than the packaged resistance of conventional package design;
2, a kind of part frame of the present invention expose the second lead frame that multi-chip list takes tiling sandwich encapsulating structure with the 3rd lead frame directly by source electrode and the grid formation electric connection of tin cream and MOS chip, reduce or remit the interconnected operation of metal bonding wire completely, saved the cost such as equipment purchasing, operation material of the interconnected operation of metal bonding wire completely. And the second lead frame of the present invention and the 3rd lead frame are all that whole piece is integrated, forming electric connection with chip is also that whole piece one step completes, compared with forming interconnected technique with conventional metals bonding wire, the interconnected chip one by one of sheet metal, technique is comparatively simple, and production efficiency is significantly improved;
3, a kind of part frame of the present invention exposes multi-chip list and takes tiling sandwich encapsulating structure because upper and lower two surfaces of chip all directly contact with lead frame, the heat producing when chip operation can shed by lead frame, and the first lead frame lower surface of the present invention is directly exposed to outside plastic packaging material, part frame of the present invention exposes multi-chip list to be taken tiling sandwich encapsulating structure and has good heat dispersion; And the present invention can be again according to the difference additional radiator on lead frame freely of product power, heat conduction or heat radiation, in order to the ability of the further increase product dissipation of heat;
4, a kind of part frame of the present invention exposes multi-chip list and takes tiling sandwich encapsulating structure and use upper lower platen to push down general frame to carry out Reflow Soldering, make framework in the time of Reflow Soldering, be difficult for the cohesion institute jack-up of cooling procedure of being heated after melting by tin cream, ensure the total height of frame structure, prevent movement or the rotation of chip, and can guarantee that framework exposes the coplanarity of outer pin.
Brief description of the drawings
Fig. 1 is a kind of known MOS encapsulating structure schematic diagram.
Fig. 2 is the side view that a kind of part frame that the present invention manufactures exposes multi-chip list and take tiling sandwich encapsulating structure.
Fig. 3 is the top view that a kind of part frame that the present invention manufactures exposes multi-chip list and take tiling sandwich encapsulating structure.
Fig. 4 is the three-dimensional view of the first lead frame in the present invention.
Fig. 5 is the three-dimensional view of the second lead frame in the present invention.
Fig. 6 is the three-dimensional view of the 3rd lead frame in the present invention.
Fig. 7 (a) takes the flow chart of tiling sandwich encapsulating structure process for a kind of part frame of the present invention exposes multi-chip list to Fig. 7 (m).
Fig. 8 is the side view that a kind of part frame that the present invention manufactures exposes multi-chip list and take another embodiment of tiling sandwich encapsulating structure.
Wherein:
Lead frame 11
The first chip 12
The second chip 13
The first metal splint 14
The second metal splint 15
The first metal bonding wire 16
The second metal bonding wire 17
The first lead frame 21
The second lead frame 22
Horizontal segment 221 on first
Linkage section 222 in the middle of first
First time horizontal segment 223
The 3rd lead frame 23
Horizontal segment 231 on second
Linkage section 232 in the middle of second
Second time horizontal segment 233
The first chip 24
The second chip 25
Tin cream 26
Plastic packaging material 27.
Detailed description of the invention
Below in conjunction with accompanying drawing, embodiment is described in further detail the present invention.
As shown in Fig. 7 (a) ~ Fig. 7 (m), the process that a kind of part frame in the present embodiment exposes multi-chip list takes tiling sandwich encapsulating structure, its concrete technology step is as follows:
Step 1, referring to Fig. 7 (a), the first lead frame is provided, the material of the first lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope;
Step 2, referring to Fig. 7 (b), apply tin cream in the first lead frame Ji Dao region by the mode of screen printing, object is to engage for realizing follow-up the first implanted chip Hou Yuji island, can control accurately thickness, area and the position of tin cream by adjusting the thickness of web plate and the area of opening;
Step 3, referring to Fig. 7 (c), in step 2 first lead frame Ji Dao region apply tin cream on implant the first chip;
Step 4, referring to Fig. 7 (d), the second lead frame is provided, described the second lead frame is Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, the first middle linkage section and first time horizontal segment, the material of the second lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope. The second lead frame first on the lower surface of horizontal segment apply tin cream by the mode of screen printing, object is that pin and the first chip front side for realizing follow-up the second lead frame forms electric connection, can control accurately thickness, area and the position of tin cream by adjusting the thickness of web plate and the area of opening;
Step 5, referring to Fig. 7 (e), by the second lead frame first on horizontal segment be pressed together on the first chip of the first lead frame upper surface, the tin cream that makes the first chip and the second lead frame pass through horizontal segment lower surface on first forms and is electrically connected, after pressing, the first lead frame and the second lead frame form general frame, and first time horizontal segment lower surface of the first lead frame lower surface and the second lead frame flushes;
Step 6, referring to Fig. 7 (f), by step 5 form general frame upper and lower surface push down with pressing plate, carry out Reflow Soldering. The material of pressing plate requires to be not easy that deformation occurs and to have good heat-conductive characteristic, and the thermal coefficient of expansion CTE of its thermal coefficient of expansion CTE and the first lead frame and the second lead frame material approaches, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C;
Step 7, referring to Fig. 7 (g), complete after Reflow Soldering, apply tin cream at the upper surface of first time horizontal segment of the second lead frame by the mode of screen printing;
Step 8, referring to Fig. 7 (h), on the tin cream that first of the second lead frame time horizontal segment upper surface applies in step 7, implant the second chip;
Step 9, referring to Fig. 7 (i), the 3rd lead frame is provided, described the 3rd lead frame is Z-shaped, described the 3rd Z-shaped lead frame comprises horizontal segment on second, the second middle linkage section and second time horizontal segment, the material of the 3rd lead frame is alloy copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope. The 3rd lead frame second on horizontal segment lower surface and second time horizontal segment lower surface apply tin cream by the mode of screen printing, object is to form and be electrically connected between horizontal segment and the second chip front side and between second time horizontal segment of the 3rd lead frame and the first lead frame upper surface for realizing on follow-up the 3rd lead frame second, can control accurately thickness, area and the position of tin cream by adjusting the thickness of web plate and the area of opening;
Step 10, referring to Fig. 7 (j), by the 3rd lead frame second on horizontal segment be pressed together on second chip of first time horizontal segment upper surface of the second lead frame, the tin cream that makes the second chip and the 3rd lead frame pass through horizontal segment lower surface on second forms and is electrically connected, and second time horizontal segment lower surface of the 3rd lead frame set up on the first lead frame upper surface, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame;
Step 11, referring to Fig. 7 (k), by step 10 form general frame upper and lower surface push down with pressing plate, carry out Reflow Soldering. The material of pressing plate requires to be not easy deformation to occur and have good heat-conductive characteristic, the thermal coefficient of expansion CTE of its thermal coefficient of expansion CTE and the first lead frame, the second lead frame and the 3rd lead frame material approaches, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C;
Step 12, referring to Fig. 7 (l), general frame by step 11 after Reflow Soldering adopts plastic packaging material to carry out plastic packaging, and after plastic packaging, horizontal segment upper surface is exposed to outside plastic packaging material on second of horizontal segment upper surface or the 3rd lead frame on first of the second lead frame;
Step 13, referring to Fig. 7 (m), the semi-finished product that step 12 completed to plastic packaging cut or die-cut operation, make originally array plastic-sealed body, cutting or die-cut independent makes part frame and exposes multi-chip list and take tiling sandwich encapsulating structure.
In above-mentioned steps, step 5 and step 6 first lead frame pressing the second lead frame form general frame and use pressing plate to carry out Reflow Soldering, can after step 8 the second lead frame is implanted the second chip, implement.
In above-mentioned steps, step 2, step 4 and step 9 can be carried out by different platform simultaneously.
Referring to Fig. 2 ~ Fig. 6, Fig. 8, a kind of part frame of the present invention exposes multi-chip list takes tiling sandwich encapsulating structure, it comprises the first lead frame 21, the second lead frame 22, the 3rd lead frame 23, the first chip 24 and the second chip 25, described the second lead frame 22 and the 3rd lead frame 23 are Z-shaped, described the second Z-shaped lead frame 22 comprises horizontal segment 221 on first, linkage section 222 and first time horizontal segment 223 in the middle of first, described the 3rd Z-shaped lead frame 23 comprises horizontal segment 231 on second, linkage section 232 and second time horizontal segment 233 in the middle of second, described the first chip 24 is folded on the first lead frame 21 and first between horizontal segment 221, the front and back of described the first chip 24 is electrically connected by horizontal segment 221 on tin cream 26 and first and the first lead frame 21 respectively, described the second chip 25 is folded on first time horizontal segment 223 and second between horizontal segment 231, the front and back of described the second chip 25 is respectively by horizontal segment 231 on tin cream 26 and second and first time horizontal segment 223 and electric connection, described the first lead frame 21, the second lead frame 22 and the 3rd lead frame 23 outer encapsulatings have plastic packaging material 27, described the first lead frame 21 lower surfaces and first time horizontal segment 223 lower surface flush and are exposed to outside plastic packaging material 27, on described first, on horizontal segment 221 upper surfaces and second, horizontal segment 231 upper surfaces do not flush, on described first, on horizontal segment 221 upper surfaces or second, horizontal segment 231 upper surfaces are exposed to outside plastic packaging material 27, described second time horizontal segment 233 lower surface are set up on the first lead frame 21 upper surfaces.
Described the first lead frame 21, the second lead frame 22 and the 3rd lead frame 23 are general frame, its material can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope.
Described the first chip 24 and the second chip 25 are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
In addition to the implementation, the present invention also includes other embodiments, and the technical scheme that all employing equivalents or equivalent substitute mode form, within all should falling into the protection domain of the claims in the present invention.
Claims (8)
1. a part frame exposes multi-chip list and takes tiling sandwich encapsulating structure, it is characterized in that: it comprises the first lead frame (21), the second lead frame (22), the 3rd lead frame (23), the first chip (24) and the second chip (25), described the second lead frame (22) and the 3rd lead frame (23) are Z-shaped, described Z-shaped the second lead frame (22) comprises horizontal segment on first (221), linkage section (222) and first time horizontal segment (223) in the middle of first, described the 3rd Z-shaped lead frame (23) comprises horizontal segment on second (231), linkage section (232) and second time horizontal segment (233) in the middle of second, described the first chip (24) is folded on the first lead frame (21) and first between horizontal segment (221), the front and back of described the first chip (24) is electrically connected by horizontal segment (221) on tin cream (26) and first and the first lead frame (21) respectively, described the second chip (25) is folded on first time horizontal segment (223) and second between horizontal segment (231), the front and back of described the second chip (25) is respectively by horizontal segment (231) on tin cream (26) and second and first time horizontal segment (223) and electric connection, described the first lead frame (21), the second lead frame (22) and the 3rd lead frame (23) outer encapsulating have plastic packaging material (27), described the first lead frame (21) lower surface and first time horizontal segment (223) lower surface flush and are exposed to outside plastic packaging material (27), on (221) upper surface of horizontal segment on described first and second, horizontal segment (231) upper surface does not flush, on (221) upper surface of horizontal segment on described first or second, horizontal segment (231) upper surface is exposed to outside plastic packaging material (27), described second time horizontal segment (233) lower surface is set up on the first lead frame (21) upper surface.
2. a kind of part frame according to claim 1 exposes multi-chip list and takes tiling sandwich encapsulating structure, it is characterized in that: described the first lead frame (21), the second lead frame (22) and the 3rd lead frame (23) are general frame.
3. the process that part frame exposes multi-chip list and takes tiling sandwich encapsulating structure, is characterized in that described method comprises the steps:
Step 1, provide the first lead frame;
Step 2, apply tin cream in the first lead frame Ji Dao region by the mode of screen printing;
On the tin cream of step 3, the first lead frame Ji Dao region coating in step 2, implant the first chip;
Step 4, provide the second lead frame, described the second lead frame is Z-shaped, described the second Z-shaped lead frame comprises horizontal segment on first, linkage section and first time horizontal segment in the middle of first, the second lead frame first on the lower surface of horizontal segment apply tin cream by the mode of screen printing;
Step 5, by the second lead frame first on horizontal segment be pressed together on the first chip of the first lead frame upper surface, after pressing, the first lead frame and the second lead frame form general frame, and first time horizontal segment lower surface of the first lead frame lower surface and the second lead frame flushes;
Step 6, the general frame upper and lower surface that step 5 is formed are pushed down with pressing plate, carry out Reflow Soldering;
Step 7, complete after Reflow Soldering, apply tin cream at the upper surface of first time horizontal segment of the second lead frame by the mode of screen printing;
On the tin cream of step 8, first time horizontal segment upper surface coating of the second lead frame in step 7, implant the second chip;
Step 9, provide the 3rd lead frame, described the 3rd lead frame is Z-shaped, described the 3rd Z-shaped lead frame comprises horizontal segment on second, linkage section and second time horizontal segment in the middle of second, the 3rd lead frame second on horizontal segment lower surface and second time horizontal segment lower surface apply tin cream by the mode of screen printing;
Step 10, by the 3rd lead frame second on horizontal segment be pressed together on second chip of first time horizontal segment upper surface of the second lead frame, and second time horizontal segment lower surface of the 3rd lead frame set up on the first lead frame upper surface, after pressing, the first lead frame, the second lead frame and the 3rd lead frame form general frame;
Step 11, the general frame upper and lower surface that step 10 is formed are pushed down with pressing plate, carry out Reflow Soldering;
Step 12, general frame by step 11 after Reflow Soldering adopt plastic packaging material to carry out plastic packaging, and after plastic packaging, horizontal segment upper surface is all exposed to outside plastic packaging material on second of the first horizontal segment upper surface of the second lead frame or the 3rd lead frame;
Step 13, the semi-finished product that step 12 is completed to plastic packaging cut or die-cut operation, make array plastic-sealed body originally, and cutting or die-cut independent makes part frame and exposes multi-chip list and take tiling sandwich encapsulating structure.
4. the process that a kind of part frame according to claim 3 exposes multi-chip list and takes tiling sandwich encapsulating structure, it is characterized in that: the material of described the first lead frame, the second lead frame and the 3rd lead frame can be alloyed copper material, fine copper material, aluminium copper facing material, zinc copper facing material, dilval material, can be also the conductive material of 8*10^-6/ DEG C ~ 25*10^-6/ DEG C for other CTE scope.
5. the process that a kind of part frame according to claim 3 exposes multi-chip list and takes tiling sandwich encapsulating structure, is characterized in that: described the first chip and the second chip are two pole piece sheets, three pole piece sheets or the multipole chip that can be combined with metallic tin.
6. the process that a kind of part frame according to claim 3 exposes multi-chip list and takes tiling sandwich encapsulating structure, it is characterized in that: the thermal coefficient of expansion CTE of the thermal coefficient of expansion CTE of described pressing plate material and the first lead frame, the second lead frame and the 3rd lead frame material approaches, and its CTE scope is 8*10^-6/ DEG C ~ 25*10^-6/ DEG C.
7. the process that a kind of part frame according to claim 3 exposes multi-chip list and takes tiling sandwich encapsulating structure, is characterized in that: described step 2, step 4 and step 9 can be carried out by different platform simultaneously.
8. the process that a kind of part frame according to claim 3 exposes multi-chip list and takes tiling sandwich encapsulating structure, it is characterized in that: step 5 and step 6 first lead frame pressing the second lead frame form general frame and use pressing plate to carry out Reflow Soldering, can after step 8 the second lead frame is implanted the second chip, implement.
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