CN206532771U - Cooling type semiconductor device - Google Patents
Cooling type semiconductor device Download PDFInfo
- Publication number
- CN206532771U CN206532771U CN201720164410.9U CN201720164410U CN206532771U CN 206532771 U CN206532771 U CN 206532771U CN 201720164410 U CN201720164410 U CN 201720164410U CN 206532771 U CN206532771 U CN 206532771U
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- Prior art keywords
- pin
- chip
- side pin
- metal pad
- round recessed
- Prior art date
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- Expired - Fee Related
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000001816 cooling Methods 0.000 title claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 60
- 229910052751 metal Inorganic materials 0.000 claims abstract description 60
- 239000006071 cream Substances 0.000 claims abstract description 20
- 238000003860 storage Methods 0.000 claims abstract description 17
- 238000005253 cladding Methods 0.000 claims abstract description 14
- 239000003822 epoxy resin Substances 0.000 claims abstract description 14
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 14
- 241000218202 Coptis Species 0.000 claims description 21
- 235000002991 Coptis groenlandica Nutrition 0.000 claims description 21
- 238000005476 soldering Methods 0.000 claims description 19
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000010426 asphalt Substances 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 239000003292 glue Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000012545 processing Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005485 electric heating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
- H01L2224/48248—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a kind of cooling type semiconductor device, its epoxy resin cladding be coated on chip, metal pad, several left side pins, several right side pins on, the metal pad, left side pin and the respective lower surface of right side pin expose the bottom of epoxy resin cladding；The left side area of the chip upper surface and right side region have several left round recesseds, several right round recesseds, each bottom is respectively provided with pin area for the left round recessed and right round recessed, and the respective medial extremity upper surface of left side pin and right side pin has the first round recessed and the second round recessed；Metal pad upper surface is provided with the annular storage cream groove of a closure along edge, and the cross sectional shape of this annular storage cream groove is inverted trapezoidal, and this annular storage cream groove is located at immediately below chip and close to the fringe region of chip.The utility model effectively prevent thermal conductive insulation glue it is excessive caused by short trouble, improve finished product rate so that processing it is more simple and convenient, improve the stability and reliability of integrated chip.
Description
Technical field
The utility model is related to a kind of chip-packaging structure, is related to technical field of semiconductors.
Background technology
In recent decades, chip encapsulation technology is always with the development of integrated circuit technique.Encapsulating structure refers to
The shell of semiconductor integrated circuit chip, it not only plays installation, fixation, sealing, protection chip and enhancing electric heating property etc.
The effect of aspect, but also be wired to by the contact on chip on the pin of package casing, these pins further through
Wire on printed circuit board (PCB) is connected with other devices.Therefore, encapsulating structure generally comprise for installing, fixed and lead
Lead frame, while also including the packaging body for being used to protect chip, seal and with lead frame match.
The encapsulating structure of traditional SOP classes uses total incapsulation design, without exposed radiator structure, mainly passes through modeling
Envelope material radiating, and the poor heat dispersion for causing such a encapsulation of the heat conductivility of plastic packaging material is poor.Power it is increasing, encapsulation
Under the less and less demand of size, the radiating shortcoming of traditional SOP structures is more and more obvious.In addition, some chip products need
Two mutually isolated chips are encapsulated in an encapsulating structure.
The content of the invention
The utility model purpose is to provide a kind of cooling type semiconductor device, and the cooling type semiconductor device is conducive to drawing
Pin and metal pad are more firmly fixed, effectively prevent thermal conductive insulation glue it is excessive caused by short trouble, improve production
Product yield rate so that processing is more simple and convenient, improves the stability and reliability of integrated chip.
To reach above-mentioned purpose, the technical solution adopted in the utility model is：A kind of cooling type semiconductor device, including core
Piece, metal pad, several left side pins, several right side pins and epoxy resin cladding, the chip pass through insulating cement
Layer is fixed on the middle section of metal pad upper surface, is arranged at a left side for chip several left side pin spacing side by side
Side, is arranged at the right side of chip several right side pin spacing side by side, and the metal pad its lower edge is provided with
One gap slot, the left side pin and the opposite medial extremity bottom of metal pad are provided with the second gap slot, the right side pin with
The opposite medial extremity bottom of metal pad is provided with the 3rd gap slot, the epoxy resin cladding be coated on chip, metal pad,
On several left side pins, several right side pins, the metal pad, left side pin and the respective lower surface of right side pin are naked
Expose the bottom of epoxy resin cladding；
The left side area of the chip upper surface and right side region have several left round recesseds, several right round recesseds,
Each bottom is respectively provided with pin area, the respective medial extremity of the left side pin and right side pin for the left round recessed and right round recessed
Upper surface has the first round recessed and the second round recessed, and some first gold thread one end are located in left round recessed and by weldering
Cream is electrically connected with pin area, and this first gold thread other end is located in the first round recessed of left side pin and electrically connected by soldering paste,
Some second gold thread one end are located in right round recessed and electrically connected by soldering paste with pin area, and this second gold thread other end is located at
Electrically connected in second round recessed of right side pin and by soldering paste；
The metal pad upper surface is provided with the annular storage cream groove of a closure, the cross sectional shape of this annular storage cream groove along edge
For inverted trapezoidal, this annular storage cream groove is located at immediately below chip and close to the fringe region of chip.
Further improved scheme is as follows in above-mentioned technical proposal：
1. in such scheme, the left side pin, the metal-coated coating of lower surface of right side pin.
2. in such scheme, the coat of metal is tin layers or NiPdAu layer.
3. in such scheme, the left round recessed and right round recessed are semi-circular recesses.
4. in such scheme, the thickness ratio of the coat of metal and left side pin or right side pin is 1：6~12.
5. in such scheme, the number of the left side pin and right side pin is 3 ~ 10.
Because above-mentioned technical proposal is used, the utility model has following advantages compared with prior art：
1. the utility model cooling type semiconductor device, its metal pad its lower edge is provided with the first gap slot, described
Left side pin and the opposite medial extremity bottom of metal pad are provided with the second gap slot, and the right side pin and metal pad are opposite
Medial extremity bottom is provided with the 3rd gap slot, is conducive to pin and metal pad being more firmly fixed, improves between PCB
The reliability of welding；Secondly, its chip is fixed on the middle section of metal pad upper surface by the glue-line that insulate, metal pad,
Left side pin and the respective lower surface of right side pin expose the bottom of epoxy resin cladding, exposed metal pad, so as to
Chip operationally quickly conducts heat, good heat dissipation effect.
2. the utility model cooling type semiconductor device, if the left side area of its chip upper surface and right side region have
Dry left round recessed, several right round recesseds, each bottom is respectively provided with pin area, the left side for the left round recessed and right round recessed
Side pin and the respective medial extremity upper surface of right side pin have the first round recessed and the second round recessed, some first gold medals
Line one end is located in left round recessed and electrically connected by soldering paste with pin area, this first gold thread other end positioned at left side pin the
Electrically connected in one round recessed and by soldering paste, some second gold thread one end are located in right round recessed and pass through soldering paste and pin area
Electrical connection, this second gold thread other end is located in the second round recessed of right side pin and electrically connected by soldering paste, effectively prevent,
The problem of missing solder and rosin joint, the carrying electric current of device was both improved, and also improved the stability and reliability of integrated chip.
3. the utility model cooling type semiconductor device, its metal pad upper surface is provided with the annular of a closure along edge
Cream groove is stored up, the cross sectional shape of this annular storage cream groove is inverted trapezoidal, this annular storage cream groove is located at immediately below chip and close to chip
Fringe region, effectively prevent thermal conductive insulation glue it is excessive caused by short trouble, improve finished product rate so that processing life
Production is more simple and convenient, improves the stability and reliability of integrated chip；Secondly, its left side pin, following table of right side pin
The metal-coated coating in face, had both reduced device and PCB conductive contact resistance, and had been also beneficial to the weld strength between PCB
Raising.
Brief description of the drawings
Accompanying drawing 1 is the utility model cooling type semiconductor device architecture schematic diagram；
Accompanying drawing 2 is the partial structural diagram of accompanying drawing 1.
In the figures above：1st, chip；2nd, metal pad；3rd, left side pin；4th, right side pin；5th, epoxy resin cladding；
6th, insulate glue-line；7th, the first gap slot；8th, the second gap slot；9th, the 3rd gap slot；10th, left round recessed；11st, right round recessed；12、
Pin area；13rd, the first round recessed；14th, the second round recessed；15th, the first gold thread；16th, the second gold thread；17th, the coat of metal；18th, ring
Shape stores up cream groove.
Embodiment
Below in conjunction with the accompanying drawings and embodiment is further described to the utility model：
Embodiment 1：A kind of cooling type semiconductor device, including chip 1, metal pad 2, several left side pins 3, some
Individual right side pin 4 and epoxy resin cladding 5, the chip 1 are fixed in the upper surface of metal pad 2 by the glue-line 6 that insulate
Region is entreated, the left side of chip 1 is arranged at, several described right side pins 4 are side by side several spacing side by side of left side pin 3
It is positioned apart from the right side of chip 1, its lower edge of metal pad 2 is provided with the first gap slot 7, the left side pin 3
The medial extremity bottom opposite with metal pad 2 is provided with the second gap slot 8, the right side pin 4 and the opposite inner side of metal pad 2
End bottom is provided with the 3rd gap slot 9, and the epoxy resin cladding 5 is coated on chip 1, metal pad 2, several left side pins
3rd, on several right side pins 4, the metal pad 2, left side pin 3 and the respective lower surface of right side pin 4 expose epoxy
The bottom of resin-coating body 5；
It is recessed that the left side area and right side region of the upper surface of chip 1 have several left round recesseds 10, several right circles
Groove 11, the respective bottom of the left round recessed 10 and right round recessed 11 is respectively provided with pin area 12, the left side pin 3 and right side pin
4 respective medial extremity upper surfaces have the first round recessed 13 and the second round recessed 14, some one end of first gold thread 15 position
Electrically connected by soldering paste in the left round recessed 10 and with pin area 12, this other end of the first gold thread 15 positioned at left side pin 3 the
Electrically connected in one round recessed 13 and by soldering paste, some one end of second gold thread 16 be located in right round recessed 11 and by soldering paste with
Pin area is electrically connected, and this second gold thread other end is located in the second round recessed of right side pin and electrically connected by soldering paste；
The upper surface of metal pad 2 is provided with the annular storage cream groove 18 of a closure, section of this annular storage cream groove 18 along edge
Face is shaped as inverted trapezoidal, and this annular storage cream groove 18 is located at immediately below chip 1 and close to the fringe region of chip 1.
The metal-coated coating 17 of lower surface of above-mentioned left side pin 3, right side pin 4；The above-mentioned coat of metal 17 is tin layers
Or NiPdAu layer.
The thickness ratio of the above-mentioned coat of metal 17 and left side pin 3 or right side pin 4 is 1：8；Above-mentioned left side pin 3 and the right side
The number of side pin 4 is 8.
Embodiment 2：A kind of cooling type semiconductor device, including chip 1, metal pad 2, several left side pins 3, some
Individual right side pin 4 and epoxy resin cladding 5, the chip 1 are fixed in the upper surface of metal pad 2 by the glue-line 6 that insulate
Region is entreated, the left side of chip 1 is arranged at, several described right side pins 4 are side by side several spacing side by side of left side pin 3
It is positioned apart from the right side of chip 1, its lower edge of metal pad 2 is provided with the first gap slot 7, the left side pin 3
The medial extremity bottom opposite with metal pad 2 is provided with the second gap slot 8, the right side pin 4 and the opposite inner side of metal pad 2
End bottom is provided with the 3rd gap slot 9, and the epoxy resin cladding 5 is coated on chip 1, metal pad 2, several left side pins
3rd, on several right side pins 4, the metal pad 2, left side pin 3 and the respective lower surface of right side pin 4 expose epoxy
The bottom of resin-coating body 5；
It is recessed that the left side area and right side region of the upper surface of chip 1 have several left round recesseds 10, several right circles
Groove 11, the respective bottom of the left round recessed 10 and right round recessed 11 is respectively provided with pin area 12, the left side pin 3 and right side pin
4 respective medial extremity upper surfaces have the first round recessed 13 and the second round recessed 14, some one end of first gold thread 15 position
Electrically connected by soldering paste in the left round recessed 10 and with pin area 12, this other end of the first gold thread 15 positioned at left side pin 3 the
Electrically connected in one round recessed 13 and by soldering paste, some one end of second gold thread 16 be located in right round recessed 11 and by soldering paste with
Pin area is electrically connected, and this second gold thread other end is located in the second round recessed of right side pin and electrically connected by soldering paste；
The upper surface of metal pad 2 is provided with the annular storage cream groove 18 of a closure, section of this annular storage cream groove 18 along edge
Face is shaped as inverted trapezoidal, and this annular storage cream groove 18 is located at immediately below chip 1 and close to the fringe region of chip 1.
The metal-coated coating 17 of lower surface of above-mentioned left side pin 3, right side pin 4；Above-mentioned left round recessed 10 and right circle
Groove 11 is semi-circular recesses.
The thickness ratio of the above-mentioned coat of metal 17 and left side pin 3 or right side pin 4 is 1：10；The above-mentioned He of left side pin 3
The number of right side pin 4 is 4.
During using above-mentioned cooling type semiconductor device, it is conducive to pin and metal pad being more firmly fixed, and carries
The high reliability welded between PCB；Secondly, its exposed metal pad, so that chip operationally quickly conducts heat,
Good heat dissipation effect；Effectively prevent again, missing solder and the problem of rosin joint, both improved the carrying electric current of device, also improved integrated
The stability and reliability of chip.
Above-described embodiment is only to illustrate technical concepts and features of the present utility model, and its object is to allow be familiar with technique
Personage can understand content of the present utility model and implement according to this, protection domain of the present utility model can not be limited with this.
All equivalent change or modifications made according to the utility model Spirit Essence, should all cover protection domain of the present utility model it
It is interior.
Claims (6)
1. a kind of cooling type semiconductor device, it is characterised in that：Including chip（1）, metal pad（2）, several left side pins
（3）, several right side pins（4）With epoxy resin cladding（5）, the chip（1）Pass through the glue-line that insulate（6）It is fixed on metal
Pad（2）The middle section of upper surface, several described left side pins（3）It is arranged at chip spacing side by side（1）Left side, if
The dry right side pin（4）It is arranged at chip spacing side by side（1）Right side, the metal pad（2）Its lower edge is opened
There is the first gap slot（7）, the left side pin（3）With metal pad（2）Opposite medial extremity bottom is provided with the second gap slot
（8）, the right side pin（4）With metal pad（2）Opposite medial extremity bottom is provided with the 3rd gap slot（9）, the asphalt mixtures modified by epoxy resin
Fat cladding（5）It is coated on chip（1）, metal pad（2）, several left side pins（3）, several right side pins（4）On, institute
State metal pad（2）, left side pin（3）With right side pin（4）Respective lower surface exposes epoxy resin cladding（5）Bottom
Portion；
The chip（1）The left side area of upper surface and right side region have several left round recesseds（10）, several right circles it is recessed
Groove（11）, the left round recessed（10）With right round recessed（11）Respective bottom is respectively provided with pin area（12）, the left side pin（3）
With right side pin（4）Respective medial extremity upper surface has the first round recessed（13）With the second round recessed（14）, Ruo Gangen
First gold thread（15）One end is located at left round recessed（10）It is interior and pass through soldering paste and pin area（12）Electrical connection, this first gold thread（15）
The other end is located at left side pin（3）The first round recessed（13）It is interior and electrically connected by soldering paste, some second gold threads（16）One
End is located at right round recessed（11）It is interior and pass through soldering paste and pin area（12）Electrical connection, this second gold thread（16）The other end is located at right side
Pin（4）The second round recessed（14）It is interior and electrically connected by soldering paste；
The metal pad（2）Upper surface is provided with the annular storage cream groove of a closure along edge（18）, this annular storage cream groove（18）'s
Cross sectional shape is inverted trapezoidal, this annular storage cream groove（18）Positioned at chip（1）Underface and close chip（1）Fringe region.
2. cooling type semiconductor device according to claim 1, it is characterised in that：The left side pin（3）, right side pin
（4）The metal-coated coating of lower surface（17）.
3. cooling type semiconductor device according to claim 2, it is characterised in that：The coat of metal（17）For tin layers or
Person's NiPdAu layer.
4. cooling type semiconductor device according to claim 1, it is characterised in that：The left round recessed（10）It is recessed with right circle
Groove（11）It is semi-circular recesses.
5. cooling type semiconductor device according to claim 2, it is characterised in that：The coat of metal（17）Draw with left side
Pin（3）Or right side pin（4）Thickness ratio be 1：6~12.
6. cooling type semiconductor device according to claim 2, it is characterised in that：The left side pin（3）Draw with right side
Pin（4）Number be 3 ~ 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720164410.9U CN206532771U (en) | 2017-02-23 | 2017-02-23 | Cooling type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720164410.9U CN206532771U (en) | 2017-02-23 | 2017-02-23 | Cooling type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206532771U true CN206532771U (en) | 2017-09-29 |
Family
ID=59920032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720164410.9U Expired - Fee Related CN206532771U (en) | 2017-02-23 | 2017-02-23 | Cooling type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206532771U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022179061A1 (en) * | 2021-02-25 | 2022-09-01 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
| US11456270B2 (en) | 2021-02-25 | 2022-09-27 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
| CN116053239A (en) * | 2023-04-03 | 2023-05-02 | 中科华艺(天津)科技有限公司 | Packaging structure of multi-chip assembly |
-
2017
- 2017-02-23 CN CN201720164410.9U patent/CN206532771U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022179061A1 (en) * | 2021-02-25 | 2022-09-01 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
| US11456270B2 (en) | 2021-02-25 | 2022-09-27 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
| CN116053239A (en) * | 2023-04-03 | 2023-05-02 | 中科华艺(天津)科技有限公司 | Packaging structure of multi-chip assembly |
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