JP5293666B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP5293666B2
JP5293666B2 JP2010074442A JP2010074442A JP5293666B2 JP 5293666 B2 JP5293666 B2 JP 5293666B2 JP 2010074442 A JP2010074442 A JP 2010074442A JP 2010074442 A JP2010074442 A JP 2010074442A JP 5293666 B2 JP5293666 B2 JP 5293666B2
Authority
JP
Japan
Prior art keywords
annular magnetic
magnetic body
semiconductor device
igbt
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010074442A
Other languages
Japanese (ja)
Other versions
JP2011210771A (en
Inventor
拓也 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2010074442A priority Critical patent/JP5293666B2/en
Publication of JP2011210771A publication Critical patent/JP2011210771A/en
Application granted granted Critical
Publication of JP5293666B2 publication Critical patent/JP5293666B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Power Conversion In General (AREA)

Description

この発明は、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）などを複数個並置した半導体装置に関する。特に、ＩＧＢＴのスイッチング時にゲート電圧に重畳される高周波ノイズを抑制した半導体装置に関する。   The present invention relates to a semiconductor device in which a plurality of insulated gate bipolar transistors (IGBTs) and the like are juxtaposed. In particular, the present invention relates to a semiconductor device that suppresses high-frequency noise superimposed on a gate voltage during IGBT switching.

ＩＧＢＴは、パワースイッチングデバイスとしてモータＰＷＭ制御インバータの応用など広く使われている。また、このＩＧＢＴは電圧駆動型素子であり、電流駆動型素子と比べて扱い易いために、市場では高耐圧・大容量化への要求が強い。この市場の要求に応えるために、ＩＧＢＴチップを複数個、同一パッケージ内に集積したモジュール構造が採用されている。   IGBTs are widely used as power switching devices such as motor PWM control inverters. In addition, since this IGBT is a voltage-driven element and is easier to handle than a current-driven element, there is a strong demand for high breakdown voltage and large capacity in the market. In order to meet this market demand, a module structure in which a plurality of IGBT chips are integrated in the same package is employed.

しかし、並列に配置されたＩＧＢＴチップ間に微妙な差異が生じ、これが原因でチップ間に相互干渉が生じ、高周波ノイズが発生し、ゲート回路を誤動作させることがある。これを解決する手法として、特許文献１では、複数個の半導体チップを同一平面に並べて組み込んだいわゆる平型ＩＧＢＴにおいて、エミッタ電極と接触するコンタクト端子体の周りにパーマロイリングなどの環状磁性体を設置して、スイッチング時の半導体チップの相互干渉を防止し、高周波ノイズを低減することが特許文献１に開示されている。   However, there are subtle differences between IGBT chips arranged in parallel, which may cause mutual interference between the chips, generating high-frequency noise and causing the gate circuit to malfunction. As a technique for solving this, in Patent Document 1, an annular magnetic body such as a permalloy ring is installed around a contact terminal body in contact with an emitter electrode in a so-called flat IGBT in which a plurality of semiconductor chips are arranged in the same plane. Patent Document 1 discloses that mutual interference of semiconductor chips during switching is prevented and high-frequency noise is reduced.

また、特許文献２には、ＩＧＢＴなどの電力半導体素子がモジュールパッケージに内蔵され、このパッケージの外側に付いている端子に環状磁性材を配置して、電力用半導体素子のスイッチングに伴って端子に流れるノイズ電流を低減することが開示されている。   Further, in Patent Document 2, a power semiconductor element such as an IGBT is built in a module package, and an annular magnetic material is arranged on a terminal attached to the outside of the package so that the terminal is connected with the switching of the power semiconductor element. It is disclosed to reduce the flowing noise current.

さらに、特許文献３には、電動機を含む電動ユニットに対して一体的な取り付けが可能なインバータモジュールの入力端子および出力端子にフェライトコアを挿入して高周波のイズを低減することが開示されている。   Furthermore, Patent Document 3 discloses that a ferrite core is inserted into the input terminal and output terminal of an inverter module that can be integrally attached to an electric unit including an electric motor to reduce high-frequency noise. .

特開平９−６４２７０号公報JP-A-9-64270 特開２００５−１８３７７６号公報JP 2005-183776 A 特開２００８−１２５２４８号公報JP 2008-125248 A

しかし、特許文献１では、平型ＩＧＢＴのパッケージ内に複数個の半導体チップを収納し、これらのエミッタ電極に接触するコンタクト端子体の周りにそれぞれ環状磁性体を設置することは記載されているが、絶縁基板に複数個のチップが載置され、この半導体チップのエミッタ電極に複数本のワイヤボンデングがされているモジュールにおいて、エミッタ電極に接続する配線に環状磁性体を設置して、高周波ノイズを抑制することについては記載されていない。   However, Patent Document 1 describes that a plurality of semiconductor chips are housed in a flat IGBT package, and an annular magnetic body is provided around each contact terminal body that contacts these emitter electrodes. In a module in which a plurality of chips are mounted on an insulating substrate and a plurality of wire bonds are formed on the emitter electrode of the semiconductor chip, an annular magnetic body is placed on the wiring connected to the emitter electrode, and high frequency noise There is no description about suppressing the above.

また、特許文献２、３では、モジュールパッケージの外側の端子に環状磁性体を設置することは記載されているが、複数個の半導体チップが併設されたモジュールで個々の半導体チップのエミッタ電極に接続する配線に環状磁性体を取り囲むように設置することについては記載されていない。   Further, in Patent Documents 2 and 3, it is described that an annular magnetic body is installed on the terminal on the outside of the module package. However, a module in which a plurality of semiconductor chips are provided is connected to the emitter electrode of each semiconductor chip. There is no description about installing the wiring to surround the annular magnetic body.

この発明の目的は、導電パターン付絶縁基板に複数のスイッチング素子が固着したモジュールにおいて、ゲート電圧波形に高周波ノイズが抑制できる半導体装置を提供することにある。   An object of the present invention is to provide a semiconductor device capable of suppressing high frequency noise in a gate voltage waveform in a module in which a plurality of switching elements are fixed to an insulating substrate with a conductive pattern.

特許請求の範囲の請求項１記載の発明によれば、導電パターン付絶縁基板と、該基板に裏側が固着するスイッチング素子からなる複数の半導体チップと、前記導電パターンに固着する導体ブロックと、該導体ブロックを取り囲んで配置される環状磁性体と、前記半導体チップの表側の主電極と一方の端が接続し、他方の端が前記導体ブロックに接続するボンディングワイヤと、を具備する構成とする。 According to the patented invention in the range of claim 1 according to, the conductive pattern with an insulation substrate, a plurality of semiconductor chips comprising a switching element back to stick to the substrate, and the conductor block fixed to the conductive pattern, the An annular magnetic body disposed so as to surround the conductor block, a main electrode on the front side of the semiconductor chip, and a bonding wire that has one end connected and the other end connected to the conductor block are provided.

また、特許請求の範囲の請求項２記載の発明によれば、請求項１に記載の発明において、前記スイッチング素子にダイオード（ＦＷＤ）が逆並列接続すると構成とする。 According to the second aspect of the present invention, in the first aspect of the present invention, a diode (FWD) is connected in reverse parallel to the switching element.

また、特許請求の範囲の請求項３に記載の発明によれば、請求項１または２に記載の発明において、少なくとも前記スイッチング素子に流れる主電流を検出するために前記環状磁性体に１ターン以上の巻線を設け電流センス部とするとよい。 According to the invention described in claim 3 of the claims, in the invention described in claim 1 or 2 , at least one turn is applied to the annular magnetic body in order to detect at least a main current flowing through the switching element. It is preferable to provide a current sensing portion by providing a winding.

また、特許請求の範囲の請求項４に記載の発明によれば、請求項１〜３のいずれか一項に記載の発明において、前記環状磁性体が、パーマロイコアもしくはフェライトコアであるとよい。 According to the invention described in claim 4 of the claims, in the invention described in any one of claims 1 to 3 , the annular magnetic body may be a permalloy core or a ferrite core.

この発明によると、導電パターン付絶縁基板にＩＧＢＴチップなどのスイッチング素子が複数搭載されたモジュールにおいて、主電流の経路に環状磁性体を挿入することで、スイッチング時発生する高周波ノイズの伝播を抑制することができる。   According to the present invention, in a module in which a plurality of switching elements such as IGBT chips are mounted on an insulating substrate with a conductive pattern, the propagation of high-frequency noise generated during switching is suppressed by inserting an annular magnetic body in the main current path. be able to.

この発明の第１実施例の半導体装置の構成図であり、（ａ）はチップが固着した絶縁基板の要部平面図、（ｂ）は銅ブロックの周りに環状磁性体を配置した場合の斜視図、（ｃ）銅ブロックがない場合の環状磁性体の斜視図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, (a) is a principal part top view of the insulated substrate to which the chip | tip fixed, (b) is a perspective view at the time of arrange | positioning an annular magnetic body around a copper block FIG. 4C is a perspective view of the annular magnetic body when there is no copper block. 図１の半導体装置の要部断面図である。FIG. 2 is a main part cross-sectional view of the semiconductor device of FIG. 1. 図１の半導体装置の等価回路図である。FIG. 2 is an equivalent circuit diagram of the semiconductor device of FIG. 1. 高周波ノイズを発生させる試験回路である。This is a test circuit that generates high-frequency noise. ＩＧＢＴがスイッチングするときのゲート電圧波形とＦＷＤの電圧電流波形を示す図であり、（ａ）は環状磁性体が設置されない場合、（ｂ）は、環状磁性体が設置された場合の図である。It is a figure which shows the voltage voltage waveform of a gate voltage and FWD when IGBT switches, (a) is a figure when an annular magnetic body is not installed, (b) is a figure when an annular magnetic body is installed. . 環状磁性体１２が設置されていない従来の半導体装置の要部平面図である。It is a principal part top view of the conventional semiconductor device in which the annular magnetic body 12 is not installed. この発明の第２実施例の半導体装置の構成図であり、（ａ）はチップが固着した絶縁基板の要部平面図、（ｂ）は銅ブロックに設置された環状磁性体の斜視図である。It is a block diagram of the semiconductor device of 2nd Example of this invention, (a) is a principal part top view of the insulated substrate to which the chip fixed, (b) is a perspective view of the cyclic | annular magnetic body installed in the copper block. . この発明の第３実施例の半導体装置の要部平面図である。It is a principal part top view of the semiconductor device of 3rd Example of this invention.

実施のための形態を以下の実施例で説明する。   The mode for implementation will be described in the following examples.

図１および図２は、この発明の第１実施例の半導体装置の構成図であり、図１（ａ）はチップが固着した絶縁基板の要部平面図、図１（ｂ）は銅ブロックの周りに環状磁性体を配置した場合の斜視図、図１（ｃ）は銅ブロックがない場合の環状磁性体の斜視図、図２は図１の要部断面図である。   FIGS. 1 and 2 are configuration diagrams of a semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a plan view of an essential part of an insulating substrate to which a chip is fixed, and FIG. FIG. 1C is a perspective view of the annular magnetic body when there is no copper block, and FIG. 2 is a cross-sectional view of the main part of FIG.

３個のＩＧＢＴチップ６の裏側の図示しないコレクタ電極と３個のＦＷＤ（フリーホイール・ダイオード）チップ９の裏側の図示しないカソード電極を、絶縁基板１の導電パターン４に半田５で固着する。また、銅ブロック１１は、図２に示すように導電パターン４に半田５で固着されている。それぞれのＩＧＢＴチップ６の表側のエミッタ電極７とＦＷＤチップ９の表側のアノード電極１０はワイヤ１３で接続する。さらに、銅ブロック１１とエミッタ電極７にワイヤ１３をボンディングして互いを接続する。銅ブロック１１には図１（ｂ）に示すように環状磁性体１２が予め嵌合されている。図１（ｃ）で示すように銅ブロック１１なしに直接導電パターン４にワイヤ１３をボンディングする場合もある。その場合には環状磁性体１２の内側の空間をワイヤ１３が通るようにボンディングする。また、図１（ｃ）の場合は、環状磁性体１２は導電パターン４に図示しない絶縁膜を介して接着剤で固着される。   A collector electrode (not shown) on the back side of the three IGBT chips 6 and a cathode electrode (not shown) on the back side of the three FWD (free wheel diode) chips 9 are fixed to the conductive pattern 4 of the insulating substrate 1 with solder 5. The copper block 11 is fixed to the conductive pattern 4 with solder 5 as shown in FIG. The emitter electrode 7 on the front side of each IGBT chip 6 and the anode electrode 10 on the front side of the FWD chip 9 are connected by a wire 13. Further, a wire 13 is bonded to the copper block 11 and the emitter electrode 7 to connect each other. An annular magnetic body 12 is fitted in the copper block 11 in advance as shown in FIG. As shown in FIG. 1C, the wire 13 may be bonded directly to the conductive pattern 4 without the copper block 11. In that case, bonding is performed so that the wire 13 passes through the space inside the annular magnetic body 12. In the case of FIG. 1C, the annular magnetic body 12 is fixed to the conductive pattern 4 with an adhesive via an insulating film (not shown).

尚、導電パターン付絶縁基板１はセラミックなどの絶縁基板１と、その裏面に固着される導電膜２と、その表側に固着される導電パターンとで構成される。尚、図中の符号の８はゲート電極パッドである。   The insulating substrate with a conductive pattern 1 includes an insulating substrate 1 such as ceramic, a conductive film 2 fixed to the back surface thereof, and a conductive pattern fixed to the front side. Reference numeral 8 in the figure denotes a gate electrode pad.

つぎに、図２を用いて、この半導体装置の製造工程を説明する
まず、導電パターン付絶縁基板１の導電パターン４にＩＧＢＴチップ６のコレクタ電極とＦＷＤチップ９のカソード電極を半田５を介して固着する。また、予め銅ブロック１１に環状磁性体１２を嵌合しておき、導電パターン４に半田５を介して銅ブロック１１を固着する。ここで、環状磁性体１２は、減衰したい高周波ノイズ、すなわち主電流の経路からゲート信号の回路への伝播を抑制したい高周波ノイズの周波数帯に応じてその材料を選択すればよい。この環状磁性体１２は、例えば、パーマロイコアやフェライトコアである。 Next, the manufacturing process of the semiconductor device will be described with reference to FIG. Stick. Further, the annular magnetic body 12 is fitted in the copper block 11 in advance, and the copper block 11 is fixed to the conductive pattern 4 via the solder 5. Here, the material of the annular magnetic body 12 may be selected according to the frequency band of the high-frequency noise to be attenuated, that is, the high-frequency noise to be suppressed from propagating from the main current path to the gate signal circuit. The annular magnetic body 12 is, for example, a permalloy core or a ferrite core.

また、銅ブロック１１を導電パターン４に固着し、その表面にワイヤ１３をボンディングするのは、図１（ｃ）のように環状磁性体１２に囲まれた底の導電パターン４にワイヤ１３をボンディングするより、作業が容易になるためである。   Also, the copper block 11 is fixed to the conductive pattern 4 and the wire 13 is bonded to the surface thereof. The wire 13 is bonded to the bottom conductive pattern 4 surrounded by the annular magnetic body 12 as shown in FIG. This is because the work becomes easier.

この例では、環状磁性体１２に、たて４ｍｍ×よこ１０ｍｍ×高さ２ｍｍのものを用いた。環状磁性体の大きさならびにその内部に嵌合されている銅ブロックの大きさは、これに限るものではなく、主回路に流れる電流（主電流）や、ワイヤボンディングの本数、導電パターンの面積や形状に応じて選定すればよい。   In this example, the annular magnetic body 12 having a length of 4 mm × width of 10 mm × height of 2 mm was used. The size of the annular magnetic body and the size of the copper block fitted therein are not limited to this, but the current flowing in the main circuit (main current), the number of wire bonding, the area of the conductive pattern, What is necessary is just to select according to a shape.

この環状磁性体１２の設置位置は前記した位置に限るものではない。主電流が流れる経路に設ければよい。例えば、ＩＧＢＴチップ６のエミッタ電極７とＦＷＤチップ９のアノード電極１０の接続箇所と導電パターン４とを結ぶ配線のどの箇所に設けても構わない。この配線に流れる電流はＩＧＢＴチップ６およびＦＷＤチップ９に流れる電流（主電流）である。   The installation position of the annular magnetic body 12 is not limited to the above-described position. What is necessary is just to provide in the path | route through which a main current flows. For example, you may provide in any location of the wiring which connects the connection location of the emitter electrode 7 of the IGBT chip | tip 6, and the anode electrode 10 of the FWD chip | tip 9, and the conductive pattern 4. FIG. The current flowing through the wiring is the current (main current) flowing through the IGBT chip 6 and the FWD chip 9.

尚、銅ブロック１１に環状磁性体１２を予め嵌合して一体とした後、銅ブロック１１を導電パターン４に半田５で固着してもよいし、銅ブロック１１を導電パターン４に半田５で固着した後に、環状磁性体１２を嵌合させてもよい。   In addition, after the annular magnetic body 12 is previously fitted and integrated with the copper block 11, the copper block 11 may be fixed to the conductive pattern 4 with the solder 5, or the copper block 11 may be fixed to the conductive pattern 4 with the solder 5. After the fixing, the annular magnetic body 12 may be fitted.

つぎに、ＩＧＢＴチップ６のエミッタ電極７とＦＷＤチップ９のアノード電極９を互いにワイヤ１３で接続し、さらに環状磁性体１２が嵌合された銅ブロック１１の表面とＩＧＢＴチップ６のエミッタ電極７を複数のワイヤ１３で接続する。尚、図ではエミッタ電極７上およびアノード電極９上が多数のワイヤａでボンディングされているのは、エミッタ電極７やアノード電極８の通電能力を補うためである。   Next, the emitter electrode 7 of the IGBT chip 6 and the anode electrode 9 of the FWD chip 9 are connected to each other by a wire 13, and the surface of the copper block 11 into which the annular magnetic body 12 is fitted and the emitter electrode 7 of the IGBT chip 6 are connected. A plurality of wires 13 are connected. In the figure, the reason why the emitter electrode 7 and the anode electrode 9 are bonded by a large number of wires a is to supplement the energization capability of the emitter electrode 7 and the anode electrode 8.

つぎに、導電パターン４に配線導体１４の一方の端を固着し、他方の端を図示しないパッケージに固定した外部導出端子に接続する。
図３は、図１の半導体装置の等価回路である。３個のＩＧＢＴ６（図１のＩＧＢＴチップと同一符号を付す）は並列接続され、それぞれのＩＧＢＴ６にＦＷＤ９（図１のＦＷＤチップと同一符号を付す）が逆並列に接続している。それぞれのＩＧＢＴ６のエミッタに接続する配線には環状磁性体１２が設置されている。 Next, one end of the wiring conductor 14 is fixed to the conductive pattern 4 and the other end is connected to an external lead-out terminal fixed to a package (not shown).
FIG. 3 is an equivalent circuit of the semiconductor device of FIG. Three IGBTs 6 (same reference numerals as the IGBT chip in FIG. 1) are connected in parallel, and FWDs 9 (same reference numerals as the FWD chip in FIG. 1) are connected in antiparallel to each IGBT 6. An annular magnetic body 12 is installed on the wiring connected to the emitter of each IGBT 6.

図３に示すＦＷＤ９を逆並列接続したＩＧＢＴ６を図示しないインバータ回路に適用し、インダクタンス負荷を接続した場合、ＩＧＢＴ６がスイッチ・オンしＦＷＤ９が逆回復するときＩＧＢＴ６のゲート配線８ａに高周波ノイズが重する場合が多い。これを模擬するために図４に示す試験回路で高周波ノイズを測定した。そのときの波形を図５に示す。   When the IGBT 6 in which the FWD 9 shown in FIG. 3 is connected in reverse parallel is applied to an inverter circuit (not shown) and an inductance load is connected, when the IGBT 6 is switched on and the FWD 9 is reversely recovered, high-frequency noise is superimposed on the gate wiring 8a of the IGBT 6 There are many cases. In order to simulate this, high frequency noise was measured with the test circuit shown in FIG. The waveform at that time is shown in FIG.

図５は、ＩＧＢＴがスイッチングするときのゲート電圧波形とＦＷＤの電圧電流波形を示す図であり、同図（ａ）は環状磁性体が設置されない場合、同図（ｂ）は、環状磁性体が設置された場合である。尚、環状磁性体１２が設置されていない従来の半導体装置の要部平面図を図６に示す。   FIG. 5 is a diagram showing a gate voltage waveform and a voltage / current waveform of FWD when the IGBT is switched. FIG. 5A shows a case where no annular magnetic body is installed, and FIG. This is the case. FIG. 6 shows a plan view of the main part of a conventional semiconductor device in which the annular magnetic body 12 is not installed.

この例では、環状磁性材料にパーマロイリングを用いているが、ゲート電圧に重畳していた９８５ＭＨｚ付近の高周波ノイズが減衰していることがわかる。
図４の試験回路において、ＩＧＢＴをオンさせ、負荷のコイル（Ｌ負荷）に電流を流し、その後でＩＧＢＴをオフさせる。すると、コイルに流れている電流はＦＷＤを通して還流電流となってＦＷＤとコイルを循環する。つぎに、ＩＧＢＴをオンさせると、ＦＷＤに流れる電流は減少し、逆回復電流が流れてＦＷＤに流れる電流は零となり、還流電流はＩＧＢＴとコイルを通して流れるようになる。尚、点線で示したＦＷＤはこの試験では利用しない。 In this example, a permalloy ring is used for the annular magnetic material, but it can be seen that high-frequency noise around 985 MHz that is superimposed on the gate voltage is attenuated.
In the test circuit of FIG. 4, the IGBT is turned on, a current is passed through the load coil (L load), and then the IGBT is turned off. Then, the current flowing through the coil becomes a return current through the FWD and circulates between the FWD and the coil. Next, when the IGBT is turned on, the current flowing through the FWD decreases, the reverse recovery current flows, the current flowing through the FWD becomes zero, and the return current flows through the IGBT and the coil. Note that the FWD indicated by the dotted line is not used in this test.

ＦＷＤが逆回復するときに、環状磁性体１２が設置されない場合は図５（ａ）に示すようにゲート電圧波形に８９５ＭＨｚ程度の高周波ノイズが重畳されている。一方、環状磁性体１２を設置すると図５（ｂ）に示すようにこの高周波ノイズは抑制される。   When the annular magnetic body 12 is not installed when the FWD reversely recovers, high-frequency noise of about 895 MHz is superimposed on the gate voltage waveform as shown in FIG. On the other hand, when the annular magnetic body 12 is installed, this high frequency noise is suppressed as shown in FIG.

図１で示すようにＩＧＢＴチップ６とＦＷＤチップ９に接続するそれぞれの配線経路の中で、ＩＧＢＴチップ６とＦＷＤチップ９にできるだけ近い箇所にそれぞれ環状磁性体１２を設置することで、ＩＧＢＴチップ６のスイッチングによって発生する高周波のノイズが、モジュールの内外へ伝播するのを防ぐことができる。そして、この高周波のノイズがゲート電圧波形に重畳されることも効果的に抑制することができる。   As shown in FIG. 1, in each wiring path connected to the IGBT chip 6 and the FWD chip 9, the annular magnetic body 12 is installed at a position as close as possible to the IGBT chip 6 and the FWD chip 9. It is possible to prevent high-frequency noise generated by switching of the signal from propagating in and out of the module. And it can suppress effectively that this high frequency noise is superimposed on a gate voltage waveform.

図７は、この発明の第２実施例の半導体装置の構成図であり、同図（ａ）はチップが固着した絶縁基板の要部平面図、同図（ｂ）は銅ブロックに設置された環状磁性体の斜視図である。   FIG. 7 is a block diagram of a semiconductor device according to a second embodiment of the present invention. FIG. 7A is a plan view of the main part of an insulating substrate to which a chip is fixed, and FIG. It is a perspective view of an annular magnetic body.

図１との違いは、環状磁性体１２に１ターン以上の巻線１５を設けて、ＩＧＢＴチップ６とＦＷＤチップ９に流れる主電流を検出できるようにした点である。巻線１５は、銅ブ
ロック１１とは絶縁されている。例えば、巻線１５を環状磁性体１２に予め巻き回しておき、その後銅ブロック１１を嵌め込めばよい。この巻線１５は全ての環状磁性体１２に設けて各ＩＧＢＴチップ６に流れる主電流を検出するようにした場合や代表して１個の環状磁性体１２に設けてモジュールに流れる主電流を検出するようにした場合がある。この巻線１５は電流センス部となる。図７のように、巻線１５の両端を端子１４へ接続して外部へ導出すればよい。 The difference from FIG. 1 is that the main current flowing through the IGBT chip 6 and the FWD chip 9 can be detected by providing the annular magnetic body 12 with one or more windings 15. The winding 15 is insulated from the copper block 11. For example, the winding 15 may be wound around the annular magnetic body 12 in advance, and then the copper block 11 may be fitted. This winding 15 is provided in all the annular magnetic bodies 12 to detect the main current flowing through each IGBT chip 6 or representatively provided in one annular magnetic body 12 to detect the main current flowing through the module. There is a case to do so. This winding 15 serves as a current sensing part. As shown in FIG. 7, both ends of the winding 15 may be connected to the terminal 14 and led out to the outside.

本発明の半導体装置は、ゲート電圧波形に重畳される高周波ノイズを抑制しながら主電流を検出することができる。各チップの主電流を検出することで、チップに過大な電流が流れるのを抑制できる。また各ＩＧＢＴチップに流れる電流がアンバランスな場合、ゲート電圧を調整して、各ＩＧＢＴチップに均一な電流を流すこともできる。   The semiconductor device of the present invention can detect the main current while suppressing high frequency noise superimposed on the gate voltage waveform. By detecting the main current of each chip, it is possible to suppress an excessive current from flowing through the chip. Further, when the current flowing through each IGBT chip is unbalanced, the gate voltage can be adjusted to allow a uniform current to flow through each IGBT chip.

図８は、この発明の第３実施例の半導体装置の要部平面図である。この図はチップが固着した絶縁基板の平面図である。
図１との違いは、ＩＧＢＴチップ６のみ導電パターン付絶縁基板１に固着されている点である。この場合も環状磁性体１２を設けることで、ＩＧＢＴチップ６のスイッチング時にゲート電圧波形に重畳される高周波ノイズを抑制できる。 FIG. 8 is a plan view of an essential part of a semiconductor device according to the third embodiment of the present invention. This figure is a plan view of an insulating substrate to which a chip is fixed.
The difference from FIG. 1 is that only the IGBT chip 6 is fixed to the insulating substrate 1 with a conductive pattern. Also in this case, the provision of the annular magnetic body 12 can suppress high frequency noise superimposed on the gate voltage waveform when the IGBT chip 6 is switched.

ここで、上記の各例では、ＩＧＢＴ６とＦＷＤ９をそれぞれ３個用い、図３に示すように、ＩＧＢＴ６とＦＷＤ９の逆並列回路を３組並列に接続した構成で説明したが、これに限るものではない。   Here, in each of the above examples, three IGBTs 6 and FWDs 9 are used, respectively, and as shown in FIG. 3, three sets of anti-parallel circuits of IGBTs 6 and FWDs 9 are connected in parallel. However, the present invention is not limited to this. Absent.

例えば、ＩＧＢＴ６とＦＷＤ９をそれぞれ１個用い、ＩＧＢＴ６とＦＷＤ９の逆並列回路を１組のみで構成する半導体装置に適用してもよい。
あるいは、ＩＧＢＴ６とＦＷＤ９の逆並列回路を直列に接続して、インバータや整流回路などの電力変換装置の１アームを構成した半導体装置に適用してもよい。 For example, the present invention may be applied to a semiconductor device in which one IGBT 6 and one FWD 9 are used, and an anti-parallel circuit of the IGBT 6 and FWD 9 is configured by only one set.
Or you may apply to the semiconductor device which connected the antiparallel circuit of IGBT6 and FWD9 in series, and comprised 1 arm of power converters, such as an inverter and a rectifier circuit.

いずれの構成においても、主電流の経路に、その経路を取り囲むように環状の磁性部材を配置することにより、ＩＧＢＴなどのスイッチング素子のスイッチングに伴って発生する高周波がノイズをゲート回路などへ伝播することを防ぐことができる。   In any configuration, by arranging an annular magnetic member in the main current path so as to surround the path, a high frequency generated by switching of a switching element such as an IGBT propagates noise to a gate circuit or the like. Can be prevented.

このように、ゲート回路への高周波ノイズの伝播を防ぐことができるので、ゲート電圧に高周波ノイズが重畳されるのを防止でき、高周波ノイズによるスイッチング素子の誤動作を防止することができる。   As described above, since the propagation of the high frequency noise to the gate circuit can be prevented, the high frequency noise can be prevented from being superimposed on the gate voltage, and the malfunction of the switching element due to the high frequency noise can be prevented.

また、絶縁基板上の導電パターンに環状磁性体を固着し、その内側へワイヤボンディングを行なうか、環状磁性体の内側に嵌合された銅ブロックにワイヤボンディングを行なうことで、容易に主電流が流れる経路を取り囲むように環状磁性体を配置することができる。   In addition, the main current can be easily generated by fixing the annular magnetic body to the conductive pattern on the insulating substrate and wire bonding inside it, or wire bonding to the copper block fitted inside the annular magnetic body. An annular magnetic body can be arranged so as to surround the flow path.

１ 導電パターン付絶縁基板
２ 導電膜
３ 絶縁基板
４ 導電パターン
５ 半田
６ ＩＧＢＴチップ／ＩＧＢＴ
７ エミッタ電極
８ ゲート電極パッド
９ ＦＷＤチップ／ＦＷＤ
１０ アノード電極
１１ 銅ブロック
１２ 環状磁性体
１３、ａ ワイヤ
１４ 配線導体
１５ 巻線 DESCRIPTION OF SYMBOLS 1 Insulating substrate with a conductive pattern 2 Conductive film 3 Insulating substrate 4 Conductive pattern 5 Solder 6 IGBT chip / IGBT
7 Emitter electrode 8 Gate electrode pad 9 FWD chip / FWD
DESCRIPTION OF SYMBOLS 10 Anode electrode 11 Copper block 12 Annular magnetic body 13, a wire 14 Wiring conductor 15 Winding

Claims (4)

導電パターン付絶縁基板と、該基板に裏側が固着するスイッチング素子からなる複数の半導体チップと、前記導電パターンに固着する導体ブロックと、該導体ブロックを取り囲んで配置される環状磁性体と、前記半導体チップの表側の主電極と一方の端が接続し、他方の端が前記導体ブロックに接続するボンディングワイヤと、を具備することを特徴とする半導体装置。 An insulating substrate with a conductive pattern; a plurality of semiconductor chips comprising switching elements whose back side is fixed to the substrate; a conductor block that is fixed to the conductive pattern; an annular magnetic body that surrounds the conductor block; and the semiconductor A semiconductor device comprising: a main electrode on a front side of a chip; and a bonding wire connected at one end and connected at the other end to the conductor block. 前記スイッチング素子にダイオードが逆並列接続することを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1 , wherein a diode is connected in reverse parallel to the switching element. 少なくとも前記スイッチング素子に流れる主電流を検出するために前記環状磁性体に１ターン以上の巻線を設け電流センス部とすることを特徴とする請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein a winding of one or more turns is provided on the annular magnetic body to form a current sensing unit in order to detect at least a main current flowing through the switching element. 前記環状磁性体が、パーマロイコアもしくはフェライトコアであることを特徴とする請求項１〜３のいずれか一項に記載の半導体装置。 The annular magnetic body, the semiconductor device according to any one of claims 1 to 3, characterized in that the permalloy core or ferrite core.
JP2010074442A 2010-03-29 2010-03-29 Semiconductor device Expired - Fee Related JP5293666B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010074442A JP5293666B2 (en) 2010-03-29 2010-03-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010074442A JP5293666B2 (en) 2010-03-29 2010-03-29 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2011210771A JP2011210771A (en) 2011-10-20
JP5293666B2 true JP5293666B2 (en) 2013-09-18

Family

ID=44941559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010074442A Expired - Fee Related JP5293666B2 (en) 2010-03-29 2010-03-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JP5293666B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014063806A (en) 2012-09-20 2014-04-10 Toshiba Corp Semiconductor device
JP2014179547A (en) * 2013-03-15 2014-09-25 Toshiba Corp Semiconductor module and method of manufacturing the same
JP6211867B2 (en) 2013-09-24 2017-10-11 ルネサスエレクトロニクス株式会社 Semiconductor device
CN108475668B (en) * 2015-10-29 2019-09-27 Abb瑞士股份有限公司 Semiconductor module
WO2020170553A1 (en) 2019-02-18 2020-08-27 富士電機株式会社 Semiconductor device
JP7138596B2 (en) * 2019-05-21 2022-09-16 三菱電機株式会社 semiconductor equipment
DE102021126682A1 (en) 2021-10-14 2023-04-20 Bayerische Motoren Werke Aktiengesellschaft Measurement setup for a power module

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04109639A (en) * 1990-08-30 1992-04-10 Fujitsu Ltd Semiconductor device
JPH0661293A (en) * 1992-08-11 1994-03-04 Nippon Steel Corp Semiconductor device
JP2000171491A (en) * 1998-12-03 2000-06-23 Mitsubishi Electric Corp Power semiconductor module
JP4138192B2 (en) * 1999-12-27 2008-08-20 三菱電機株式会社 Semiconductor switch device

Also Published As

Publication number Publication date
JP2011210771A (en) 2011-10-20

Similar Documents

Publication Publication Date Title
JP5293666B2 (en) Semiconductor device
JP5259016B2 (en) Power semiconductor module
JP5637944B2 (en) Power semiconductor module
JP6394489B2 (en) Semiconductor device
US9116532B2 (en) Power semiconductor device module
US10134718B2 (en) Power semiconductor module
JP4660214B2 (en) Power semiconductor device
US10727213B2 (en) Power semiconductor module and power semiconductor device
JP2019029457A (en) Semiconductor module
US8736040B2 (en) Power module with current routing
JP6096614B2 (en) Power semiconductor module and power converter using the same
JP6969501B2 (en) Semiconductor device
JP2011200074A (en) Power converter
WO2020158057A1 (en) Power semiconductor module and power conversion device using said power semiconductor module
JP2020017623A (en) Semiconductor device
JP2007181351A (en) Inverter module of power converter
CN110176446B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
US20180191337A1 (en) Insulated gate semiconductor device and method for manufacturing insulated gate semiconductor device
JP4866143B2 (en) Power semiconductor device
JP2008306872A (en) Semiconductor device
JP5490775B2 (en) Power module
JP6394459B2 (en) Semiconductor device
JP4246040B2 (en) Semiconductor device package
JP5682194B2 (en) Power converter
WO2022168606A1 (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120614

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130219

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130221

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130422

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130514

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130527

R150 Certificate of patent or registration of utility model

Ref document number: 5293666

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees