JPH0661293A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0661293A JPH0661293A JP4235326A JP23532692A JPH0661293A JP H0661293 A JPH0661293 A JP H0661293A JP 4235326 A JP4235326 A JP 4235326A JP 23532692 A JP23532692 A JP 23532692A JP H0661293 A JPH0661293 A JP H0661293A
- Authority
- JP
- Japan
- Prior art keywords
- interconnection
- semiconductor device
- wiring
- bonding wire
- packaging part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45565—Single coating layer
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- Engineering & Computer Science (AREA)
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- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置、特にその
実装のための配線部の構成に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a wiring portion for mounting the semiconductor device.
【０００２】[0002]
【従来の技術】半導体装置を実装するために使用するボ
ンディングワイヤ，ＴＡＢ（Tape Automated Bonding）
リード等の電気的配線部は、通常その外部接続端子であ
るリードフレームやアウタリード等とＩＣチップ上の電
極パッドとの電気的導通をとるために使われている。そ
してこの電気的配線部のための配線空間は、一般に電気
的導通をとる以外に実質的機能を有していない。近年、
電磁波障害対策として電源回路等にノイズフィルタ等が
多用されてきているが、集積回路の場合には外部リード
フレーム等を通したＩＣパッケージ外部にノイズフィル
タが配置される。即ち、集積回路から離れた位置にかか
るノイズフィルタが設置されるようになっている。2. Description of the Related Art TAB (Tape Automated Bonding), a bonding wire used for mounting a semiconductor device
The electrical wiring portion such as a lead is usually used to establish electrical continuity between the lead frame, the outer lead and the like which are external connection terminals thereof and the electrode pad on the IC chip. The wiring space for the electrical wiring portion generally has no substantial function other than electrical conduction. recent years,
A noise filter or the like has been frequently used in a power supply circuit or the like as a measure against electromagnetic interference, but in the case of an integrated circuit, the noise filter is arranged outside the IC package through an external lead frame or the like. That is, the noise filter is installed at a position distant from the integrated circuit.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
半導体装置において、上記のようにノイズフィルタがＩ
Ｃチップ等の集積回路から離れて配置されているため、
それらの間の配線，実装配線長さ分の存在により、集積
回路チップの直前位置で、誤動作の原因になるノイズが
取り込まれる危険があった。また、特にＤＲＡＭ（Dyna
mic Random Access Memory）等のように瞬間的に電力を
消費する半導体デバイスにおいては、電源線と接地線と
をコンデンサを介して接続する必要があるが、デバイス
の高密度化に伴って集積回路素子相互の間隔が小さくな
りつつある現状では、コンデンサ等の外部受動素子の配
置自体が実装上の制限となっている。However, in the conventional semiconductor device, the noise filter is I as described above.
Since it is placed away from integrated circuits such as C chips,
Due to the presence of the wiring between them and the length of the mounting wiring, there is a risk that noise, which causes malfunction, may be taken in at the position immediately before the integrated circuit chip. In addition, especially DRAM (Dyna
In a semiconductor device such as a mic random access memory) that consumes power instantaneously, it is necessary to connect a power supply line and a ground line through a capacitor, but as the device density increases, integrated circuit elements In the present situation where the mutual spacing is becoming smaller, the placement itself of external passive elements such as capacitors is a mounting limitation.
【０００４】本発明はかかる実情に鑑み、上述した従来
の実装上の制限を克服すると共に、配線実装空間におい
て信号ノイズフィルタ，等価並列コンデンサ機能を持た
せた配線実装部を有する半導体装置を提供することを目
的とする。In view of such circumstances, the present invention provides a semiconductor device having a wiring mounting portion having a signal noise filter and an equivalent parallel capacitor function in a wiring mounting space, while overcoming the above-mentioned conventional restrictions on mounting. The purpose is to
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置は、
ＩＣチップ及び外部接続端子間の電気的接続を行うため
の配線実装部に、高透磁率材を配置したものである。The semiconductor device of the present invention comprises:
A high-permeability material is arranged in a wiring mounting portion for electrically connecting the IC chip and the external connection terminal.
【０００６】特に上記配線実装部は、ＴＡＢリード，ボ
ンディングワイヤ又はボンディングパッド周辺部により
構成される。In particular, the wiring mounting portion is composed of a TAB lead, a bonding wire or a bonding pad peripheral portion.
【０００７】先ずここで、配線実装部とはＩＣチップか
らその外部接続端子までの電気的接続を行うすべての配
線空間をいい、例えばリード，ボンディングワイヤ又は
ＴＡＢリード等をいうものとする。かかる配線実装部の
インダクタンスはそれに隣接する周囲の透磁率の大きさ
に比例することが知られているが、本発明に係る配線実
装部では通常の配線周囲に被覆又は隣接させることによ
り、透磁率が大きい磁性体が近傍に配置される。例えば
フェライトやアモルファス磁性体が用いられ、配線周囲
の比透磁率は数千〜一万倍で通常の配線に比べて飛躍的
に大きくなる。そしてこのインダクタンス成分が雑音吸
収と電流平滑機能を果たす。First, the wiring mounting portion means all wiring spaces for electrical connection from the IC chip to its external connection terminals, for example, leads, bonding wires or TAB leads. It is known that the inductance of such a wiring mounting portion is proportional to the magnitude of the magnetic permeability of the periphery adjacent to the wiring mounting portion. However, in the wiring mounting portion according to the present invention, the magnetic permeability can be improved by covering or adhering to the normal wiring periphery. A magnetic material having a large value is arranged in the vicinity. For example, ferrite or an amorphous magnetic material is used, and the relative magnetic permeability around the wiring is several thousand to 10,000 times, which is significantly larger than that of normal wiring. And this inductance component fulfills a noise absorption and current smoothing function.
【０００８】上記の場合、磁性体を配置する態様として
は、被覆する場合、部分的に覆う場合、塗布する場合、
装着する場合又は接触させる場合等がある。図１は配線
に用いるボンディングワイヤ１１に高透磁率材１２を被
覆した例を示しており、この例では、電流が流れたとき
に生じる磁場は上記高透磁率材１２によってボンディン
グワイヤ１１に発生する磁束密度が著しく大きくなる。
これにより、ボンディングワイヤ１１のインダクタンス
は、磁性体がその周囲にない通常の場合に比べて飛躍的
に大きくなる。そして集積回路パッケージの外部に構成
されていたフィルタ・コンデンサ機能をその最適位置で
ある集積回路パッケージの内部に構成することができ
る。In the above case, the arrangement of the magnetic material includes the following methods: covering, partially covering, and coating.
It may be attached or contacted. FIG. 1 shows an example in which a bonding wire 11 used for wiring is covered with a high magnetic permeability material 12. In this example, a magnetic field generated when a current flows is generated in the bonding wire 11 by the high magnetic permeability material 12. The magnetic flux density increases significantly.
As a result, the inductance of the bonding wire 11 is dramatically increased as compared with the normal case where the magnetic body is not present around the bonding wire 11. Then, the filter / capacitor function, which is formed outside the integrated circuit package, can be formed inside the integrated circuit package which is the optimum position.
【０００９】[0009]
【作用】ところで、集積回路がその性能を十分に発揮す
るためには、回路ノイズを除去するフィルタ及び安定動
作のためのコンデンサを可能な限り集積回路に接近して
配置する必要がある。本発明によれば、例えば上記ボン
ディングワイヤ１１の例ではその周囲の透磁率を大きく
して、配線路のインダクタンスを通常の配線よりも大き
くしたことにより、高周波ノイズを除去するフィルタ機
能及び等価平滑コンデンサ機能を兼備した高透磁率材を
配置して成る配線実装において、最適位置である能動回
路の最も近傍位置に安定化素子を配置することができ
る。このように、フィルタ機能を有する配線実装部とす
ることにより、従来の場合と同等なパッケージング空間
において、電気的によりいっそう安定動作可能な磁場環
境を形成し、これにより高い機能を有する集積回路パッ
ケージを実現することができる。In order for the integrated circuit to fully exhibit its performance, it is necessary to dispose a filter for removing circuit noise and a capacitor for stable operation as close to the integrated circuit as possible. According to the present invention, for example, in the example of the bonding wire 11 described above, the magnetic permeability around the bonding wire 11 is increased and the inductance of the wiring path is made larger than that of normal wiring, so that a filter function and an equivalent smoothing capacitor for removing high frequency noise are obtained. In wiring mounting in which a high-permeability material having a function is arranged, the stabilizing element can be arranged at the optimum position which is the closest position to the active circuit. By thus forming the wiring mounting portion having a filter function, a magnetic field environment capable of electrically more stable operation is formed in a packaging space equivalent to the conventional case, and as a result, an integrated circuit package having a high function is formed. Can be realized.
【００１０】[0010]
【実施例】以下、図２に基づき本発明の半導体装置の第
一実施例を説明する。本実施例では、高透磁率材として
フェライトを使用するが、この粉末フェライトを樹脂バ
インダーによって、径３０μｍの金ボンディングワイヤ
の表面に厚さ５μｍで被覆した。特に生産性，柔軟性及
び対ボンディングワイヤ２１との密着性等を考慮してフ
ェライト粉末を樹脂と混練させた被覆材２２を用い、こ
の高透磁率材としての被覆材２２を塗布したボンディン
グワイヤ２１を集積回路デバイスであるＤＲＡＭ集積回
路チップ２３の電源部ワイヤに適用した。なお図中、２
４はリードフレームである。従来の数十〜数百ｐＦ程度
の瞬時電力供給用コンデンサの役割を電気的に等価なワ
イヤ実装部のみにより実現することができた。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the semiconductor device of the present invention will be described below with reference to FIG. In this embodiment, ferrite is used as the high magnetic permeability material, and this powder ferrite was coated with a resin binder on the surface of a gold bonding wire having a diameter of 30 μm to a thickness of 5 μm. In particular, in consideration of productivity, flexibility, adhesion to the bonding wire 21, and the like, a coating material 22 in which ferrite powder is kneaded with a resin is used, and the bonding wire 21 coated with the coating material 22 as the high magnetic permeability material. Was applied to the power source wire of the DRAM integrated circuit chip 23 which is an integrated circuit device. In the figure, 2
Reference numeral 4 is a lead frame. The role of the conventional capacitor for instantaneous power supply of about several tens to several hundreds of pF can be realized only by the electrically equivalent wire mounting portion.
【００１１】次に本発明の半導体装置の第二実施例で
は、被覆材としてアモルファス磁性体を用いたボンディ
ングワイヤである。即ち、Ｆｅ系アモルファス磁性体と
してスパッタリング法によりワイヤ表面に磁性体を被覆
させた。Next, a second embodiment of the semiconductor device of the present invention is a bonding wire using an amorphous magnetic material as a coating material. That is, as the Fe-based amorphous magnetic material, the surface of the wire was coated with the magnetic material by the sputtering method.
【００１２】ＤＲＡＭ特有の瞬時電力消費を補うため
に、従来では所定のコンデンサを用いなければ適正動作
が得られなかった。本発明によれば強磁性体を被覆した
配線実装部が安定動作を図る受動デバイスとして機能
し、これをＩＣの電源端子の直下に接続することによ
り、コンデンサ無しの状態でＩＣの適正動作を保証する
ことができる。In order to make up for the instantaneous power consumption peculiar to DRAM, in the past, proper operation could not be obtained unless a predetermined capacitor was used. According to the present invention, the wiring mounting portion coated with the ferromagnetic material functions as a passive device for stable operation, and by connecting this directly under the power supply terminal of the IC, the proper operation of the IC is guaranteed without the capacitor. can do.
【００１３】図３は本発明の半導体装置の第三実施例を
示している。この第三実施例では、微小加工用のパルス
レーザであるアレキサンドライトレーザを用いて、高密
度，微細ビームによりビーズ加工を行い、フェライトビ
ーズを作成した。上記フェライトビーズは内径１００μ
ｍ及び外径２００μｍで、厚さ１５０μｍである。フェ
ライト材料としてはＭｎ−Ｚｎ系を用いた。そして図３
に示したように、かかるフェライトビーズ３１をＤＲＡ
Ｍ−ＩＣデバイス３２の電源部ボンディングパッド３３
の周囲に配置して配線実装を行った。なお図中、３４は
ボンディングワイヤ、３５はリードフレームである。FIG. 3 shows a third embodiment of the semiconductor device of the present invention. In the third embodiment, a bead processing is performed by a high-density, fine beam using an alexandrite laser which is a pulse laser for micro processing, and ferrite beads are produced. The ferrite beads have an inner diameter of 100μ
m, the outer diameter is 200 μm, and the thickness is 150 μm. A Mn-Zn system was used as the ferrite material. And Figure 3
As shown in FIG.
Power unit bonding pad 33 of M-IC device 32
Wiring was performed by placing it around. In the figure, 34 is a bonding wire and 35 is a lead frame.
【００１４】第三実施例によれば、従来ＩＣの瞬間電力
供給用に用いられていたコンデンサの機能を上記ボンデ
ィングパッド３３上のフェライトビーズ３１によって実
現することができる。かかる構成により、外部に接続さ
れるべきコンデンサを使用することなく、デバイス動作
可能電圧を維持するように、電源ラインの瞬間電圧低下
を抑制し、これにより従来コンデンサを使用しないと機
能しなかったＩＣを動作させることが可能になった。According to the third embodiment, the function of the capacitor which has been conventionally used for instantaneous power supply of IC can be realized by the ferrite beads 31 on the bonding pad 33. With such a configuration, an instantaneous voltage drop of the power supply line is suppressed so as to maintain the device operable voltage without using a capacitor that should be connected to the outside, and thus the conventional IC that would not function unless a capacitor was used. It became possible to operate.
【００１５】図４は本発明の半導体装置の第四実施例を
示している。この第四実施例では、樹脂を混練したフェ
ライト粉末で成る高透磁率材４１をＴＡＢインナーリー
ド４２の電源ライン上に塗布し、このＴＡＢインナーリ
ード４２の端部をバンプ４３を介してＩＣチップ４４と
接続したものである。FIG. 4 shows a fourth embodiment of the semiconductor device of the present invention. In the fourth embodiment, a high magnetic permeability material 41 made of ferrite powder mixed with resin is applied on the power supply line of the TAB inner lead 42, and the end portion of the TAB inner lead 42 is bumped 43 to the IC chip 44. It is connected with.
【００１６】この第四実施例によれば、ＴＡＢインナー
リード４２のインダクタンスを大きくし、これにより従
来所謂、外付けコンデンサを電源ラインに接続しなけれ
ば、動作することができなかったＤＲＡＭ−ＩＣデバイ
スをコンデンサ無しで動作させることができた。According to the fourth embodiment, the inductance of the TAB inner lead 42 is increased so that the DRAM-IC device which cannot operate unless the so-called external capacitor is connected to the power supply line. Could be operated without a capacitor.
【００１７】[0017]
【発明の効果】以上説明したように本発明によれば、強
磁性体を配線実装部に配置し、これによりインダクタン
ス成分を増大させた配線が、ノイズフィルタ・等価並列
コンデンサの役目を果たすようにすることができる。こ
の結果、高周波化に伴い従来必要になっていた外部接続
素子を設けることなく、従来の半導体装置と実質的に同
等なパッケージ空間において、ノイズや瞬間電力消費に
対して極めて強く安定した集積回路を有効に実現するこ
とができる等の利点がある。As described above, according to the present invention, the ferromagnetic material is arranged in the wiring mounting portion so that the wiring having an increased inductance component serves as a noise filter and an equivalent parallel capacitor. can do. As a result, an integrated circuit that is extremely strong and stable against noise and instantaneous power consumption is provided in a package space substantially equivalent to that of a conventional semiconductor device without providing an external connection element that has been conventionally required with the increase in frequency. There are advantages such as effective realization.
【図１】本発明の半導体装置における高透磁率材が被覆
されたボンディングワイヤの断面図である。FIG. 1 is a cross-sectional view of a bonding wire coated with a high magnetic permeability material in a semiconductor device of the present invention.
【図２】本発明の半導体装置の第一実施例による高透磁
率材が被覆されたボンディングワイヤを、集積回路の配
線実装時に電源配線として使用した例を示す平面図であ
る。FIG. 2 is a plan view showing an example in which a bonding wire coated with a high-permeability material according to the first embodiment of the semiconductor device of the present invention is used as a power supply wiring during wiring mounting of an integrated circuit.
【図３】本発明の半導体装置の第三実施例による高透磁
率材としてのフェライトビーズを、集積回路のパッドに
配置してボンディングを行う例を示す斜視図である。FIG. 3 is a perspective view showing an example in which ferrite beads as high magnetic permeability materials according to a third embodiment of the semiconductor device of the present invention are arranged on pads of an integrated circuit and bonding is performed.
【図４】本発明の半導体装置の第四実施例による高透磁
率材が塗布されたインナーリードを、集積回路の電源部
に適用した例を示す部分側面図である。FIG. 4 is a partial side view showing an example in which an inner lead coated with a high-permeability material according to a fourth embodiment of the semiconductor device of the present invention is applied to a power supply section of an integrated circuit.
１１，２１，３４ ボンディングワイヤ １２，４１ 高透磁率材 ２２ 被覆材 ２３ 集積回路チップ ２４ リードフレーム ３１ フェライトビーズ ３３ ボンディングパッド ３５ リードフレーム ４２ インナーリード ４４ ＩＣチップ 11,21,34 Bonding wire 12,41 High magnetic permeability material 22 Covering material 23 Integrated circuit chip 24 Lead frame 31 Ferrite bead 33 Bonding pad 35 Lead frame 42 Inner lead 44 IC chip
Claims (4)
接続を行うための配線実装部に、高透磁率材を配置した
ことを特徴とする半導体装置。1. A semiconductor device in which a high-permeability material is arranged in a wiring mounting portion for electrically connecting an IC chip and an external connection terminal.
ことを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the wiring mounting portion is a TAB lead.
であることを特徴とする請求項１に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the wiring mounting portion is a bonding wire.
周辺部であることを特徴とする請求項１に記載の半導体
装置。4. The semiconductor device according to claim 1, wherein the wiring mounting portion is a peripheral portion of a bonding pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4235326A JPH0661293A (en) | 1992-08-11 | 1992-08-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4235326A JPH0661293A (en) | 1992-08-11 | 1992-08-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0661293A true JPH0661293A (en) | 1994-03-04 |
Family
ID=16984453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4235326A Withdrawn JPH0661293A (en) | 1992-08-11 | 1992-08-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0661293A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6430085B1 (en) * | 2001-08-27 | 2002-08-06 | Motorola, Inc. | Magnetic random access memory having digit lines and bit lines with shape and induced anisotropy ferromagnetic cladding layer and method of manufacture |
| US6430084B1 (en) * | 2001-08-27 | 2002-08-06 | Motorola, Inc. | Magnetic random access memory having digit lines and bit lines with a ferromagnetic cladding layer |
| JP2011210771A (en) * | 2010-03-29 | 2011-10-20 | Fuji Electric Co Ltd | Semiconductor device |
| DE102013104955A1 (en) * | 2013-05-14 | 2014-11-20 | Epcos Ag | Multi-layer component with an external contact |
-
1992
- 1992-08-11 JP JP4235326A patent/JPH0661293A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6430085B1 (en) * | 2001-08-27 | 2002-08-06 | Motorola, Inc. | Magnetic random access memory having digit lines and bit lines with shape and induced anisotropy ferromagnetic cladding layer and method of manufacture |
| US6430084B1 (en) * | 2001-08-27 | 2002-08-06 | Motorola, Inc. | Magnetic random access memory having digit lines and bit lines with a ferromagnetic cladding layer |
| JP2011210771A (en) * | 2010-03-29 | 2011-10-20 | Fuji Electric Co Ltd | Semiconductor device |
| DE102013104955A1 (en) * | 2013-05-14 | 2014-11-20 | Epcos Ag | Multi-layer component with an external contact |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991102 |