JPH06140451A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH06140451A
JPH06140451A JP4311370A JP31137092A JPH06140451A JP H06140451 A JPH06140451 A JP H06140451A JP 4311370 A JP4311370 A JP 4311370A JP 31137092 A JP31137092 A JP 31137092A JP H06140451 A JPH06140451 A JP H06140451A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
power supply
inductance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4311370A
Other languages
Japanese (ja)
Inventor
Hiroshi Maeda
浩 前田
Osamu Arashida
修 嵐田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Ltd
Hitachi Yonezawa Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Yonezawa Electronics Co Ltd filed Critical Hitachi Ltd
Priority to JP4311370A priority Critical patent/JPH06140451A/en
Publication of JPH06140451A publication Critical patent/JPH06140451A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H—ELECTRICITY
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    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
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    • H01L2924/30107—Inductance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a semiconductor integrated circuit device from which the number of external circuit parts required to reduce power supply noise and voltage reflection can be reduced and, at the same time, the labor required for fitting the external circuit parts can be reduced. CONSTITUTION:The bonding pad 5 of a semiconductor integrated circuit chip 1 is connected to the lead terminal 3 of the package incorporating the chip 1 through a bonding wire 12 which is wound one or more turns so as to form an inductance. Since the bonding wire 12 having the inductance is effective to reduce power supply noise and voltage reflection, the number of external circuit parts of this semiconductor integrated circuit device can be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、ボンディング形式でパ
ッケージされる半導体集積回路装置に係わり、例えば電
源ノイズ及び電圧反射対策に有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device packaged in a bonding type, and more particularly to a technique effective for measures against power supply noise and voltage reflection.

【０００２】[0002]

【従来の技術】電源ノイズ対策として、インダクタン
ス、インダクタンスと容量素子、又はインダクタンスと
抵抗素子を、電源供給経路に設けることができる。この
ような対策について記載された文献の例としては、例え
ば、昭和５８年８月２０日に（株）オーム社から発行さ
れた『電子通信ハンドブック』の第１５４５頁がある。
また、電圧反射対策として、インダクタンス、又は、イ
ンダクタンスと抵抗素子を、信号経路に配置することが
できる。斯る対策について記載された文献の例として
は、前記『電子通信ハンドブック』の第９３２頁があ
る。本発明者は、電源ノイズ対策として、半導体集積回
路装置の電源用リード端子が接続される実装ボード上の
電源用の配線に、インダクタンスと抵抗素子を直列接続
したモジュールを設け、また電圧反射対策として、前記
実装ボード上の信号用の配線に、インダクタンスと抵抗
素子を接続したモジュールを設けることについて検討し
た。2. Description of the Related Art As a measure against power supply noise, an inductance, an inductance and a capacitance element, or an inductance and a resistance element can be provided in a power supply path. An example of a document describing such countermeasures is, for example, page 1545 of "Electronic Communication Handbook" published by Ohmsha Co., Ltd. on August 20, 1983.
In addition, as a countermeasure against voltage reflection, an inductance or an inductance and a resistance element can be arranged in the signal path. An example of a document describing such countermeasures is page 932 of the "Electronic Communication Handbook". As a power supply noise countermeasure, the present inventor provides a module in which an inductance and a resistance element are connected in series on a power supply wiring on a mounting board to which a power supply lead terminal of a semiconductor integrated circuit device is connected, and also as a voltage reflection countermeasure. It was examined to provide a module in which an inductance and a resistance element were connected to the signal wiring on the mounting board.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、発明者
は、前記インダクタンス及びその他の素子を接続したモ
ジュールを前記半導体集積回路装置のリード端子が接続
される実装ボード上に設けると、それに係る手間とその
ための回路部品の点数が多くなることを見い出した。However, when the inventor provides the module to which the inductance and other elements are connected on the mounting board to which the lead terminals of the semiconductor integrated circuit device are connected, the inconvenience and the related work are required. It was found that the number of circuit components of the above increases.

【０００４】本発明の目的は、半導体集積回路装置の電
源ノイズ対策及び電圧反射対策のための外づけ回路部品
の部品点数を減らすこができると共に、外付けのための
手間を省くことができる半導体集積回路装置を提供する
ことにある。An object of the present invention is to reduce the number of external circuit components for power supply noise countermeasures and voltage reflection countermeasures for semiconductor integrated circuit devices, and to reduce the time and effort required for external attachment. An object is to provide an integrated circuit device.

【０００５】本発明の前記並びにその他の目的と新規な
特徴は本明細書の記述及び添付図面から明らかになるで
あろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【０００６】[0006]

【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば下記
の通りである。The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

【０００７】すなわち、本発明の半導体集積回路装置
は、電源ノイズ対策及び電圧反射対策を考慮し、そのた
めの回路素子として、ボンディングパッドに接続される
ボンディングワイヤの一部を１回以上巻回して成るイン
ダクタンスを内蔵する。さらに、その他の回路素子とし
て抵抗素子や容量素子を必要とするときには、これらを
該当するボンディングパッドに接続して半導体集積回路
チップに内蔵させるとよい。That is, in the semiconductor integrated circuit device of the present invention, in consideration of the power supply noise countermeasure and the voltage reflection countermeasure, a part of the bonding wire connected to the bonding pad is wound one or more times as a circuit element therefor. Built-in inductance. Further, when a resistance element or a capacitance element is required as another circuit element, these elements may be connected to the corresponding bonding pad and built in the semiconductor integrated circuit chip.

【０００８】[0008]

【作用】上記した手段によれば、電源供給用ボンディン
グパットに接続され、インダクタンスを保有するボンデ
ィングワイヤは、外付け回路部品としてのインダクタン
ス素子を要することなく電源ノイズを低減する。前記ボ
ンディングワイヤに加え、半導体集積回路チップの内部
に設けた抵抗素子又は容量素子も同様に、同種の外付け
回路部品を省いて電源ノイズ対策に資する。信号用ボン
ディングパットに接続され、インダクタンスを保有する
ボンディングワイヤは、外付け回路部品としてのインダ
クタンス素子を要することなく電圧反射を低減する。前
記ボンディングワイヤに加え、半導体集積回路チップの
内部に設けた抵抗素子も同様に、同種の外付け回路部品
を省いて電圧反射対策に資する。According to the above means, the bonding wire which is connected to the power supply bonding pad and holds the inductance reduces the power supply noise without requiring an inductance element as an external circuit component. In addition to the bonding wire, the resistance element or the capacitance element provided inside the semiconductor integrated circuit chip similarly contributes to the power supply noise countermeasure by omitting the same kind of external circuit component. The bonding wire connected to the signal bonding pad and having an inductance reduces voltage reflection without requiring an inductance element as an external circuit component. In addition to the bonding wire, the resistance element provided inside the semiconductor integrated circuit chip also contributes to the voltage reflection countermeasure by omitting the same kind of external circuit component.

【０００９】[0009]

【実施例】図１には本発明の一実施例に係る半導体集積
回路装置の要部が示され、図２には、係る半導体集積回
路装置の全体がパッケージの一部を切欠して示されてい
る。1 shows a main part of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 shows the whole semiconductor integrated circuit device with a part of a package cut away. ing.

【００１０】本実施例の半導体集積回路装置は、半導体
集積回路チップ１と当該半導体集積回路チップ１を内蔵
するパッケージ２から成る。前記半導体集積回路チップ
１は特に制限されないが、公知の半導体集積回路製造技
術により、単結晶シリコンのような半導体基板に複数個
の回路素子が集積されて所定の回路機能を持ち、例え
ば、メモリ、マイクロコンピュータ、或いはアナログ用
ＬＳＩ（ラージ．スケール．インテグレーテッド．サー
キッツ）とされる。前記半導体集積回路装置は、前記半
導体集積回路チップ１と前記パッケージ２をつなぐ金細
線等のボンディングワイヤが熱圧着又は超音波ボンディ
ングされており、後述する電源ノイズ及び電圧反射対策
の手段を内蔵する。The semiconductor integrated circuit device of this embodiment comprises a semiconductor integrated circuit chip 1 and a package 2 having the semiconductor integrated circuit chip 1 built therein. The semiconductor integrated circuit chip 1 is not particularly limited, but by a known semiconductor integrated circuit manufacturing technique, a plurality of circuit elements are integrated on a semiconductor substrate such as single crystal silicon and have a predetermined circuit function. It is a microcomputer or an analog LSI (Large Scale Integrated Circuits). In the semiconductor integrated circuit device, a bonding wire such as a gold wire connecting the semiconductor integrated circuit chip 1 and the package 2 is thermocompression-bonded or ultrasonic-bonded, and has a built-in means for preventing power supply noise and voltage reflection, which will be described later.

【００１１】図２において、前記半導体集積回路チップ
１は、外部との電源供給、信号のやりとり等のための接
続箇所として、複数のボンディングパッドを備えてい
る。前記複数のボンディングパッドのうち、電源供給用
ボンディングパッド５は、ボンディングワイヤ１２でパ
ッケージ２の電源供給用リード端子３と接続されてい
る。又、前記複数のボンディングパッドのうち、信号用
ボンディングパッド８は、ボンディングワイヤ１３で信
号用リード端子６に接続されている。当該ボンディング
ワイヤ１２は、例えば予め形状を特定してコイル状に巻
かれた細い被覆ワイヤが、そのままの形状でボンディン
グされたもので、インダクタンスを形成して電源ノイズ
対策の有効な手段となる。前記ボンディングワイヤ１３
は、同様にされたもので、やはりインダクタンスを形成
して電圧反射対策の有効な手段となる。なお、前記ボン
ディングワイヤ１２，１３の形成するインダクタンス値
は、ボンディングワイヤのコイルの形、寸法、巻数及び
内部の物質の透磁率などによって決定され、必要とされ
るインダクタンス値から、その寸法や巻数を割り出すと
よい。In FIG. 2, the semiconductor integrated circuit chip 1 is provided with a plurality of bonding pads as connection points for supplying power to the outside and exchanging signals. Of the plurality of bonding pads, the power supply bonding pad 5 is connected to the power supply lead terminal 3 of the package 2 by the bonding wire 12. Further, among the plurality of bonding pads, the signal bonding pad 8 is connected to the signal lead terminal 6 by the bonding wire 13. The bonding wire 12 is, for example, a thin covered wire which is specified in shape and wound in a coil shape in advance, and is bonded in the same shape. The bonding wire 12 forms an inductance and is an effective measure against power supply noise. The bonding wire 13
Is the same as above, and also forms an inductance and becomes an effective means for countermeasures against voltage reflection. The inductance value formed by the bonding wires 12 and 13 is determined by the shape, size, and number of turns of the coil of the bonding wire and the magnetic permeability of the internal substance. You should figure out.

【００１２】前記半導体集積回路チップ１には、前記電
源ノイズ対策並びに電圧反射対策のために、前記インダ
クタンスに加えて、抵抗素子９，１０を内蔵することが
できる。斯る抵抗素子は接続する電源供給用ボンディン
グパット５又は信号用ボンディングパッド８に直列に接
続される。例えば前記抵抗素子９，１０は、Ｎ型半導体
領域にＰ型の不純物を選択拡散したり、ポリシリコンな
どの高抵抗配線材料を利用して形成することができる。
また、同様に前記チップには、内蔵された容量素子１１
を形成しておくことができる。この容量素子１１の一方
の蓄積電極は電源供給用ボンディングパッド５に接続さ
れ、他方の蓄積電極は極性の異なる電源（例として５Ｖ
のようなＶｄｄに対する０ＶのようなＶｓｓ）若しくは
電源の中間電位に接続される。斯る容量素子１１は、導
電型の異なる半導体領域を利用した接合容量、又は一対
の導電層の間に誘電体層を形成した構造などを採用する
ことができる。また、前記電源供給用ボンディングパッ
ト５に直列に接続された抵抗素子９や容量素子１１を内
蔵することにより、当該抵抗素子９や容量素子１１は、
ボンディングワイヤ１２とともに電源ノイズ対策の有効
な手段となる。また、前記信号用ボンディングパット８
に直列に接続された抵抗素子１０を内蔵することによ
り、当該抵抗素子１０は、ボンディングワイヤ１３とと
もに電圧反射対策の有効な手段となる。In the semiconductor integrated circuit chip 1, in addition to the inductance, resistance elements 9 and 10 can be built in as a countermeasure against the power supply noise and the voltage reflection. The resistance element is connected in series to the power supply bonding pad 5 or the signal bonding pad 8 to be connected. For example, the resistance elements 9 and 10 can be formed by selectively diffusing P-type impurities in an N-type semiconductor region or using a high resistance wiring material such as polysilicon.
Similarly, the chip has a built-in capacitive element 11
Can be formed. One storage electrode of the capacitive element 11 is connected to the bonding pad 5 for power supply, and the other storage electrode has a power supply of different polarity (for example, 5V).
Vss such as 0V to Vdd) or the intermediate potential of the power supply. The capacitive element 11 may employ a junction capacitance using semiconductor regions having different conductivity types, a structure in which a dielectric layer is formed between a pair of conductive layers, or the like. Further, by incorporating the resistance element 9 and the capacitance element 11 connected in series to the power supply bonding pad 5, the resistance element 9 and the capacitance element 11 are
Together with the bonding wire 12, it becomes an effective measure against power supply noise. In addition, the signal bonding pad 8
By incorporating the resistance element 10 connected in series with the resistance element 10 together with the bonding wire 13, the resistance element 10 becomes an effective measure against voltage reflection.

【００１３】以上のように構成された本実施例の半導体
集積回路装置は、その他の集積回路装置や回路部品とと
もに、所定の実装ボード（図示せず）に搭載されること
になる。電源供給用リード端子３は実装ボード上の電源
配線に接続され、信号用リード端子６は実装ボード上の
所定の信号配線に接続される。このとき、半導体集積回
路装置ための電源ノイズ対策や電圧反射対策のための回
路素子は、この半導体集積回路装置本体に内蔵されてい
るため、斯る対策のために特別な外付け回路部品を実装
する必要はない。これによって、半導体集積回路装置の
ための電源ノイズ対策や電圧反射対策のための外付け回
路部品の点数を削減することができるとともに、これを
実装するための手間を省くことができる。The semiconductor integrated circuit device of the present embodiment configured as described above is mounted on a predetermined mounting board (not shown) together with other integrated circuit devices and circuit components. The power supply lead terminal 3 is connected to the power supply wiring on the mounting board, and the signal lead terminal 6 is connected to a predetermined signal wiring on the mounting board. At this time, since the circuit element for the power supply noise countermeasure and the voltage reflection countermeasure for the semiconductor integrated circuit device is built in the main body of the semiconductor integrated circuit device, a special external circuit component is mounted for the countermeasure. do not have to. As a result, it is possible to reduce the number of external circuit components for the power supply noise countermeasure and the voltage reflection countermeasure for the semiconductor integrated circuit device, and it is possible to save the labor for mounting them.

【００１４】特に本実施例においては、被覆ワイヤを利
用しているので、パッケージをモールドするときの流体
抵抗によってコイル部品が不所望に接触しても、コイル
自体の長さは変わらないから、規定のインダクタンス値
が不所望にばらつくおそれを回避することができる。In particular, in this embodiment, since the covered wire is used, the length of the coil itself does not change even if the coil component undesirably comes into contact with the package due to the fluid resistance when the package is molded. It is possible to avoid the possibility that the inductance value of the variable undesirably varies.

【００１５】更に半導体集積回路装置内蔵のインダクタ
ンスにボンディングワイヤを流用しているので、チップ
サイズそれ自体並びにパッケージのサイズに影響を与え
ない。Further, since the bonding wire is diverted to the inductance built in the semiconductor integrated circuit device, it does not affect the chip size itself and the package size.

【００１６】以上本発明者によってなされた発明を実施
例に基づいて具体的に説明したが、本発明はそれに限定
されるものではなく、その要旨を逸脱しない範囲におい
て種々変更可能であることは言うまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

【００１７】例えば、ボンディングワイヤ１２，１３
は、被覆ワイヤでなくてもよい。また、ボンディングワ
イヤ１２，１３をコイル状にしてボンディングする手段
は、その機能をボンディング装置に持たせてもよい。ま
た、抵抗素子９，１０や容量素子１１の構成には、その
他の構成を適宜採用できる。For example, the bonding wires 12 and 13
May not be a coated wire. In addition, the bonding device may have the function of the means for bonding the bonding wires 12 and 13 in a coil shape. Further, other configurations can be appropriately adopted for the configurations of the resistance elements 9 and 10 and the capacitive element 11.

【００１８】[0018]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば下記
の通りである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

【００１９】すなわち、半導体集積回路装置の内部に、
ボンディングワイヤを巻回して形成されるインダクタン
ス、更に必要な場合には半導体集積回路チップ内部でそ
れに接続する抵抗や容量素子を設けてなる半導体集積回
路装置を実現し、これらが同装置の電源ノイズ対策や電
圧反射対策に寄与するから、それら対策のために必要と
された外付け回路部品の部品点数を少なくすることがで
きるとともに、それを実装するための手間を省くことが
できるという効果がある。That is, inside the semiconductor integrated circuit device,
We have realized a semiconductor integrated circuit device that has an inductance formed by winding a bonding wire and, if necessary, a resistor and a capacitance element connected to it inside the semiconductor integrated circuit chip, and these are measures against power supply noise of the device. Since it contributes to the countermeasures against the voltage reflection and the voltage reflection, it is possible to reduce the number of external circuit components required for the countermeasures and to reduce the labor for mounting the external circuit components.

【００２０】更にインダクタンスは、ボンディングワイ
ヤを流用しているので、チップサイズやパッケージのサ
イズには一切影響を与えない。Furthermore, since the inductance uses the bonding wire, it has no influence on the chip size and the package size.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例に係る半導体集積回路装置の
要部を示す斜視図である。FIG. 1 is a perspective view showing a main part of a semiconductor integrated circuit device according to an embodiment of the present invention.

【図２】半導体集積回路装置の全体を、パッケージの一
部を切欠して示す説明図である。FIG. 2 is an explanatory diagram showing the entire semiconductor integrated circuit device with a part of the package cut away.

【符号の説明】[Explanation of symbols]

１ 半導体集積回路チップ ２ パッケージ ３ 電源供給用リード端子 ５ 電源供給用ボンディングパッド ６ 信号用リード端子 ８ 信号用ボンディングパッド ９ 〜１０ 抵抗素子 １１ 容量素子 １２〜１３ ボンディングワイヤ 1 Semiconductor Integrated Circuit Chip 2 Package 3 Power Supply Lead Terminal 5 Power Supply Bonding Pad 6 Signal Lead Terminal 8 Signal Bonding Pad 9-10 Resistive Element 11 Capacitive Element 12-13 Bonding Wire

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 半導体集積回路チップのボンディングパ
ッドを、同チップを内蔵するパッケージのリード端子
に、ボンディングワイヤで接続して成る半導体集積回路
装置において、所定の前記ボンディングワイヤは、その
一部が１回以上巻回されてインダクタンスを形成して成
るものであることを特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device comprising a bonding pad of a semiconductor integrated circuit chip connected to a lead terminal of a package containing the same chip with a bonding wire, wherein a part of the predetermined bonding wire is 1 part. A semiconductor integrated circuit device characterized by being formed by winding more than once to form an inductance. 【請求項２】 前記所定のボンディングワイヤは、電源
供給用ボンディングパッドに接続され、当該ボンディン
グワイヤが保有するインダクタンスは、電源ノイズ対策
のための回路素子を構成するものであることを特徴とす
る請求項１記載の半導体集積回路装置。2. The predetermined bonding wire is connected to a power supply bonding pad, and the inductance held by the bonding wire constitutes a circuit element for power supply noise countermeasures. Item 2. The semiconductor integrated circuit device according to item 1. 【請求項３】 半導体集積回路チップの内部には、前記
電源供給用ボンディングパッドに接続した抵抗素子又は
容量素子を設けて成るものであることを特徴とする請求
項２記載の半導体集積回路装置。3. The semiconductor integrated circuit device according to claim 2, wherein a resistance element or a capacitance element connected to the power supply bonding pad is provided inside the semiconductor integrated circuit chip. 【請求項４】 前記所定のボンディングワイヤは、信号
入力、信号出力、又は信号入出力の中から選ばれた一つ
の機能を有する信号用ボンディングパッドに結合され、
当該ボンディングワイヤが保有するインダクタンスは、
電圧反射対策のための回路素子を構成するものであるこ
とを特徴とする請求項１記載の半導体集積回路装置。4. The predetermined bonding wire is coupled to a signal bonding pad having one function selected from signal input, signal output, or signal input / output,
The inductance of the bonding wire is
2. The semiconductor integrated circuit device according to claim 1, which constitutes a circuit element as a countermeasure against voltage reflection. 【請求項５】 半導体集積回路チップの内部には、信号
用ボンディングパッドに接続した抵抗素子を設けて成る
ものであることを特徴とする請求項４記載の半導体集積
回路装置。5. The semiconductor integrated circuit device according to claim 4, wherein a resistance element connected to the signal bonding pad is provided inside the semiconductor integrated circuit chip.
JP4311370A 1992-10-27 1992-10-27 Semiconductor integrated circuit device Withdrawn JPH06140451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4311370A JPH06140451A (en) 1992-10-27 1992-10-27 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4311370A JPH06140451A (en) 1992-10-27 1992-10-27 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH06140451A true JPH06140451A (en) 1994-05-20

Family

ID=18016362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4311370A Withdrawn JPH06140451A (en) 1992-10-27 1992-10-27 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH06140451A (en)

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US7671617B2 (en) 2006-11-07 2010-03-02 Samsung Electronics Co., Ltd. Test system to test multi-chip package compensating a signal distortion
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US8247825B2 (en) 2008-12-26 2012-08-21 Fu Zhun Precision Industry (Shen Zhen) Co., Ltd. Light emitting diode
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US8315068B2 (en) 2009-11-12 2012-11-20 International Business Machines Corporation Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same
US8310841B2 (en) 2009-11-12 2012-11-13 International Business Machines Corporation Integrated circuit die stacks having initially identical dies personalized with switches and methods of making the same
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