JPH04186667A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04186667A
JPH04186667A JP2312540A JP31254090A JPH04186667A JP H04186667 A JPH04186667 A JP H04186667A JP 2312540 A JP2312540 A JP 2312540A JP 31254090 A JP31254090 A JP 31254090A JP H04186667 A JPH04186667 A JP H04186667A
Authority
JP
Japan
Prior art keywords
coil
semiconductor chip
semiconductor device
insulating film
electric circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2312540A
Other languages
Japanese (ja)
Inventor
Keisuke Ishibashi
敬介 石橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Corp
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Corp, Omron Tateisi Electronics Co filed Critical Omron Corp
Priority to JP2312540A priority Critical patent/JPH04186667A/en
Publication of JPH04186667A publication Critical patent/JPH04186667A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16235Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Coils Or Transformers For Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To make the occupancy area of a mounting board small, and miniaturize it and reduce cost by packaging the electric circuit requiring a coil as one part. CONSTITUTION:A plane coil 2 is stacked on the surface of a semiconductor chip 1 through an insulating film 5, and both ends 2A and 2B of this plane coil 2 are connected electrically to the proper electrode pads 1A and 1B of the semiconductor chip 1. This way, by molding the one, where the plane coil 2 is united with the semiconductor chip 1, with resin, the electric circuit requiring to use the coil is packaged as one part. It can be materialized as a device, which includes a band removing filter, a Colpitts oscillating circuit, or a differential circuit.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、平面形コイルを内蔵した半導体装置に関する
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device incorporating a planar coil.

〈従来技術〉 現在の半導体集積技術では、半導体基板に、抵抗やコン
デンサなどの受動素子、ダイオードやトランジスタなど
の能動素子などを形成することはできるけれども、コイ
ルについては形成すること1ができない。
<Prior Art> Current semiconductor integration technology allows passive elements such as resistors and capacitors, and active elements such as diodes and transistors to be formed on a semiconductor substrate, but it is not possible to form coils.

ところで、コイルを用いる電気回路として、例えば帯域
除去フィルタ(BEF)やコルピイソツ発振回路などが
あるが、これらは、いずれも、能動素子や受動素子から
なる所定の電気回路が形成された半導体チップをパッケ
ージ化してなる半導体装置と、外付はコイルとを用い、
これらをそれぞれプリント基板上に実装するとともに、
プリント基板上のプリント配線を介して接続することに
より、製作されるのが一般的である。
By the way, examples of electric circuits that use coils include band-elimination filters (BEF) and Korpiisotsu oscillation circuits, but these are all packaged with a semiconductor chip on which a predetermined electric circuit consisting of active elements and passive elements is formed. Using a semiconductor device made up of a semiconductor device and an external coil,
Each of these is mounted on a printed circuit board, and
It is generally manufactured by connecting via printed wiring on a printed circuit board.

〈発明が解決しようとする課題〉 このように、従来では、コイルを必要とする電気回路の
場合、半導体チップ内部にコイルを除く回路要素しか形
成できないので、それとは別に外付はコイルが必要にな
っている。そのため、部品点数や組付工数が多くなって
、プリント基板上の占有面積が大きくなるといった問題
があり、近年益々要求される小型化、低コスト化に対応
できなくなってきている。
<Problems to be Solved by the Invention> As described above, conventionally, in the case of an electric circuit that requires a coil, only the circuit elements other than the coil can be formed inside the semiconductor chip. It has become. As a result, there are problems in that the number of parts and the number of assembly steps increase, and the area occupied on the printed circuit board increases, making it impossible to meet the demands for miniaturization and cost reduction that have been increasingly demanded in recent years.

本発明は、このような事情に鑑みて創案されたもので、
コイルを必要とする電気回路の構成を簡酪化することを
目的としている。
The present invention was created in view of these circumstances, and
The purpose is to simplify the configuration of electric circuits that require coils.

く課題を解決するための手段〉 本発明は、このような目的を達成するために、次のよう
な構成をとる。
Means for Solving the Problems> In order to achieve the above objects, the present invention has the following configuration.

本発明の半導体装置は、半導体チップと、この半導体装
ノブ上に形成された絶縁膜と、この絶縁膜を介して該半
導体チップ上に積層され該半導体チップの内部素子に電
気的に接続された平面形コイルと、これらをパンケージ
化する外装部材とを具備していることに特徴を有する。
The semiconductor device of the present invention includes a semiconductor chip, an insulating film formed on the semiconductor device knob, and a semiconductor device stacked on the semiconductor chip via the insulating film and electrically connected to internal elements of the semiconductor chip. It is characterized in that it includes a planar coil and an exterior member that makes these into a pancage.

〈作用〉 本発明では、コイルを必要とする電気回路を、−個の部
品としてパッケージ化しているから、その取り扱いが簡
単になるばかりか、実装部位の占有面積が小さくなる。
<Function> In the present invention, since the electric circuit that requires a coil is packaged as a single component, it is not only easy to handle, but also the area occupied by the mounting portion is reduced.

〈実施例〉 以下、本発明の実施例を図面に基づいて詳細に説明する
。第1図ないし第5図に本発明の一実施例を示している
<Example> Hereinafter, an example of the present invention will be described in detail based on the drawings. An embodiment of the present invention is shown in FIGS. 1 to 5.

第1図は半導体装置の縦断側面図、第2図は半導体装置
の要部の平面図である。図中、1は半導体基板に能動素
子や受動素子がプレーナ技術にて形成されてなる半導体
チップ、2は透明フィルムの一面に渦巻きパターンの導
電体が印刷形成されてなる平面形コイル、3は半導体チ
ップ1と平面形コイル2とをパッケージする外装部材と
してのモールド樹脂である。
FIG. 1 is a longitudinal sectional side view of the semiconductor device, and FIG. 2 is a plan view of the main parts of the semiconductor device. In the figure, 1 is a semiconductor chip in which active elements and passive elements are formed on a semiconductor substrate using planar technology, 2 is a planar coil in which a spiral pattern of conductive material is printed on one side of a transparent film, and 3 is a semiconductor. This is a molding resin that serves as an exterior member for packaging the chip 1 and the planar coil 2.

4はリードフレーム4であり、このリードフレーム4の
アイランド部4Aに半導体装ノブlの裏面電極(図示省
略)が接合され、リードフレーム4の端子部4B・・に
半導体チップ1の表面の適当な電極バッドICがボンデ
ィングワイヤ6を介して接続される。
Reference numeral 4 designates a lead frame 4. A back electrode (not shown) of a semiconductor device knob l is bonded to an island portion 4A of the lead frame 4, and an appropriate portion of the surface of the semiconductor chip 1 is connected to a terminal portion 4B of the lead frame 4. Electrode pad ICs are connected via bonding wires 6.

平面形コイル2は、半導体チ・ノブ1の表面上に絶縁膜
5を介して積層され、この平面形コイル2の両端部2A
、2Bが半導体チップ1の適当な電極パッドIA、IB
に電気的に接続されている。
The planar coil 2 is laminated on the surface of the semiconductor chip 1 with an insulating film 5 interposed therebetween, and both ends 2A of the planar coil 2
, 2B are appropriate electrode pads IA, IB of the semiconductor chip 1.
electrically connected to.

このように、本実施例の半導体装置では、半導体装ツブ
1に平面形コイル2を一体化したものをモールド樹脂3
でモールドすることによって、コイルを用いる必要のあ
る電気回路を一個の部品としてパッケージ化している。
In this way, in the semiconductor device of this embodiment, the planar coil 2 is integrated into the semiconductor chip 1 by molding resin 3.
By molding the coil, an electrical circuit that requires the use of a coil is packaged as a single component.

ところで、本実施例の半導体装置は、第3図に示す帯域
除去フィルタや、第4図に示すコルビイノツ発振回路や
、また、第5図に示す微分回路を含む装置として実現で
きる。これらの図に示す電気回路におけるコイルとして
平面形コイル2が利用されるようになっており、他の回
路要素は半導体チップ1に形成される。第3図や第5図
に示すように二つのコイルを用いる場合には、半導体チ
ップ1上に二枚の平面形コイル2を積層することで構成
できる。
Incidentally, the semiconductor device of this embodiment can be realized as a device including the band-rejection filter shown in FIG. 3, the Corby-Inotsu oscillation circuit shown in FIG. 4, and the differential circuit shown in FIG. A planar coil 2 is used as a coil in the electric circuit shown in these figures, and other circuit elements are formed on a semiconductor chip 1. When two coils are used as shown in FIGS. 3 and 5, it can be constructed by stacking two planar coils 2 on the semiconductor chip 1.

なお、本発明は上述した実施例のみに限定されない。例
えば、平面形コイル2は、半導体チップ1を覆う絶縁膜
5上にフォトリソグラフィ技術により形成される渦巻き
パターンのアルミニウム膜とすることができる。また、
半導体チップ1には表面保護用の絶縁膜(図示省略)が
形成されているから、この表面保護用の絶縁膜を上述の
絶縁膜5として利用することもできる。
Note that the present invention is not limited to the embodiments described above. For example, the planar coil 2 can be an aluminum film with a spiral pattern formed on the insulating film 5 covering the semiconductor chip 1 by photolithography. Also,
Since an insulating film for surface protection (not shown) is formed on the semiconductor chip 1, this insulating film for surface protection can also be used as the above-mentioned insulating film 5.

〈発明の効果〉 以上のことから、本発明では、コイルを用いる必要のあ
る電気回路を、外付はコイルを用いない一個のパッケー
ジされた部品とすることができるから、従来に比べて部
品点数及び組付工数を削減できるとともに実装基板にお
ける占有面積も小さくできるなど、小型化と低コスト化
に大きく貢献できる。
<Effects of the Invention> From the above, according to the present invention, an electric circuit that requires the use of a coil can be made into a single packaged component that does not use an external coil, so the number of parts can be reduced compared to the conventional method. In addition to reducing assembly man-hours, the area occupied on the mounting board can also be reduced, making it possible to greatly contribute to downsizing and cost reduction.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第5図は本発明の一実施例に係り、第1図
は半導体装置の縦断側面図、第2図は半導体装置の要部
の平面図、第3図ないし第5図は具体的な回路例を示す
回路図である。
1 to 5 relate to one embodiment of the present invention, in which FIG. 1 is a vertical cross-sectional side view of a semiconductor device, FIG. 2 is a plan view of main parts of the semiconductor device, and FIGS. FIG. 2 is a circuit diagram showing a typical circuit example.

Claims (1)

【特許請求の範囲】[Claims] (1)半導体チップ1と、この半導体チップ1上に形成
された絶縁膜5と、この絶縁膜5を介して該半導体チッ
プ1上に積層され該半導体チップ1の内部素子に電気的
に接続された平面形コイル2と、これらをパッケージ化
する外装部材3とを具備していることを特徴とする半導
体装置。
(1) A semiconductor chip 1; an insulating film 5 formed on the semiconductor chip 1; A semiconductor device comprising a planar coil 2 and an exterior member 3 for packaging these.
JP2312540A 1990-11-16 1990-11-16 Semiconductor device Pending JPH04186667A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2312540A JPH04186667A (en) 1990-11-16 1990-11-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2312540A JPH04186667A (en) 1990-11-16 1990-11-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04186667A true JPH04186667A (en) 1992-07-03

Family

ID=18030457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2312540A Pending JPH04186667A (en) 1990-11-16 1990-11-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04186667A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633785A (en) * 1994-12-30 1997-05-27 University Of Southern California Integrated circuit component package with integral passive component
US5914525A (en) * 1997-06-26 1999-06-22 Innotech Corporation Semiconductor device
JP2008251901A (en) * 2007-03-30 2008-10-16 Fuji Electric Device Technology Co Ltd Composite semiconductor device
JP2011060303A (en) * 1998-02-04 2011-03-24 Gemalto Sa Device with integrated circuit made secure by attenuation of electronic signatures

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633785A (en) * 1994-12-30 1997-05-27 University Of Southern California Integrated circuit component package with integral passive component
US5914525A (en) * 1997-06-26 1999-06-22 Innotech Corporation Semiconductor device
JP2011060303A (en) * 1998-02-04 2011-03-24 Gemalto Sa Device with integrated circuit made secure by attenuation of electronic signatures
JP2008251901A (en) * 2007-03-30 2008-10-16 Fuji Electric Device Technology Co Ltd Composite semiconductor device

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