JPH04192353A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPH04192353A JPH04192353A JP2317755A JP31775590A JPH04192353A JP H04192353 A JPH04192353 A JP H04192353A JP 2317755 A JP2317755 A JP 2317755A JP 31775590 A JP31775590 A JP 31775590A JP H04192353 A JPH04192353 A JP H04192353A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- terminals
- capacitor
- integrated circuit
- distance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims description 3
- 239000012778 molding material Substances 0.000 claims description 3
- 241000272168 Laridae Species 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 1
- 239000000919 ceramic Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子機器に用いるプリント配線基板上に実装
するＩＣ−ＬＳＩのビン配列、及び、その構造に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bin arrangement of IC-LSIs mounted on a printed wiring board used in electronic equipment and its structure.
従来のＬＳＩは、日立８／１６ビツトマイクロコンピユ
一タ周辺ＬＳＩデータブック（８９年９月発行）Ｋ記載
されているように、ＡＧＮＤ１端子（５０番ビン）とＧ
ＯＭＰ端子（５７番ピン）間には電気容量を接続するこ
とになっているにも係らず二端子は離れて配置されてお
シ、また、バイパスコンデンサを最短距離に接続する必
要のある電源、グランド端子間も離れて配置されている
。Conventional LSIs have an AGND1 terminal (bin 50) and a G
Even though a capacitor is supposed to be connected between the OMP terminals (pin 57), the two terminals are placed far apart, and the power supply requires that the bypass capacitor be connected at the shortest distance. The ground terminals are also spaced apart.
上記従来技術は、特定の電気容量を端子間に必要として
いるにも係らす端子が離れて＾るため、プリント配線基
板上に配線が必要であ）、個別部品を使用するため、プ
リント基板組立部品の点数が増加し、工数が多い丸め装
造原価も高く、実装密度が低下し、電源端子とグランド
膚子が離れているため、バイパスコンデンサを近い距離
に配置する限界があｆｉ、ＬＳＩのスイッチング速度が
高速化すると、電源・グランド間ノイズをおさえる事が
できなくなるという問題があった。In the above conventional technology, since the terminals are separated even though a specific capacitance is required between the terminals, wiring is required on the printed wiring board), and because individual parts are used, it is difficult to assemble the printed circuit board. The number of parts increases, the number of man-hours increases, the cost of rounding increases, the packaging density decreases, and the distance between the power supply terminal and the ground plane limits the ability to place bypass capacitors close together. As the switching speed increases, there is a problem in that it becomes impossible to suppress noise between the power supply and ground.
本発明の目的は、個別部品であるコンデンサをＬＳＩと
の最短距離に配置し、実装の高密度化を図ることＫあ）
、さらに、高速スイッチング動作でも、電源・グランド
間ノイズ発生の少ないＬＳＩを提供することにある。The purpose of the present invention is to arrange a capacitor, which is an individual component, at the shortest distance from the LSI to achieve higher mounting density.Ka)
Furthermore, it is an object of the present invention to provide an LSI that generates less noise between the power supply and the ground even during high-speed switching operation.
上記目的を達成する九め尤、本発明は電気容量を設ける
必要のある二電子を隣接して配列する手段と、最短距離
に配置する必要のあるコンデンサをＩＣ−ＬＳＩパッケ
ージ内に内蔵したものである。In order to achieve the above object, the present invention incorporates a means for arranging two electrons adjacent to each other, which require capacitance, and a capacitor, which must be arranged at the shortest distance, in an IC-LSI package. be.
〔作用〕
電気容量を設ける必要のある二層子を隣接して配列する
ことにより、最短配線もしくは配線なしでコンデンサ金
接続することができるために、プリント基板の高密度実
装を実現できる。また、隣接しているためにＩＣパッケ
ージ内にコンデンサを内蔵することも容易となる。その
ようにコンデンサをＩ Ｃハラケージ内に内蔵すること
によ）スイッチング素子と、そのスイッチング動作電流
を補充するコンデンサとの距離が近づく丸め、高速スイ
ッチング動作時の電源・グランド間ノイズを低減するこ
とができる。[Function] By arranging two-layer devices that require capacitance adjacent to each other, it is possible to connect the capacitors with the shortest wiring or without wiring, thereby realizing high-density mounting of printed circuit boards. Furthermore, since they are adjacent to each other, it is easy to incorporate the capacitor into the IC package. By incorporating a capacitor in the IC cage in this way, the distance between the switching element and the capacitor that supplements the switching operation current becomes closer, reducing noise between the power supply and ground during high-speed switching operation. can.
以下、本発明の実施例を第１図から第４図を用いて説明
する。Embodiments of the present invention will be described below with reference to FIGS. 1 to 4.
第１図は、本発明の一実施例のＩＣの斜視図であり、図
中、１はＩＣ本体、２はＩＣチップ、５はボンディング
ワイヤ、４はビン、５はエポキシレジン等のモールド材
料、６はチップコンデンサである。４−１ビンと４−２
ビンの間に、例えば、位相補償用のコンデンサを接続す
る必要がある丸め、とのニビンを隣接して配列すること
によシモールド材料５内のピンチ上にチップ型のコンデ
ンサを配置することが可能となる。チップ型部品は、３
２１６タイプさら２０１２タイプへ、さらに：１６０８
タイプへと小製化が進み、ＩＣ内に配置する事が可能な
大きさになってきつつある。第１図ではＦｌ接するビン
の組は一つしか記していないが、同−ＩＣ内には細組存
在してもよい。チップコンデンサ６も、−個のみ記しで
あるが、−組の隣接するビンの組に何個搭載してもよい
。この様だ、電気容量を設ける事が必要なニピンを隣接
配量する事によ）、チップ型部品の内部搭載を容易とし
、かつ、動作素子（ＩＣチップ２）に近接して配置する
ことが可能となる。さらに、このことは、プリント基板
組立部品の部品点数全削減し、プリント基板上の余分な
配線パターン管削除することかで惠るので、高密度実装
に寄与する。FIG. 1 is a perspective view of an IC according to an embodiment of the present invention, in which 1 is an IC main body, 2 is an IC chip, 5 is a bonding wire, 4 is a bottle, 5 is a molding material such as epoxy resin, 6 is a chip capacitor. 4-1 bin and 4-2
Between the bins, it is possible to place chip-type capacitors on the pinch in the simold material 5 by arranging the nibins next to each other with a round, where it is necessary to connect a capacitor for phase compensation, for example. becomes. Chip type parts are 3
216 type further to 2012 type, further: 1608
The size of semiconductor devices is becoming smaller and smaller, allowing them to be placed inside ICs. Although only one set of bins adjacent to Fl is shown in FIG. 1, sub-sets may exist within the same IC. Although only - pieces of chip capacitors 6 are shown, any number of chip capacitors 6 may be mounted in the - set of adjacent bins. In this way, by arranging the pins adjacent to each other, which require capacitance, it is possible to easily mount chip-type components internally and to place them close to the operating element (IC chip 2). It becomes possible. Furthermore, this contributes to high-density packaging because it reduces the total number of parts in the printed circuit board assembly and eliminates redundant wiring pattern tubes on the printed circuit board.
第２図は、ＸＣの他Ｏ実施例の斜視図であシ、図中の符
号は第１図で用いたものと同じである。FIG. 2 is a perspective view of another O embodiment of the XC, and the reference numerals in the figure are the same as those used in FIG. 1.
第１図と同様ビン４−１とビン４−２の間には電気容量
を設ける必要があシ、隣接して配列しである。ＩＣパッ
ケージのモールド材料５の最外部付近は、強度・密べい
度の問題等からチップコンデンサ６の配置は制限される
丸め、容量、耐圧の大きな、内蔵不可能な大きさのチッ
プコンデンサ６を、ガルウィング型のビン４の水平部分
に搭載する。この場合、チップコンデンサ乙の電極外形
寸法は、以下の範囲にとどめる必要があり、この事が特
徴と表る。チップコンデンサ６の電極間の最小距離は、
ビン４−１とビン４−２の向かい合った内側の距離以上
であ）、電極の最外側間距離は、ビン４−１とビン４−
２の向か匹合った外側の距離以内である。また、はんだ
付は後の検査の都合上、ビン４の上に搭載したくない場
合は、ビン４−１とビン４−２から、その延長上に引い
たプリント基板上のパタンの上のりフローパッド上に配
置しても、パターン長は最短にする事ができる。As in FIG. 1, it is necessary to provide an electric capacity between the bins 4-1 and 4-2, and they are arranged adjacent to each other. Near the outermost part of the molding material 5 of the IC package, the placement of the chip capacitor 6 is limited due to issues such as strength and density, and a chip capacitor 6 with a large capacity and withstand voltage that cannot be built in is placed. , mounted on the horizontal part of the gull wing type bin 4. In this case, the external dimensions of the electrodes of the chip capacitor B must be kept within the following range, and this is a feature. The minimum distance between the electrodes of the chip capacitor 6 is
The distance between the outermost electrodes is equal to or greater than the distance between the opposing inner sides of the bins 4-1 and 4-2), and the distance between the outermost electrodes is
It is within the distance between the opposite sides of the two. In addition, if you do not want to solder on top of Bin 4 for later inspection reasons, please refer to the soldering flow of the pattern on the printed circuit board drawn from Bin 4-1 and Bin 4-2 on their extension. Even when placed on a pad, the pattern length can be minimized.
第５図は、本発明の一実施例のＩＣの断面図である。図
中、第１図と同一符号のものは、第１図と同じ名称でち
ゃ、７は絶縁材、８はグランド電極、９は絶縁誘電材、
１０は電源電極、１１は導体であシ、１１−１はビン４
−１と電源電極１０を接続する導体であシ、他とは絶縁
されている、１１−２はビン４−２とグランド電極８を
接続するものである。このように、ＩＣ本体１の内部下
部に、平板電極をもち、静電容量を確保する事によ）、
バイパスコンデンサの最短距離配置が可能となる。この
場合、コンデンサの必要なビン４を隣接して配列する必
要はない。FIG. 5 is a sectional view of an IC according to an embodiment of the present invention. In the figure, the same numbers as in Figure 1 have the same names as in Figure 1, 7 is an insulating material, 8 is a ground electrode, 9 is an insulating dielectric material,
10 is a power supply electrode, 11 is a conductor, 11-1 is a bottle 4
A conductor 11-2 connects the pin 4-2 and the ground electrode 8, and is insulated from the others. In this way, by having a flat plate electrode at the inner lower part of the IC body 1 to ensure capacitance),
This allows bypass capacitors to be placed at the shortest distance. In this case, it is not necessary to arrange the bins 4 that require capacitors adjacently.
第４因はＩＣ内部に構成するコンデンサの平面及び側面
図である。電気容量を設ける必要のあるビン４−１と４
−２を隣接させ、幅を大きく広げて上下に重ね、その間
に絶縁誘電材９を挿入して必要な電気容量が得られる。The fourth factor is a plan view and a side view of a capacitor configured inside the IC. Bins 4-1 and 4 that require electrical capacity
-2 are placed adjacent to each other, the widths are greatly expanded, and the insulating dielectric material 9 is inserted between them to obtain the necessary capacitance.
この様な方法により、ｆｃ内部にコンデンサを持つこと
により、プリント基板組立部品点数の削減、高速スイッ
チング素子の電源グランド間ノイズＯ低減等の効果があ
る。By having a capacitor inside fc, such a method has effects such as reducing the number of printed circuit board assembly parts and reducing noise O between the power source and ground of high-speed switching elements.
本発明だよれば、ＩＣとＩＣＫ必要なコンデンサを同一
モールド内に収納するので、プリント基板組立部品点数
の減少だよる工数の削減及び、実装面積の減少に二る装
置の小型化・扁密度実装化の効果がある。According to the present invention, since the IC and the capacitors required for the ICK are housed in the same mold, the number of printed circuit board assembly parts is reduced, thereby reducing man-hours, and the mounting area is reduced, resulting in device miniaturization and density mounting. It has the effect of
また、バイパスコンデンサをＩＣ内部に持つためＩＣチ
ップとバイパスコンデンサの距離を短縮することができ
るため、高速スイッチングＩＣの電源・グランド間ノイ
ズの低減が可能とな）、高速スイッチングＩＣの利用が
容易となる。In addition, since the bypass capacitor is inside the IC, the distance between the IC chip and the bypass capacitor can be shortened, making it possible to reduce noise between the power supply and ground of high-speed switching ICs), making it easier to use high-speed switching ICs. Become.
第１図は本発明の一実施例のＩＣの斜視図、菖２図はＩ
Ｃ他の実施例の斜視図、第Ｓ図は本発明のＩＣの断面図
、第４図はＩＣ内部に構成するコンデンサの平面図（ａ
）及び側面図（ｂ）である。
１°・・ＩＣ本体、２・・・ＩＣチップ、３・・・ホン
ディングワイヤ、４・・・ビン、５・・・モールド材料
、６・・・チップコンデンサ、７・・・絶縁材、ａ・・
・グランド電極、９・・・絶縁誘電材、１０・・・電源
電極、１１・・・導体。
一ヲ＝−二二ン２、
一二二、Ｆ：ｔ、７Figure 1 is a perspective view of an IC according to an embodiment of the present invention, and Figure 2 is an I
Figure C is a perspective view of another embodiment, Figure S is a sectional view of the IC of the present invention, and Figure 4 is a plan view (a
) and a side view (b). 1°...IC body, 2...IC chip, 3...Honding wire, 4...Bin, 5...Mold material, 6...Chip capacitor, 7...Insulating material, a・・・
- Ground electrode, 9... Insulating dielectric material, 10... Power supply electrode, 11... Conductor. 1 = -22 in 2, 122, F:t, 7
Claims (1)
プをプラスチックやセラミックでモールドしその外に電
気的端子を持つＩＣにおいて、モールド材料の中にコン
デンサを内蔵することを特徴とする集積回路。 ２、二本の端子間に所望の電気容量を持つ必要のある端
子を備えたＩＣにおいて、 前記端子の組を隣接して配置することを特徴とする集積
回路。 ３、電極間距離がＩＣの二端子内側距離以上で、前記電
極の最外側がＩＣの二端子外側距離以内で、かつ、前記
電極の幅がＩＣのガルウィング型端子の水平部分以内で
あることを特徴とするチップ型コンデンサ。 ４、ＩＣのガルウィング型端子の水平部分の上部にチッ
プ型部品をはんだ付けにより搭載することを特徴とする
電気部品実装方式。[Claims] 1. An IC in which an integrated circuit chip made of silicon, gallium arsenide, etc. is molded with plastic or ceramic and has electrical terminals on the outside, characterized in that a capacitor is built into the molding material. integrated circuit. 2. An integrated circuit comprising terminals that need to have a desired capacitance between the two terminals, characterized in that a set of the terminals are arranged adjacent to each other. 3. Make sure that the distance between the electrodes is greater than or equal to the inner distance between the two terminals of the IC, the outermost part of the electrode is within the outer distance of the two terminals of the IC, and the width of the electrode is within the horizontal part of the gull wing terminal of the IC. Features of chip-type capacitors. 4. An electrical component mounting method characterized by mounting chip-type components on the top of the horizontal portion of the gull-wing terminal of an IC by soldering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2317755A JPH04192353A (en) | 1990-11-26 | 1990-11-26 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2317755A JPH04192353A (en) | 1990-11-26 | 1990-11-26 | Integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04192353A true JPH04192353A (en) | 1992-07-10 |
Family
ID=18091680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2317755A Pending JPH04192353A (en) | 1990-11-26 | 1990-11-26 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04192353A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990029740A (en) * | 1997-09-18 | 1999-04-26 | 갈라스 윌리엄 이 | Improved RF Electronics Package |
| JP2006278355A (en) * | 2005-03-25 | 2006-10-12 | Nec Corp | Assembly structure and manufacturing method of integrated circuit package |
-
1990
- 1990-11-26 JP JP2317755A patent/JPH04192353A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990029740A (en) * | 1997-09-18 | 1999-04-26 | 갈라스 윌리엄 이 | Improved RF Electronics Package |
| JP2006278355A (en) * | 2005-03-25 | 2006-10-12 | Nec Corp | Assembly structure and manufacturing method of integrated circuit package |
| JP4701779B2 (en) * | 2005-03-25 | 2011-06-15 | 日本電気株式会社 | Integrated circuit package assembly structure |
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