JP4701779B2 - Integrated circuit package assembly structure - Google Patents

Description

This invention relates to an integrated circuit package assembly structure and, more particularly, to the integrated circuit package assembly structure adapted to implement a combination of the integrated circuit and the peripheral components on the circuit board.

  As integrated circuits represented by LSI (Large Scale Integrated circuit) become multifunctional, these integrated circuits are incorporated in various electronic devices such as mobile phones and personal computers. These electronic devices are required to be reduced in size and weight of the entire device, and in particular, cellular phones are required to improve portability in addition to them. Here, the integrated circuit is mounted on a common circuit board in combination with peripheral components as small surface mounting components such as a bypass capacitor and a resistor. In order to satisfy the required conditions as described above, it is necessary to reduce the size, weight, and thickness of the integrated circuit to be used and the peripheral components themselves, and to reduce the mounting area. .

  For this reason, the integrated circuit and peripheral components used are competing to reduce the size of the component members to less than 0.1 mm for miniaturization. Recently, small size surface mount parts such as bypass capacitors and resistors have become the mainstream in the size of 1.0 mm x 0.5 mm, but there are also smaller ones of 0.6 mm x 0.3 mm. Has appeared. On the other hand, in an integrated circuit, great efforts are made to invest tens of millions of yen in order to reduce the size of 0.1 mm.

  FIG. 10 shows a concept of a conventional integrated circuit package assembly structure in which an integrated circuit and peripheral components are mounted on a circuit board. FIG. 10A is a perspective view showing a configuration before mounting peripheral components, and FIG. This is a configuration after peripheral components are mounted. Conventionally, first, as shown in FIG. 10A, a BGA (Ball Grid Array) package 104 as an integrated circuit is mounted on a common circuit substrate 103 having wirings 101 and lands 102 previously formed on the surface. Next, as shown in FIG. 10B, a chip-type bypass capacitor 105, for example, is mounted as a peripheral component so that both terminals thereof are connected to both lands 102 and attached externally. Here, the BGA package 104 is used as an example of an integrated circuit that is excellent in terms of mounting area, and the chip-type bypass capacitor 105 is also used by taking advantage of being excellent as a small surface mounting component.

However, in the conventional integrated circuit package assembly structure shown in FIG. 10, since the wiring 101 is formed between the BGA package 104 and the bypass capacitor 105, this portion becomes a useless space. That is, if a bypass capacitor 105 having a size of, for example, 1.0 mm × 0.5 mm is used as a peripheral component, the mounting area of the bypass capacitor 105 in this case is 0.5 mm ² , but wasted due to the wiring 101 as described above. If there is a large space, the substantial mounting area becomes many times that of the bypass capacitor 105, which is a peripheral component, so that it is impossible to reduce the mounting area of the integrated circuit package assembly structure.

In the conventional integrated circuit package assembly structure shown in FIG. 10, since complicated wiring including invisible wiring 101 ′ is formed in the circuit board 103 immediately below the BGA package 104, The wiring path to the bypass capacitor 105 becomes long, and the efficiency of wiring on the circuit board 103 cannot be achieved. As described above, when the wiring path of the bypass capacitor 105 as a peripheral component becomes long, the bypass capacitor 105 used for reducing power supply noise becomes far from the power supply, so that the function as the bypass capacitor is lowered.
As described above, it becomes difficult to reduce the mounting area, and when the wiring path becomes longer, the size of the circuit board becomes larger, and thus the cost reduction cannot be avoided.

  For example, Patent Document 1 discloses an integrated circuit package three-dimensional assembly structure in which a plurality of integrated circuit packages are combined and connected to each other in the upper surface direction, the bottom surface direction, and the side surface direction to shorten the bonding distance between them. ing. In the integrated circuit package three-dimensional assembly structure, as shown in FIG. 11, the integrated circuit packages 160, 162, 164, 166, 168, 170, 172, 174, 176, 178, 180, and 182 are three-dimensionally arranged on the circuit board 100. In this assembly method, the upper surface 140 and the bottom surface 142 are stacked in the direction and the side surface 144 is bonded in parallel. Taking the integrated circuit package 168 as an example, the upper joint surface 146 is connected to the integrated circuit package 174 in the upper surface direction 140, the bottom joint surface 148 is connected to the integrated circuit package 162 in the bottom surface direction 142, and the side joint surface thereof. 150 is connected to the integrated circuit packages 166 and 170 in the direction of the side surface 144.

Further, for example, Patent Document 2 discloses a semiconductor package in which a terminating resistor or a bypass capacitor is mounted on a metal pad provided on a side surface of the semiconductor package so as to reduce a mounting area. In addition, a BGA package in which a bypass capacitor is soldered to the half-through electrode on the peripheral side surface of the BGA package substrate and the electrical characteristics are modified using the half-through electrode when there is a soldering failure, For example, it is disclosed in Patent Document 3.
Utility Model Registration No. 3064379 JP-A 63-147355 Japanese Patent No. 3447908

By the way, the conventional techniques described in Patent Documents 1 to 3 have problems as described below.
First, in the conventional integrated circuit package three-dimensional assembly structure described in Patent Document 1, a plurality of integrated circuit packages 160, 162, 164, 166, 168, 170, 172, 174, 176, 178, 180 are provided as shown in FIG. , 182 are connected to each other by a three-dimensional assembly method. However, it is effective to reduce the joint distance between them, but not only in the direction of the side surface 144 but also in the direction of the top surface 140 and the bottom surface 142, Since the packages are stacked, it becomes a big bottleneck in the case of reducing the thickness especially in order to improve portability like the mobile phone as described above.

  Next, in the semiconductor package described in Patent Document 2, since the metal pads are provided on the side surfaces after the semiconductor package is completed, the number of manufacturing processes increases, and the cost increase cannot be avoided. Further, in the BGA package described in Patent Document 3, since it is necessary to form a constricted portion in a part of the half-through electrode in order to remodel the electrical characteristics, the electrode shape becomes complicated and a defect caused by this electrode shape Therefore, the reliability of the semiconductor package decreases. Further, in this semiconductor package, measures against soldering defects are taken, and no consideration is given to the thinning of the BGA package.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances. A semiconductor package assembly that realizes a reduction in thickness and can previously provide peripheral component connection electrodes having a simple structure in the side surface direction of the semiconductor package. Its purpose is to provide a structure .

In order to solve the above problems, an invention according to claim 1 relates to an integrated circuit package assembly structure in which an integrated circuit and peripheral components are combined and mounted on a circuit board, and an electrode is a package of the integrated circuit. The electrode is provided in such a manner that it is in surface contact with the side surface of the integrated circuit, and the electrode is bent outwardly from the bottom edge of the side surface of the package of the integrated circuit in a mode of surface contact with the surface of the circuit board on which the integrated circuit is mounted. The peripheral part extends beyond the height of the package into a first portion of the electrode that extends and makes surface contact with the side surface of the package and a second portion of the electrode that makes surface contact with the circuit board surface It is characterized by electrical connection without any disposition .

According to the integrated circuit package assembly structure of the present invention, peripheral parts such as a bypass capacitor are placed on a simple land previously provided on the side surface of the integrated circuit package so as not to exceed the height of the integrated circuit package. The thickness in the height direction does not increase. Further, since the land is provided on the side surface at the same time as the integrated circuit package is completed, the manufacturing process is not increased, and the cost increase can be avoided. Further, since the land shape is simple, it is difficult for defects to occur, so that the reliability of the integrated circuit package does not deteriorate.
Further, according to the method of manufacturing an integrated circuit package of the present invention, the land can be easily provided simultaneously with the manufacture of the integrated circuit package.

The integrated circuit package assembly structure 10 has a configuration in which a BGA package 2 and a bypass capacitor 3 are combined and mounted on a circuit board 1, and a land 4 is provided on a side surface 2S of the BGA package 2. 3 are electrically connected so as not to exceed the height of the BGA package 2.
Further, in the semiconductor package manufacturing method, the metal member 8 is disposed in the space between the plurality of LSI chips 6 and 7 in advance and the whole is packaged by the sealing body 12, and then sealed along the length direction of the metal member 8. The BGA package 2 in which the metal member 8 is exposed by cutting the stopper 12 and separating the plurality of LSI chips 6 and 7 and the land 4 is provided on the side surface 2S is manufactured.

1 is a perspective view showing an integrated circuit package assembly structure according to Embodiment 1 of the present invention, FIG. 2 is an enlarged view of a main part A of the integrated circuit package assembly structure, and FIG. The perspective view which shows the structure of (b) is a perspective view which shows the structure after mounting a peripheral component.
In the integrated circuit package assembly structure 10 of this example, as shown in FIG. 1, a BGA package 2 as an integrated circuit is mounted on a circuit board 1 made of plastic, ceramic or the like. A chip-type bypass capacitor 3, for example, is electrically connected as a component. Here, the BGA package 2 is used as an example of an integrated circuit which is excellent in terms of mounting area, and the bypass capacitor 3 is used taking advantage of being excellent as a small surface mounting component. Further, as is well known in this technical field, the BGA package 2 has a plurality of ball electrodes (not shown) provided in advance on the back surface thereof electrically connected to wiring (not shown) provided in advance on the circuit board 1. Thus, it is mounted on the circuit board 1.

  The BGA package 2 has a height 2h of 1.0 mm, for example, and the side surface 2S has a height 4h made of a conductor of 0.5 mm and a width 4w of 0.25 mm, as shown in FIG. A pair of rectangular lands 4 are provided as peripheral component connecting electrodes. These lands 4 are electrically connected to corresponding terminals of the integrated circuit through wiring (not shown) in the BGA package 2. As an example, the land 4 shows only a pair for connecting one bypass capacitor. The BGA package 2 including the land 4 is manufactured by a manufacturing method as described later.

  As shown in FIG. 2B, the bypass capacitor 3 is, for example, a chip-shaped chip having a height 3h of 0.3 mm, a length 3l of 1.0 mm, and a width 3w of 0.5 mm. Electrodes 5 having a width 5w of 0.5 mm and a length 5l of 0.25 mm are provided at both ends of the bypass capacitor 3 along the length 31 direction. The bypass capacitor 3 is electrically connected as shown in FIG. 2B by soldering the electrodes 5 to the lands 4. Here, the bypass capacitor 3 is arranged so that the width 3w (0.5 mm) direction coincides with the height 2h (1.0 mm) direction of the BGA package 2, and as a result, the bypass capacitor 3 has a height of the BGA package 2. Arranged so as not to exceed. Therefore, it is possible to reduce the thickness of the BGA package 2 to which the bypass capacitor 3 as a peripheral component is electrically connected.

Next, with reference to FIGS. 3A to 3C, a method for manufacturing the BGA package 2 used in Example 1 will be described in the order of steps.
First, as shown in FIG. 3A, a first group of chips C1 in which a plurality of LSI chips 6 (6a, 6b, 6c) having desired functions are arranged in the height direction, and other functions are provided. A plurality of LSI chips 7 (7a, 7b, 7c) having a second group of chip groups C2 arranged in the height direction are arranged in a plane direction, and the first and second groups of chip groups C1, C2 are arranged. A plurality of metal members 8 to be lands are arranged in the space between them. Next, a desired terminal (not shown) of a desired LSI chip (for example, 6b) of the chip group C1 of the first group is electrically connected to a corresponding metal member 8 by a signal line (wiring) 9, and the like. Then, a desired terminal (not shown) of a desired LSI chip (for example, 7c) of the chip group C2 of the second group is electrically connected to the corresponding metal member 8 by a signal line (wiring) 11.

  Next, as shown in FIG. 3B, the whole including the LSI chips 6a to 6c and 7a to 7c, the metal member 8, and the wirings 9 and 11 of the chip groups C1 and C2 of the first and second groups. For example, a resin such as an epoxy resin is poured by the transfer mold method and packaged by the sealing body 12.

  Next, as shown in FIG. 3C, the sealing body 12 is cut along the length direction of the metal member 8 with a diamond cutter or the like, and the first group of the chip group C1 and the second group of the second group. By separating the chip group C2, the metal member 8 is exposed and the land 4 is formed. Thus, the BGA package 2 is completed. A plurality of ball-like electrodes (not shown) are formed on the back surface of the BGA package 2, but such electrode forming techniques are well known in the art and are not directly related to the present invention. The explanation is omitted because it is a technology. Then, as shown in FIG. 1, the bypass capacitor 3 as a peripheral component is electrically connected to the land 4 on the side surface 2S of the BGA package 2 by soldering, so that the integrated circuit package assembly structure 10 of this example is obtained. Finalize.

  According to the integrated circuit package assembly structure 10 as described above, the bypass capacitor 3 is electrically disposed in the land 4 having a simple shape provided in advance on the side surface 2S of the BGA package 2 so as not to exceed the height of the BGA package. Since the connection is made, the thickness in the height direction does not increase. In addition, since the land 4 is provided on the side surface 2S simultaneously with the completion of the BGA package 2, the manufacturing process does not increase, and an increase in cost can be avoided. Further, since the shape of the land 4 is simple, it is difficult for defects to occur, so that the reliability of the BGA package 2 is not lowered.

As described above, according to the integrated circuit package assembly structure 10 of this example, in the configuration in which the BGA package 2 and the bypass capacitor 3 are combined and mounted on the circuit board 1, the land 4 is formed on the side surface 2S of the BGA package 2. Since the bypass capacitor 3 is electrically connected to the land 4 so as not to exceed the height of the BGA package 2, the thickness of the BGA package 2 in the height direction can be reduced.
Further, according to the semiconductor package manufacturing method of this example, after the metal member 8 is disposed in advance in the space between the plurality of LSI chips 6 and 7 and the whole is packaged by the sealing body 12, the length of the metal member 8 is increased. By cutting the sealing body 12 along the direction and separating the plurality of LSI chips 6 and 7, the metal member 8 is exposed, and the BGA package 2 having the land 4 on the side surface 2S is manufactured. The land 4 can be provided simultaneously with the manufacture of the BGA package 2.
Therefore, it is possible to reduce the thickness and to provide peripheral component connection electrodes having a simple structure in the side surface direction of the semiconductor package in advance.

4 is an enlarged view of the main part of an integrated circuit package assembly structure according to Embodiment 2 of the present invention. FIG. 4 (a) is a perspective view showing a configuration before mounting peripheral components, and FIG. 4 (b) shows peripheral components. It is a side view which shows the structure after mounting. The structure of the integrated circuit package assembly structure of this example is greatly different from that of the first embodiment described above, in that lands for connecting peripheral parts are provided extending from the side surface of the integrated circuit package to the circuit board. It is.
In the integrated circuit package assembly structure 15 of this example, as shown in FIG. 4A, a BGA package 2 as an integrated circuit is mounted on a circuit board 1 made of plastic, ceramic or the like, and a side surface 2S of this BGA package 2 is mounted. A pair of rectangular lands 4 made of a conductor and having a height 4h of 0.5 mm and a width 4w of 0.25 mm are provided as peripheral component connection electrodes. Further, a pair of rectangular reinforcing lands 13 having a length 13 l of 0.4 mm and a width 13 w of 0.25 mm are provided on the circuit board 1 as reinforcing electrodes so as to be in contact with the lands 4.

The bypass capacitor 3 is electrically connected as shown in FIG. 4B by soldering the electrodes 5 to the lands 4 and 13, respectively. Here, the bypass capacitor 3 is arranged so that the width 3w (0.5 mm) direction coincides with the height 2h (1.0 mm) direction of the BGA package 2, and the bypass capacitor 3 is the BGA package as in the first embodiment. It is arranged not to exceed the height of 2. Therefore, it is possible to reduce the thickness of the BGA package 2 to which the bypass capacitor 3 as a peripheral component is electrically connected. Further, in this example, since the reinforcing land 13 is provided in contact with the land 4, an effect that the connection strength of the bypass capacitor 3 can be increased can be obtained.
Other than this, the configuration is substantially the same as the configuration of the first embodiment described above. Therefore, in FIG. 4, each component corresponding to the configuration of FIGS.

  As described above, the configuration of this example can provide substantially the same effect as that of the first embodiment, and can also obtain the effect of increasing the connection strength of peripheral components.

5A and 5B show an integrated circuit package assembly structure that is Embodiment 3 of this example, where FIG. 5A is a perspective view showing a configuration before mounting peripheral components, and FIG. 5B shows a configuration after mounting peripheral components. It is a perspective view shown. The configuration of the integrated circuit package assembly structure of this example is greatly different from that of the first embodiment described above in that when a plurality of pairs of lands are provided, common lands are provided adjacent to each other.
In the integrated circuit package assembly structure 20 of this example, as shown in FIG. 5A, a BGA package 2 as an integrated circuit is mounted on a circuit board 1 made of plastic, ceramic or the like, and a side surface 2S of the BGA package 2 is mounted. Are provided with two pairs of lands 14 and 16 having a rectangular shape with conductor heights 14h and 16h of 0.5 mm, widths 14w and 16w of 0.25 mm, as peripheral component connection electrodes. , 16 are GND (ground) lands 14E, 16E which are common electrodes.

  The pair of bypass capacitors 3 are electrically connected as shown in FIG. 5B by soldering the GND electrode 5E of the electrodes 5 to the GND electrodes 14E and 16E, respectively. Here, each bypass capacitor 3 is arranged so that the width 3w (0.5 mm) direction coincides with the height 2h (1.0 mm) direction of the BGA package 2 as in the first embodiment. Arranged so as not to exceed the height of the BGA package 2. Therefore, it is possible to reduce the thickness of the BGA package 2 to which the bypass capacitor 3 as a peripheral component is electrically connected. In this example, since the GND lands 14E and 16E, which are common electrodes of the two pairs of lands 14 and 16, are provided adjacent to each other, the pair of bypass capacitors 3 and the GND electrodes 5E are back to back. Since it is possible to connect in a simple arrangement and to reduce the dead space when connecting a large number of peripheral parts, it is possible to obtain an effect that the mounting area in the side surface 2S direction of the BGA package 2 can be reduced.

  Thus, the configuration of this example can provide substantially the same effect as that of the first embodiment, and in addition, the effect that the mounting area in the side surface direction of the package can be reduced.

6 is a perspective view showing an integrated circuit package assembly structure according to Embodiment 4 of the present invention, FIG. 7A is an enlarged top view showing a main part B of FIG. 6, and FIG. 7B is FIG. FIG. 8 is a perspective view showing a comparative example. FIG. The configuration of the integrated circuit package assembly structure of this example is greatly different from that of the above-described first embodiment. As an example of the integrated circuit, an SOP (Small Out-line Package: SO package) is used instead of the BGA package. Is a point.
In the integrated circuit package assembly structure 25 of this example, as shown in FIGS. 6, 7A and 7B, an SOP 17 as an integrated circuit is mounted on a circuit board 1 made of plastic, ceramic or the like. Leads 18 are drawn out from both side surfaces 17S of the same, and a bypass capacitor 3 is electrically connected as a peripheral component to a tip portion 18T of the lead 18 in contact with the circuit board 1. Here, the SOP 17 is used as an example of an integrated circuit that is excellent in terms of mounting area like the BGA package, and the bypass capacitor 3 is used taking advantage of being excellent as a small surface mounting component. A tip portion 18T of the lead 18 of the SOP 17 is connected to a wiring (not shown) in the circuit board 1.

  For example, in the case of TSSOP (Thin Shrink SOP) which is a kind of SOP, the length of the lead 18 is about 1.0 mm, and the length of the tip portion 18T is about 0.5 mm. By using it, the bypass capacitor 3 can be soldered without protruding from the tip end portion 18T of the lead 18. Therefore, the bypass capacitor 3 can be connected without occupying extra space on the circuit board 1. Moreover, solderability can be improved by processing the front-end | tip part 18T flatly as needed.

  In the conventional integrated circuit package assembly structure corresponding to this example, as shown in FIG. 8, since the wiring 106 is required between the lead 118 from the SOP 117 and the bypass capacitor 105, this portion becomes useless space. Therefore, it becomes impossible to reduce the mounting area of the integrated circuit package assembly structure.

  Further, since the leads 18 are arranged with a pitch of 0.4 mm, as shown in FIGS. 7A and 7B, the leads 18A, 18B, 18C, 18D... A bypass capacitor 3 can be connected between 18B and 18D. In this case, by insulating the portions other than the electrodes 5 of the bypass capacitor 3, the insulation of the bypass capacitor 3 with respect to the lead 18 </ b> C can be made complete. With such a lead arrangement, the lead 18B can be used as a power supply line, the lead 18C as a control signal line, and the lead 18D as a ground line. Also, by insulating the slopes of the leads 18B and 18D, the solder can be limited only to the flat portions of the leads 18B and 18D during soldering, and the mounting yield can be improved. Furthermore, since there are gaps between the leads 18B and 18C and between the leads 18C and 18D, the effect of improving heat dissipation can also be obtained.

  As described above, the configuration of this example can provide substantially the same effect as that of the first embodiment. In addition, the mounting yield can be improved and the heat dissipation can be improved. .

FIG. 9 is a side view showing an integrated circuit package assembly structure according to Embodiment 5 of the present invention. The configuration of the integrated circuit package assembly structure of this example is greatly different from that of the above-described fourth embodiment in that peripheral components having a size matching the pitch of the SOP leads are connected.
In the integrated circuit package assembly structure 30 of this example, as shown in FIG. 9, an SOP 19 as an integrated circuit is mounted on a circuit board 1 made of plastic, ceramic or the like, and the leads 19 drawn out from both side surfaces of the SOP 17 are mounted. Bypass capacitors 22 having sizes adapted to various pitches are electrically connected.

  For example, as shown in FIG. 9, if a plurality of leads 21A, 21B, 21C, 21D, 21E... Are drawn from the SOP 19 at an arbitrary pitch, for example, the electrode 23 is soldered between the leads 21A, 21E. A bypass capacitor 22 is connected. By connecting the bypass capacitor 22 sized according to the lead pitch in this way, it is freed from the restriction that only a bypass capacitor having a size corresponding to the lead pitch standardized in advance must be used. Thus, it becomes possible to use a bypass capacitor according to the application and the like, and it is possible to obtain an effect that it is possible to flexibly respond to the user's request and the like.

  As described above, the configuration of this example can provide substantially the same effect as that of the fourth embodiment, and in addition, peripheral parts having a size corresponding to the lead pitch can be used, so that it can flexibly respond to user requests and the like. The effect that it can be done can be obtained.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and the present invention can be changed even if there is a design change or the like without departing from the gist of the present invention. include. For example, in the embodiment, the example in which the bypass capacitor is used as the peripheral component has been described. However, the present invention is not limited to this and can be applied to the case where other components such as a resistor are used. In the integrated circuit package manufacturing method according to the embodiment, an example in which a plurality of LSI chips are arranged in each group has been described. However, the present invention is not limited to this, and at least one LSI chip in each group may be arranged. Further, the size of the land provided on the side surface of the integrated circuit package and the size of the bypass capacitor used as the peripheral component are shown as an example, and the present invention is not limited to this and can be applied to different sizes.

1 is a perspective view showing an integrated circuit package assembly structure that is Embodiment 1 of the present invention; FIG. The main part of the integrated circuit package assembly structure is shown enlarged, (a) is a perspective view showing a configuration before mounting peripheral components, and (b) is a perspective view showing a configuration after mounting peripheral components. . It is process drawing which shows the manufacturing method of the integrated circuit package used for the integrated circuit package assembly structure in order of a process. The main part of the integrated circuit package assembly structure which is Example 2 of this invention is expanded and shown, (a) is a perspective view which shows the structure before mounting a peripheral component, (b) is after mounting a peripheral component It is a side view which shows a structure. FIG. 6 shows an integrated circuit package assembly structure that is Embodiment 3 of this example, (a) is a perspective view showing a configuration before mounting peripheral components, and (b) is a perspective view showing a configuration after mounting peripheral components. is there. It is a perspective view which shows the integrated circuit package assembly structure which is Example 4 of this invention. 6 shows an enlarged main part of FIG. 6, (a) is a top view, and (b) is a side view. 10 is a perspective view showing a comparative example with respect to Example 4. FIG. It is a side view which shows the integrated circuit package assembly structure which is Example 5 of this invention. The concept of a prior art example is shown, (a) is a perspective view which shows the structure before mounting a peripheral component, (b) is a perspective view which shows the structure after mounting a peripheral component. It is sectional drawing which shows a prior art example.

Explanation of symbols

1 Circuit Board 2 BGA Package 2S Side of BGA Package 3, 22 Bypass Capacitor 4 BGA Package Land (Peripheral Component Connection Electrode)
5, 23 Bypass capacitor electrodes 6a-6c, 7a-7c LSI chip 8 Metal member 9, 11 Wiring 10, 15, 20, 25, 30 Integrated circuit package assembly structure 12 Sealing body 13 Reinforcement land (peripheral component reinforcement) Electrode)
14, 16 lands 14E, 16E GND lands 17, 19 SOP (SO package)
18A-18D, 21A-21E Lead

Claims (1)

An integrated circuit package assembly structure in which an integrated circuit and peripheral components are combined and mounted on a circuit board,
An electrode is provided so as to be in surface contact with a side surface of the package of the integrated circuit, and the electrode is in surface contact with a surface of the circuit board on which the integrated circuit is mounted from a lower end edge of the side surface of the package of the integrated circuit. The peripheral component extends outwardly in a bent shape and has a first part of the electrode in surface contact with the side surface of the package and a second part of the electrode in surface contact with the circuit board surface. An integrated circuit package assembly structure characterized in that an electrical connection is made in an arrangement state not exceeding the height of the package.

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