JPH04162657A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH04162657A
JPH04162657A JP2287015A JP28701590A JPH04162657A JP H04162657 A JPH04162657 A JP H04162657A JP 2287015 A JP2287015 A JP 2287015A JP 28701590 A JP28701590 A JP 28701590A JP H04162657 A JPH04162657 A JP H04162657A
Authority
JP
Japan
Prior art keywords
lead
lead frame
power supply
dielectric
tip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2287015A
Other languages
Japanese (ja)
Inventor
Hiroyuki Hatori
羽鳥　浩行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2287015A priority Critical patent/JPH04162657A/en
Publication of JPH04162657A publication Critical patent/JPH04162657A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

Abstract

PURPOSE:To enable noise on a power supply line to be restricted, eliminate the need for an externally mounted capacitor, enable the number of components on the board to be reduced, and achieve a high-density packaging by allowing at least one lead to hold a dielectric between leads to be connected to a power supply and allowing a lead frame to have capacity. CONSTITUTION:A lead frame 1 consists of a lead 3 to be connected to a power supply with a tap part 2 for sealing a chip including a semiconductor element at a tip and a lead 4 to be connected to the power supply similarly. A tip of the lead 4 has a square tip part 5 as in the tap part 2. A dielectric 6 is held between the tab part 2 of the lead 3 and the tip part 5 of the lead 4. The dielectric 6 consists of for example a ceramic material. The lead frame 1 has a capacity at the tab part 2 according to the tap part electrode 2 of the lead 3 and the tip part electrode 5 of the lead 4 as well as the dielectric 6, thus enabling noise of the power supply line to be restricted.

Description

【発明の詳細な説明】 ［産業上の利用分野コ 本発明は半導体装置用リードフレームに関し、特に、電
源ライン上のノイズを解消できる容量をもつリードフレ
ームに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor device, and more particularly to a lead frame having a capacity capable of eliminating noise on a power supply line.

［従来の技術］ 実装用基板（ボード）上に、半導体装置（以下、ＩＣと
いうこともある）を搭載し、システムを組むときに、当
該ボードの配線上（特に、電源ライン上）にノイズが乗
ることがあり、電源電圧にノイズが乗ると、システム全
体の誤動作をまねくおそれがある。[Prior art] When a semiconductor device (hereinafter also referred to as an IC) is mounted on a mounting substrate (board) and a system is assembled, noise is generated on the wiring of the board (especially on the power line). If noise is added to the power supply voltage, it may cause the entire system to malfunction.

そこで、従来、その対策として、ＩＣと別個に、所謂デ
カップリングコンデンサと称されるコンデンサを付設す
ることが行われていた。Conventionally, as a countermeasure against this problem, a capacitor called a so-called decoupling capacitor has been attached separately from the IC.

尚リードフレームについて述べた特許および実用新案の
例としては、特公昭６１−１６５５３号公報、実開昭４
８−８８９４２号、同５１−２１５６２号、同５２−１
６４２４４号、同５３−５６５４５号公報が挙げられる
。Examples of patents and utility models that describe lead frames include Japanese Patent Publication No. 61-16553 and Utility Model Publication No. 4
No. 8-88942, No. 51-21562, No. 52-1
No. 64244 and No. 53-56545 are cited.

［発明が解消しようとする課題］ しかるに、このようにＩＣと別個にコンデンサを付設す
る形態では、システムを組む上で、部品点数が多くなり
、また、コンデンサを付加する空間が必要となるので高
密度にＩＣを組込むことを妨げ、さらに、ボードも大型
のものを必要としていた。[Problems to be solved by the invention] However, in this configuration in which the capacitor is attached separately from the IC, the number of parts increases when assembling the system, and space for adding the capacitor is required, so it is expensive. The density hindered the integration of ICs and also required a large board.

本発明は、かかる従来技術の有する欠点を解消し、電源
ライン上のノイズを抑制できるとともに、外付けのコン
デンサを必要とせず、ボード上の部品点数を軽減でき、
高密度実装が可能で、ボードも小型化できる技術を提供
することを目的とする。The present invention eliminates the drawbacks of the prior art, suppresses noise on the power supply line, does not require an external capacitor, and reduces the number of components on the board.
The purpose is to provide technology that enables high-density packaging and miniaturization of boards.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

［課題を解決するための手段］ 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

本発明では、リードフレームに容量をもたせるようにし
たもので、リードフレームのリード間に誘電体を挟持さ
せるようにした。In the present invention, the lead frame is made to have a capacitance, and a dielectric material is sandwiched between the leads of the lead frame.

［作用］ これにより、容量をもつリードフレームに、半導体素子
を含むチップを搭載し、電源ラインと電気的に接続させ
、当該チップを収納しパッケージ化したＩＣを、ボード
上に実装すれば、当該ＩＣ内のリードフレームの誘電体
よりなる容量が電源ラインのノイズを抑制する効果をも
ち、当該ＩＣの他に別個にコンデンサをボード上に付加
する必要がなくなり、その結果、部品点数が少なくなり
、高密度実装が可能で、ボードも小型化できる。[Function] As a result, if a chip containing a semiconductor element is mounted on a lead frame with a capacitance and is electrically connected to a power supply line, and the chip is housed and packaged, the IC is mounted on a board. The capacitance made of the dielectric material of the lead frame in the IC has the effect of suppressing noise in the power supply line, and there is no need to add a separate capacitor to the board in addition to the IC, resulting in a reduction in the number of parts. High-density mounting is possible, and boards can be made smaller.

［実施例コ 以下、本発明の実施例を図面に基づいて説明する。[Example code] Embodiments of the present invention will be described below based on the drawings.

第１図は、本発明の実施例を示すリードフレー二の要部
説明図、第２図はリードフレームの断面図である。FIG. 1 is an explanatory view of the main parts of a lead frame showing an embodiment of the present invention, and FIG. 2 is a sectional view of the lead frame.

リードフレーム１は、半導体素子を含むチップを固着さ
せるタブ部２を先端に有する電源（ＶｃＣ）と接続され
るリード３と、同様に電源（ＶｃＣ）と接続されるリー
ド４とを具備して成る。The lead frame 1 includes a lead 3 connected to a power source (VcC), which has a tab portion 2 at the tip for fixing a chip containing a semiconductor element, and a lead 4 similarly connected to the power source (VcC). .

リード４の先端には、上記リード３のタブ部２と同様に
四辺形の先端部５を有している。The tip of the lead 4 has a quadrilateral tip 5 similar to the tab portion 2 of the lead 3 described above.

当該リード３のタブ部２と当該リード４の先端部５との
間には、誘電体６が挟持されている。A dielectric 6 is sandwiched between the tab portion 2 of the lead 3 and the tip 5 of the lead 4.

誘電体６は、例えばセラミック材により構成される。The dielectric 6 is made of, for example, a ceramic material.

リード３のタブ部電極２とリード４の先端部電極５と誘
電体６により、リードフレーム１はそのタブ部２に容量
を持つ。The lead frame 1 has a capacitance in the tab portion 2 due to the tab electrode 2 of the lead 3, the tip electrode 5 of the lead 4, and the dielectric 6.

図示が省略されているが、タブ部２の表面には、半導体
素子を含むチップが固着され、該チップのバッドと、リ
ード３との間で、ワイヤボンディングが行われ、また、
該チップのパッドとリード４との間でもワイヤボンディ
ングが行われる。Although not shown, a chip including a semiconductor element is fixed to the surface of the tab portion 2, and wire bonding is performed between the pad of the chip and the lead 3.
Wire bonding is also performed between the pads of the chip and the leads 4.

前述のように、リード３とリード４とは、それぞれ電源
ラインに接続している。As described above, lead 3 and lead 4 are each connected to a power supply line.

同様にその図示が省略されているが、当該ワイヤボンデ
ィング後に、その組立て品は、樹脂モールドに付され、
パッケージ化される。Similarly, although illustration is omitted, after the wire bonding, the assembled product is placed in a resin mold,
Packaged.

第３図は当該ＩＣパッケージの内部配線図を示し、リー
ド３部分に対応するパッケージ部分３０およびリード４
部分に対応するパッケージ部分４０は、それぞれ一方が
Ｖｃｃに、他方がグランド（ＧＮＤ）に電気的に接続さ
れている。FIG. 3 shows an internal wiring diagram of the IC package, and shows a package part 30 corresponding to the lead 3 part and a lead 4 part.
The corresponding package parts 40 are electrically connected on one side to Vcc and on the other side to ground (GND).

本発明に使用されるリードフレーム１は、例えば、Ｎｉ
−Ｆｅ合金により構成されている。The lead frame 1 used in the present invention is made of, for example, Ni
-Constructed from Fe alloy.

半導体素子を含むチップは、例えばシリコン単結晶基板
から成り、周知の技術によって、その内部には多数の回
路素子が形成され、１つの回路機能が与えられている。A chip including a semiconductor element is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed therein using a well-known technique to provide one circuit function.

回路素子の具体例は、例えばＭＯＳトランジスタから成
り、これらの回路素子によって、例えば論理回路および
メモリの回路機能が形成されている。A specific example of the circuit element is, for example, a MOS transistor, and these circuit elements form the circuit functions of, for example, a logic circuit and a memory.

本発明によれば、ＩＣパッケージ内部のリードフレーム
１自体が、リード３電極とり−ド４電極と誘電体６より
なる容量をもち電源ラインのノイズを抑えることができ
るので、従来例のようにコンデンサをＩＣパッケージと
は別個に取付ける必要はない。According to the present invention, the lead frame 1 itself inside the IC package has a capacitance made up of 3 leads, 4 electrodes, and a dielectric 6, and can suppress noise on the power supply line. There is no need to mount the IC separately from the IC package.

従って、実装に際して当該ＩＣパッケージの他にコンデ
ンサを付設しなくてもよいので、ボード上の部品点数が
軽減されるとともに、コンデンサの付設に要するスペー
スを確保しなくても済むので、ボード上においてＩＣパ
ッケージの高密度実装が可能で、しかも、ボードは小型
化できる。Therefore, since there is no need to attach a capacitor in addition to the IC package when mounting, the number of parts on the board is reduced, and there is no need to secure the space required for attaching a capacitor, so the IC package can be mounted on the board. High-density package packaging is possible, and the board can be made smaller.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

［発明の効果］ 本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

すなわち、本発明によれば、ＩＣパッケージ内部のリー
ドフレーム自体が、リード電極とリード電極と誘電体よ
りなる容量をもち電源ラインのノイズを抑えることがで
きるので、従来例のようにコンデンサをＩＣパッケージ
とは別個に取付ける必要はない。That is, according to the present invention, the lead frame itself inside the IC package has a capacitance made up of lead electrodes, lead electrodes, and a dielectric material, and can suppress noise in the power supply line. There is no need to install it separately.

従って、実装に際して当該ＩＣパッケージの他にコンデ
ンサを付設しなくてもよいので、ボード上の部品点数が
軽減されるとともに、コンデンサ分のスペースを確保し
なくても済むので、ボード上ＩＣパンケージの高密度実
装が可能で、しかも、ボードは小型化できる。Therefore, since there is no need to attach a capacitor in addition to the IC package during mounting, the number of components on the board is reduced, and there is no need to secure space for the capacitor, so the height of the IC package on the board can be reduced. Density mounting is possible, and the board can be made smaller.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例を示すリードフレームの要部説
明図、 第２図は本発明の実施例を示す断面図、第３図は本発明
の実施例を示す配線図である。 １　・リードフレーム、２・・タブ部、３・・リード、
４　リード、５　リード４の先端部、６・−誘電体。FIG. 1 is an explanatory diagram of main parts of a lead frame showing an embodiment of the present invention, FIG. 2 is a sectional view showing an embodiment of the present invention, and FIG. 3 is a wiring diagram showing an embodiment of the present invention. 1.Lead frame, 2..Tab section, 3..Lead,
4 lead, 5 tip of lead 4, 6 - dielectric.

Claims (1)

【特許請求の範囲】 １、半導体装置用リードフレームにおいて、少なくとも
一方のリードは電源と接続されるリード間に誘電体を挟
持させ、当該リードフレームに容量を持たせて成ること
を特徴とする半導体装置用リードフレーム。 ２、一方のリードはその先端部に半導体装置素子を含む
チップを固着させるタブ部を有し、他方のリードは誘電
体を支持できる先端部を有し、これらリードのタブ部と
先端部との間に誘電体層を形成して、半導体素子を含む
チップを固着するタブ部に容量を持たせて成る、請求項
１に記載の半導体装置用リードフレーム。[Claims] 1. A lead frame for a semiconductor device, in which at least one lead is connected to a power source, and a dielectric material is sandwiched between the leads, and the lead frame has a capacitance. Lead frame for equipment. 2. One lead has a tab portion at its tip portion to which a chip containing a semiconductor device element is fixed, and the other lead has a tip portion that can support a dielectric material, and the tab portion and the tip portion of these leads are 2. The lead frame for a semiconductor device according to claim 1, wherein a dielectric layer is formed between the tab portions for fixing a chip including a semiconductor element to have a capacitance.
JP2287015A 1990-10-26 1990-10-26 Lead frame for semiconductor device Pending JPH04162657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2287015A JPH04162657A (en) 1990-10-26 1990-10-26 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2287015A JPH04162657A (en) 1990-10-26 1990-10-26 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPH04162657A true JPH04162657A (en) 1992-06-08

Family

ID=17711930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2287015A Pending JPH04162657A (en) 1990-10-26 1990-10-26 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH04162657A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206373A (en) * 1992-01-28 1993-08-13 Nec Kyushu Ltd Semiconductor integrated circuit device
WO1996015555A1 (en) * 1994-11-10 1996-05-23 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US5589709A (en) * 1992-12-03 1996-12-31 Linear Technology Inc. Lead frame capacitor and capacitively-coupled isolator circuit using same
US5965936A (en) * 1997-12-31 1999-10-12 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US6054754A (en) * 1997-06-06 2000-04-25 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
US6114756A (en) * 1998-04-01 2000-09-05 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit leadframes
US6472737B1 (en) 1998-01-20 2002-10-29 Micron Technology, Inc. Lead frame decoupling capacitor, semiconductor device packages including the same and methods

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206373A (en) * 1992-01-28 1993-08-13 Nec Kyushu Ltd Semiconductor integrated circuit device
US5589709A (en) * 1992-12-03 1996-12-31 Linear Technology Inc. Lead frame capacitor and capacitively-coupled isolator circuit using same
US5650357A (en) * 1992-12-03 1997-07-22 Linear Technology Corporation Process for manufacturing a lead frame capacitor and capacitively-coupled isolator circuit using same
US5926358A (en) * 1992-12-03 1999-07-20 Linear Technology Corporation Lead frame capacitor and capacitively-coupled isolator circuit using same
US5945728A (en) * 1992-12-03 1999-08-31 Linear Technology Corporation Lead frame capacitor and capacitively coupled isolator circuit
US6124630A (en) * 1994-11-10 2000-09-26 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
WO1996015555A1 (en) * 1994-11-10 1996-05-23 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US5734198A (en) * 1994-11-10 1998-03-31 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US6307255B1 (en) 1994-11-10 2001-10-23 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US6707136B2 (en) 1996-09-04 2004-03-16 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US6515353B2 (en) 1996-09-04 2003-02-04 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US6781219B2 (en) 1997-06-06 2004-08-24 Micron Technology, Inc. Semiconductor die assembly having leadframe decoupling characters
US6184574B1 (en) 1997-06-06 2001-02-06 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
US6504236B2 (en) 1997-06-06 2003-01-07 Micron Technology, Inc. Semiconductor die assembly having leadframe decoupling characters and method
US6054754A (en) * 1997-06-06 2000-04-25 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
US6310388B1 (en) 1997-06-06 2001-10-30 Micron Technology, Inc. Semiconductor die assembly having leadframe decoupling characters
US5965936A (en) * 1997-12-31 1999-10-12 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US6515359B1 (en) 1998-01-20 2003-02-04 Micron Technology, Inc. Lead frame decoupling capacitor semiconductor device packages including the same and methods
US6472737B1 (en) 1998-01-20 2002-10-29 Micron Technology, Inc. Lead frame decoupling capacitor, semiconductor device packages including the same and methods
US6717257B2 (en) 1998-01-20 2004-04-06 Micron Technology, Inc. Lead frame decoupling capacitor, semiconductor device packages including the same and methods
US7071542B2 (en) 1998-01-20 2006-07-04 Micron Technology, Inc. Lead frame decoupling capacitor, semiconductor device packages including the same and methods
US6396134B2 (en) 1998-04-01 2002-05-28 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit lead frames
US6531765B2 (en) 1998-04-01 2003-03-11 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit lead frames and method
US6265764B1 (en) 1998-04-01 2001-07-24 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit lead frames
US6730994B2 (en) 1998-04-01 2004-05-04 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit lead frames and methods
US6114756A (en) * 1998-04-01 2000-09-05 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit leadframes

Similar Documents

Publication Publication Date Title
US6271582B1 (en) Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die
US5656856A (en) Reduced noise semiconductor package stack
US5200364A (en) Packaged integrated circuit with encapsulated electronic devices
KR100447869B1 (en) Stack Semiconductor Chip Package Having Multiple I/O Pins and Lead Frame Suitable For Use in Such a Stack Semiconductor Chip Package
US5115298A (en) Packaged integrated circuit with encapsulated electronic devices
US4934820A (en) Semiconductor device
JPH07288309A (en) Semiconductor device, manufacture thereof and semiconductor module
JPS61117858A (en) Semiconductor device
JPH1084074A (en) Semiconductor package
JPH04162657A (en) Lead frame for semiconductor device
US6052289A (en) Interdigitated leads-over-chip lead frame for supporting an integrated circuit die
JPH09120974A (en) Semiconductor device
JPS63132459A (en) Semiconductor package with built-in capacitor
JPH0521698A (en) Semiconductor device
JP2780355B2 (en) Semiconductor integrated circuit device
TWI253156B (en) Providing in package power supplies for integrated circuits
JPH05121632A (en) Semiconductor device
JP3846777B2 (en) Ball grid array package
JP3064674B2 (en) Semiconductor device
JPH06163700A (en) Integrated circuit device
JPS62210661A (en) Semiconductor device
JP2522455B2 (en) Semiconductor integrated circuit device
KR0159965B1 (en) Semiconductor package having heat sink
KR101014180B1 (en) Semiconductor chip
JPH01296654A (en) Semiconductor device