JP4660214B2 - Power semiconductor device - Google Patents

Description

  The present invention has a circuit in which an output line to a load is drawn from a connection point of two series-connected semiconductor switching elements in which power lines from a power source are connected to both ends, and both the semiconductor switching elements are complementarily opened and closed The present invention relates to a power semiconductor device that converts the power of the power source by being controlled and outputs the converted power to the load, and particularly relates to a device having a wiring structure suitable for high power use.

Conventionally, in order to solve various problems such as power loss, heat generation, destruction, malfunction due to noise, etc., which are increased as a larger current is required to be converted at a higher frequency in a power semiconductor device. Reduction of inductance is one solution (Patent Documents 1 to 5).
Patent Document 1 paragraph 0005 describes that when the inductance is L, a surge voltage of −L (di / dt) is generated, which may cause malfunction or destruction.
As semiconductor switching elements, transistors such as MOSFETs and IGBTs are mainly used. As a semiconductor device for high power use, there is a three-phase motor drive circuit such as an electric hawk lift. It is required to convert a large current at a high frequency (more than 10 kHz for a hawk lift) to increase the output of electric motors such as vehicles and lifts and to prevent noise.

Patent Documents 1 to 3 describe circuits of both series semiconductor switching elements in which an output line is connected to each other connection point and a power line is connected to both ends.
In Patent Document 1, a circuit diagram is shown in FIG. 10 and an external view of the apparatus is shown in FIGS. As shown in FIG. 11 of Patent Document 1, in the drive circuit of the three-phase motor, three sets of series semiconductor switching element circuits are configured corresponding to the u-phase, v-phase, and w-phase.
In the devices described in Patent Literatures 1 to 3, the high potential side of the power line is P, the low potential side is N, and the output line is U. The flat electrode lead-out terminals corresponding to these three electrodes (the electrodes are led out to the outside) Are arranged in parallel.
In the device described in Patent Document 1, the portions of the electrode lead-out terminals arranged in parallel to each other are vertically placed with respect to the mounting substrate of the semiconductor switching element, and the P and N electrode lead-out terminals are compared. Placed close to each other.
In the device described in Patent Document 2 and the device described in Patent Document 3 in FIG. 1, the portions of the electrode lead-out terminals arranged in parallel with each other are stacked via an insulator and mounted with a semiconductor switching element. Arranged in parallel to the substrate, three layers are stacked in the order of P, U, N or N, U, P.

また、インダクタンスＬは、Ｌ＝Ｌｓ±Ｍ ・・・（３）で表される。但し、同方向に電流が流れるときに＋、逆方向に電流が流れるときに−である。 Here, according to Neumann's theorem, the self-inductance Ls of a round bar wire having a length l, a radius a, and an inductivity μ is expressed by the following equation (1): a length l parallel to the center axis distance d, an inductivity A mutual inductance M acting between two round bar conductors of μ is expressed by the following equation (2).

The inductance L is expressed by L = Ls ± M (3). However, it is + when current flows in the same direction, and-when current flows in the opposite direction.

In Patent Document 1, paragraph 0040 flows through an E ₂ terminal (reference numeral 5 in the same document) and a C ₁ terminal (reference numeral 7 in the same document) that are parallel to each other and separated by a distance d that is 1/5 times the terminal width of the shorter one. It is described that since the current is in the opposite direction, a negative mutual inductance works and acts to reduce the inductance of both terminals. Here, the E ₂ terminal and the C ₁ terminal correspond to the P and N electrode lead-out terminals (the E ₂ terminal is N and the C ₁ terminal is P).
This is interpreted as stating that L is reduced if the equation (3) becomes L = Ls−M because the current is in the reverse direction, and 0 <M <2Ls (however, the same document) Does not touch the effective range of M).

In Patent Document 2, paragraph 0006, assuming that there is no leakage current, the same current that flows in the output line U flows in either the P power line or the N power line in the opposite direction to the U output line, so that the inductance of the wiring is effective. It is described that it can be reduced.
This is interpreted as stating that L is reduced if the equation (3) becomes L = Ls−M because the current is in the reverse direction, and 0 <M <2Ls (however, the same document) Does not touch the effective range of M).

Patent Document 3 paragraph 0016 includes an electrode bar for deriving the U electrode (reference numeral 35 in the same document), an electrode bar for deriving the P electrode (reference numeral 36 in the same document), and an electrode bar for deriving the U electrode (in the same document). It is described that the current at the time of switching flows to the opposite side in the overlapping part of the electrode bar 35) and the electrode bar for deriving the N electrode (reference numeral 37 in the same document), so that the inductance value at that time is almost zero. ing.
This is interpreted as stating that L is reduced if the equation (3) becomes L = Ls−M because the current is in the reverse direction, and 0 <M <2Ls (however, the same document) Does not touch the effective range of M). If the current is reversed and the values of Ls and M are equal, L is 0.

Further, in the inventions described in Patent Documents 1 to 3, it is understood that the self-inductance is intended to be reduced by forming the P, U, and N electrode lead-out terminals into a wide flat plate shape (Patent Documents). 1 paragraph 0043 etc.).
In addition, although Formula (1) is related with a round bar conducting wire, the radius a in Formula (1) is a parameter relating to the cross-sectional area of the conducting wire. If the thickness is constant, the self-inductance Ls decreases as the width of the conductor increases.

As described above, in the inventions described in Patent Documents 1 to 3, in common, the self-inductance Ls is reduced by the wide electrode, and canceling is performed by canceling the mutual inductance M by the reverse current. It is understood that it is based on the theory of reducing.
By reducing the inductance L, the surge voltage -L (di / dt) is reduced to prevent breakage, magnetically acting noise is reduced to prevent malfunction, and the switching loss corresponding to the inductance is reduced. As a result, it is understood that the amount of generated heat is reduced.
Japanese Patent No. 3053298 JP 2001-332688 A JP 2004-214452 A Japanese Patent Laid-Open No. 11-177021 JP-A-11-177018

  In contrast to the configuration in which the three electrodes described in Patent Document 1 are arranged vertically with respect to the circuit board, the inventions described in Patent Documents 2 and 3 having three-layer wirings in which the three electrodes are stacked flattened to reduce the thickness of the device. It is advantageous.

However, the effect of reducing the inductance L due to the generation of the mutual inductance M is limited to the case where the currents flowing in the adjacent conductors are opposite at the same point and the value of the mutual inductance M is 0 <M <2Ls.
Under the driving operation of a three-phase motor or the like, it is impossible to flow a current in all directions of the three-layer wiring of P, N, and U at all times, and the mutual inductance M value is canceled out. In order to be within the range of 0 <M <2Ls, it is difficult to make the inductance canceling effect highly effective because the range of the distance d is limited. If it is not in the range of 0 <M <2Ls, the inductances are strengthened.
In the inventions of Patent Documents 2 and 3, the three-layer wiring is laminated in the order of P, U, and N. However, the U electrode moves at a frequency twice that of the P and U electrodes. The amount of heat generation is most likely to increase, and sandwiching between the P and U electrodes is disadvantageous in terms of heat dispersibility and heat dissipation, and the influence of noise is relatively large.
Since such a disadvantageous arrangement for heat countermeasures is forced, it is difficult to effectively exhibit the inductance canceling effect while obtaining a thermal design gain. In addition, the arrangement giving priority to noise countermeasures is also limited.

As described above, the inventions described in Patent Documents 2 and 3 having the three-layer wiring in which the three electrodes are flatly stacked in contrast to the configuration in which the three electrodes described in Patent Document 1 are arranged vertically with respect to the circuit board, It is advantageous for thinning.
Furthermore, in contrast to the configuration in which the three electrode lead-out terminals described in Patent Document 2 are installed adjacent to the semiconductor element on the circuit board, the configuration in Patent Document 3 in which the circuit board is spaced apart from the circuit board is arranged. However, this is advantageous for increasing the wiring width of the electrode lead-out terminal and reducing the area of the device.

Further, in the apparatus described in Patent Document 3, the branch portion protruding in the circuit board direction at the end of the electrode lead-out terminal (“electrode bar” in the same publication) is directly connected to the electrode on the surface of the semiconductor chip. Although it is simpler than the devices described in Patent Documents 1 and 2 in which bonding wires are connected to the electrodes on the surface, the dimensional accuracy of the electrode lead-out terminal and the dimensional accuracy of the case that holds one end of the electrode lead-out terminal are strictly required. Also, careful assembly work is required so as not to damage the semiconductor chip. Assembling stress and thermal stress applied to the semiconductor chip increase, and environmental temperature changes and it is added during use as when mounted on a forklift. There is concern about equipment failure due to vibration or the like.
In the device described in Patent Document 2, one end of a bonding wire is bonded to an electrode on the surface of a semiconductor chip, and the other end is bonded to an electrode lead-out terminal (“3-layer wide electrode” in the same publication), and the other end Since there is a wire bonded to the conductor pattern on the circuit board, all wire bonding cannot be performed before the electrode lead-out terminals are arranged, that is, the wire bonding cannot be completed in the mounting process of the circuit board alone. . Further, since the bonding wire is connected to the electrode lead-out terminal, the dimensional accuracy, the placement accuracy, the wire bonding accuracy, etc. of the electrode lead-out terminal are strictly required.
In the apparatus described in Patent Document 1, since both ends of the bonding wire are bonded to the semiconductor chip or the circuit board, the wire bonding can be completed in the mounting process of the circuit board alone, and the electrode lead-out terminal is connected to the semiconductor chip. Although accuracy in consideration of direct connection and wire bonding is not required, the circuit area increases. In addition to an increase in circuit area, the electrode lead-out terminals are erected perpendicularly to the circuit surface, which increases the size of the device.

In the device described in Patent Document 3, as shown in FIG. 1 of Patent Document 3, the lower end of the branch portion protruding in the circuit board direction at the end portion of the electrode lead-out terminal (“electrode bar” in the same publication) is The space above the semiconductor element is bent so as to be parallel to the surface of the semiconductor element, and the space above the semiconductor element is not used as a laminated space for the three-layer wiring.
Further, as shown in FIG. 1 of Patent Document 3, the lead-out direction of the U electrode is different from the P and N electrodes, and the electrode lead-out terminal for taking out the U electrode is detoured in the internal space of the device. The wiring width of the three electrode lead-out terminals decreases.
Therefore, the device described in Patent Document 3 also has a disadvantageous structure for enlarging the wiring width in a certain device space.

The present invention has been made in view of the above-described problems in the prior art, and it is an object of the present invention to provide a power semiconductor device in which the shape and arrangement of electrode lead-out terminals are good in terms of thinning, thermal countermeasures, and noise countermeasures. And
It is another object of the present invention to provide a power semiconductor device in which heat dispersibility and heat dissipation are improved and wiring resistance, particularly heat resistance, is reduced.
It is another object of the present invention to provide a highly reliable power semiconductor device that has a good manufacturing yield, can withstand the environment during use, and has high reliability.
As a result, an object of the present invention is to provide a power semiconductor device that can withstand a larger current at a higher frequency.

The invention described in claim 1 for solving the above-described problems has a circuit in which an output line to a load is drawn from a connection point between two series-connected semiconductor switching elements in which power lines from a power source are connected to both ends. The power semiconductor device that converts the power of the power source and outputs the power to the load by complementary open / close control of the semiconductor switching elements,
The high potential side of the power line is P, the low potential side is N, the output line is U, and there are three electrode lead-out terminals corresponding to three electrodes of P, N, U,
The three electrode lead-out terminals are stacked above the circuit board on which the semiconductor switching element is mounted, and are stacked at intervals in the order of P, N, U from the side closer to the circuit board, and at least in the stacked portion, the circuit board It is formed in a flat plate shape parallel to the power semiconductor device.

According to the first aspect of the present invention, since the electrode lead-out terminals are arranged in the order of P, N, and U from the side close to the circuit board in parallel with the circuit board, the electrode lead-out terminals are doubled with respect to the P and N electrode lead-out terminals. The U electrode lead-out terminal that flows the current of the highest frequency and generates the largest amount of heat is placed at the top of the three layers, and the U electrode lead-out terminal can be placed on the device surface side opposite to the back surface of the circuit board.
As a result, the U electrode lead-out terminal having the largest heat generation amount can be arranged on the device surface side away from the circuit board to prevent heat concentration, and the heat radiation from the device surface side of the U electrode lead-out terminal can be promoted. And heat dissipation is improved.
Since a relatively low temperature P and N electrode lead-out terminal is interposed between the U electrode lead-out terminal and the circuit board, radiation heat from the U electrode lead-out terminal to the circuit board can be prevented.
Further, the P electrode lead-out terminal is disposed closest to the circuit board. Further, an N electrode lead-out terminal is disposed on the P electrode lead-out terminal. Both the high-potential P-electrode lead terminal and the low-potential N-electrode lead terminal are relatively stable in potential, and therefore, noise is not caused to the circuit board without causing a significant change in the magnetic field with the circuit board. The influence of can be suppressed. Since both the circuit board that is likely to be a noise source and the U electrode lead-out terminal are separated via the P and N electrode lead-out terminals, the influence of noise can be suppressed.
In addition, the laminated portion where the three electrode lead-out terminals P, N, and U are laminated is formed in a flat plate shape parallel to the circuit board, and is disposed above the circuit board, which is advantageous for reducing the thickness and size of the device.
As described above, the shape and arrangement of the electrode lead-out terminals are good in terms of thinning, heat countermeasures, and noise countermeasures. As a result, even with a small size, a larger current can be converted at a higher frequency.

  According to a second aspect of the present invention, in the power semiconductor device according to the first aspect, the stacked portion is disposed above one or more of the semiconductor switching elements.

According to the second aspect of the present invention, since the stacked portion of the P, N, and U three electrode lead-out terminals is disposed above one or more semiconductor switching elements, the space above the semiconductor switching elements is also increased. By utilizing this, the wiring width of the laminated portion can be formed wide.
By increasing the wiring width, the heat capacity of the electrode lead-out terminal is increased, the heat dispersibility is improved, and the wiring resistance, particularly the thermal resistance component, is reduced. As a result, it can withstand higher currents at higher frequencies.
One of the semiconductor switching elements to which the U output line is connected is connected between P-U and the other is connected between U-N. Therefore, the minimum number of semiconductor switching elements is two. A plurality of semiconductor switching elements connected between P-U may be provided in parallel, or a plurality of semiconductor switching elements connected between U-N may be provided in parallel. Therefore, the total number of semiconductor switching elements may be 3 or more. In that case, the stacked portion can be disposed above three or more semiconductor switching elements.

  According to a third aspect of the present invention, the outer end connecting portion to which the external wiring of each of the P, N, and U electrode lead-out terminals is connected is adjacent to one side of the circuit board when the circuit board is viewed vertically. 3. The power semiconductor device according to claim 1, wherein the power semiconductor device is disposed on an outer side, and the stacked portion is formed to extend from the one side to the opposite side.

  According to the third aspect of the present invention, the P, N, and U electrode lead-out terminals are taken out in the direction opposite to the extending direction to the inside, so that they are not detoured. Since there is no detour wiring, the wiring width of the three electrode lead-out terminals can be increased in a limited device internal space.

  According to a fourth aspect of the present invention, one or more inner end connection portions connected to the circuit board of the electrode lead-out terminals of P, N, and U are formed so as to protrude from the side edge of the laminated portion, and the circuit board side 4. The power semiconductor device according to claim 1, wherein the power semiconductor device is a protrusion that is bent inwardly and further bent inward before that.

  According to invention of Claim 4, since the lower end of the protrusion-shaped inner end connection part which protrudes and is formed from the side edge of a lamination | stacking part is formed in an inner fold, compared with the case where it makes an outer fold, other When the structure is the same, the width of the stacked portion can be made larger.

In the invention according to claim 5, the lower ends bent inside the inner end connection portions of the P, N, and U electrodes are respectively joined to the conductor pattern on the circuit board,
The semiconductor switching element connected between P-U is joined to a conductor pattern to which the inner end connection portion of the P electrode is joined,
The surface main electrode of the semiconductor switching element connected between the P-U and the conductor pattern to which the inner end connection portion of the U electrode is connected via a bonding wire,
The semiconductor switching element connected between U and N is joined to a conductor pattern to which the inner end connection portion of the U electrode is joined,
5. The main surface electrode of the semiconductor switching element connected between the U and N and a conductor pattern to which an inner end connection portion of the N electrode is joined are connected via a bonding wire. This is a power semiconductor device.

According to the fifth aspect of the present invention, the inner end connecting portions of the P, N, and U electrodes are respectively joined to the conductor pattern on the circuit board. This can be bonded by a conductive bonding agent such as solder.
Each electrode lead-out terminal is electrically connected to the electrode of the semiconductor switching element via a conductor pattern or a bonding wire on the circuit board.
Therefore, wire bonding can be completed in the mounting process of the circuit board alone, and the accuracy in consideration of direct connection to the semiconductor chip and wire bonding is not required for the electrode lead-out terminal, and the yield is relatively easy and reliable. High product can be manufactured. The circuit area increases by providing the bonding wire and the relay bonding area on the circuit board, but the space above the circuit surface is effectively used as the arrangement area for the electrode lead-out terminal, so the electrode lead-out terminal is formed wider. It becomes easy.

According to a sixth aspect of the present invention, the outer end connection portions to which the external wirings of the P, N, and U electrode lead-out terminals are connected are arranged at different positions in the order of P, N, and U along one side of the circuit board. And
The outer end connection portion of the N electrode is within the formation range of the stacked portion along the one side,
All or part of the outer end connection portion of the P electrode and the outer end connection portion of the U electrode are outside the formation range of the stacked portion along the one side,
The P-electrode lead-out terminal and the U-electrode lead-out terminal have a portion that protrudes out of the range in the direction along the one side from the end of the stacked portion on the one side and is connected to the outer end connection portion. 6. The power semiconductor device according to claim 5, wherein the power semiconductor device is a power semiconductor device.

According to the sixth aspect of the invention, first, the outer end connecting portions of the P, N, and U electrodes are arranged at different positions along one side of the circuit board, so that the external wiring can be easily connected. Furthermore, since all or part of the outer end connection portion of the P electrode and the outer end connection portion of the U electrode are outside the formation range of the laminated portion along the one side, the three outer end connection portions are widely dispersed. Even if each outer end connection portion is enlarged, a sufficient interval can be secured, and external wiring can be easily connected.
Furthermore, the P electrode lead-out terminal and the U electrode lead-out terminal are formed with a portion that protrudes out of the range in the direction along the one side from the end of the laminated portion on the one side and is connected to the outer end connecting portion. . Therefore, even if all or part of the outer end connection portion of the P electrode and the outer end connection portion of the U electrode are outside the formation range of the laminated portion along the one side, the portion connected to the outer end connection portion The wiring width is not reduced. Further, the P electrode lead terminal and the U electrode lead terminal can be made larger in volume than the N electrode lead terminal.
As for heat conduction in the solid, the N electrode lead-out terminal conducts heat only from the semiconductor switching element through the bonding wire, but the P electrode lead-out terminal and the U electrode lead-out terminal do not go through the bonding wire, and the conductor pattern on the circuit. Therefore, the heat generation amount is larger than that of the N electrode lead terminal (as described above, the U electrode lead terminal has the largest heat generation amount).
Therefore, by making the P electrode lead-out terminal and the U electrode lead-out terminal larger than the N electrode lead-out terminal, temperature imbalance can be suppressed as compared with the case where it is the same or smaller than the N electrode lead-out terminal.

  According to a seventh aspect of the present invention, a fold along the one side is formed in a portion from the outer end connecting portion to the laminated portion along the one side of the P electrode lead terminal and the U electrode lead terminal. The power semiconductor device according to claim 6.

  According to the seventh aspect of the present invention, by folding along the one side, the cross-sectional area of the portion from the outer end connecting portion to the laminated portion can be increased within a limited space, and the current and heat can be increased. Can be prevented.

  The invention according to claim 8 is characterized in that the inner end connection portion of the P electrode is formed on the opposite side of its outer end connection portion through the laminated portion. This is a power semiconductor device.

  When the inner end connecting portion and the outer end connecting portion are formed on the same side, the current density at the end opposite to the inner end connecting portion and the outer end connecting portion decreases as the laminated portion is widened. On the other hand, according to the invention described in claim 8, since the inner end connecting portion and the outer end connecting portion of the P electrode are arranged on the opposite sides of each other through the laminated portion, even if the laminated portion is widened, The uneven distribution of the current path can be suppressed, and the current density in the electrode lead-out terminal can be prevented from becoming non-uniform.

  The power semiconductor according to claim 9, wherein the inner end connection portion of the N electrode is formed on the opposite side of the inner end connection portion of the P electrode through the stacked portion. Device.

  According to the ninth aspect of the present invention, the inner end connecting portion of the P electrode and the inner end connecting portion of the N electrode are disposed on the opposite sides of each other through the stacked portion. When the mounting region of the semiconductor switching element and the mounting region of the semiconductor switching element connected between U and N are divided and arranged with the boundary immediately below the stacked portion, a symmetrical optimal wiring structure can be configured. it can.

In the invention according to claim 10, the inner end connection part of the U electrode is formed on both sides of the laminated part,
The inner end connection portion of the U electrode joined to the surface main electrode of the semiconductor switching element connected between the P-U and the conductor pattern connected via the bonding wire is an inner end connection portion of the P electrode. Formed on the same side,
The inner end connection portion of the U electrode joined to the conductor pattern to which the semiconductor switching element connected between U and N is joined is formed on the same side as the inner end connection portion of the N electrode. A power semiconductor device according to claim 9.

  According to the tenth aspect of the present invention, the mounting region of the semiconductor switching element connected between P-U and the mounting region of the semiconductor switching element connected between U-N are placed in the region immediately below the stacked portion. Thus, the inner end connection part of the U electrode can be connected in the shortest time.

  The invention according to claim 11 is characterized in that one inner end connecting portion of the P electrode is located on the tip side of the stacked portion and one or more of the U electrodes formed on the same side as the inner end connecting portion of the P electrode. 11. The power semiconductor device according to claim 10, wherein all of the inner end connection portions are located closer to the base end side of the stacked portion than one inner end connection portion of the P electrode located on the distal end side. .

According to the eleventh aspect of the present invention, the amount of heat generated is larger than that of the inner end connection portion of the U electrode joined to the surface main electrode of the semiconductor switching element connected between P and U and the conductor pattern connected via the bonding wire. Since at least one of the inner end connection portions of the P electrode that tends to be large is disposed on the most distal side, the substantial current path cross-sectional area can be increased in the P electrode lead-out terminal disposed in the stacked portion, The current can be dispersed, and the concentration of current and heat can be reduced.
The inner end connection portion connected to the semiconductor switching element via the conductor pattern on the circuit board generates more heat than the inner end connection portion connected to the semiconductor switching element via the conductor pattern and bonding wire on the circuit board. Becomes larger. It is preferable to increase the substantial current path cross-sectional area in the electrode lead-out terminal where the heat generation amount is large.

  The invention according to claim 12 is characterized in that one inner end connection portion of the U electrode formed on the same side as the inner end connection portion of the N electrode is located on the tip side of the stacked portion, and one or more of the N electrodes are provided. 11. The power semiconductor device according to claim 10, wherein all of the inner end connection portions are located closer to the base end side of the stacked portion than one inner end connection portion of the U electrode located on the distal end side. .

  According to the twelfth aspect of the invention, at least one of the inner end connection portions of the U electrode that generates the largest amount of heat to be bonded to the conductor pattern to which the semiconductor switching element connected between U and N is bonded is the most distal end. Since it is arranged on the side, the substantial current path cross-sectional area can be increased in the U electrode lead-out terminal arranged in the laminated portion, the current can be spread more widely, and the concentration of current and heat can be reduced. Can do.

  The invention according to claim 13 is characterized in that the inner end connecting portions of the respective P, N, and U electrodes are provided on the same side edge so as to be distributed to the distal end side and the proximal end side. A power semiconductor device according to any one of claims 4 to 12.

  According to the thirteenth aspect of the present invention, since there are always two or more current paths from the laminated portion to the inner end connecting portion and from the inner end connected portion to the laminated portion, the distal end side and the proximal end side are secured. In each electrode lead-out terminal, the substantial current path cross-sectional area can be increased, the current can be more widely dispersed, and the concentration of current and heat can be reduced.

  The invention according to claim 14 is a heat sink that contacts the back surface of the circuit board, and a frame-like insulating case that is fixed to an edge of the heat sink around the circuit board and surrounds the circuit board. The power semiconductor device according to any one of claims 1 to 13, wherein the three electrode lead-out terminals are held by being partially buried in the insulating case. It is.

  According to the fourteenth aspect of the present invention, the heat dissipation from the back surface of the circuit board is good by the heat radiating plate, and the three electrode lead-out terminals are buried and held in the insulating case. Also, after the electrode lead-out terminal is buried and held in a predetermined position of the insulating case, the insulating case integrated with the electrode lead-out terminal and the electrode lead-out terminal are placed on a heat sink with the circuit board fixed at the predetermined position. The electrode lead-out terminals can be arranged on the circuit board simply and accurately, and the joining of each inner end connection portion and the circuit board can be collectively processed through necessary processes such as solder heat treatment. Can do.

  According to a fifteenth aspect of the present invention, in the electric power according to any one of the first to fourteenth aspects, an interval between the three electrode lead-out terminals is held via an insulating material. Semiconductor device.

  According to the fifteenth aspect of the present invention, since the distance between the electrode lead-out terminals is held via the insulating material, it is possible to reliably insulate even at a narrow distance and hold it at a constant distance.

  According to a sixteenth aspect of the present invention, in the power semiconductor device according to any one of the first to fifteenth aspects, the semiconductor switching element is a MOSFET.

  According to the sixteenth aspect of the present invention, since the MOSFET originally includes a diode in its structure, the MOSFET can normally withstand even without providing an external diode element.

As described above, according to the present invention, the shape and arrangement of the electrode lead-out terminals are excellent in thickness reduction, heat countermeasures, and noise countermeasures.
In particular, the width of the electrode lead-out terminal can be easily increased, and a substantial current path cross-sectional area in the electrode lead-out terminal can be increased while suppressing an imbalance in current density. By effectively increasing the cross-sectional area of the electrode lead-out terminal in this manner, the heat capacity of the electrode lead-out terminal is increased, heat dispersibility and heat dissipation are improved, and the wiring resistance, particularly the heat resistance, is reduced.
Since the three electrode lead-out terminals form a laminated structure, it is possible to partially cancel the inductance due to mutual inductance. Also, by widening the electrode lead-out terminals, the self-inductance is reduced and the self-inductance is reduced. There is an effect that the inductance is reduced by a reduction or self-inductance reduction and an inductance canceling action by mutual inductance.
Furthermore, according to the present invention, it is possible to obtain a power semiconductor device that has a good manufacturing yield, can withstand the environment during use, and has high reliability.
As a result, according to the present invention, even if it is small, there is an effect that it can withstand conversion of a larger current at a higher frequency.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following is one embodiment of the present invention and does not limit the present invention.
FIG. 1 is a plan view (partially transparent) of the power semiconductor device of this embodiment. 2 is a cross-sectional view taken along line AA in FIG. 3 is a cross-sectional view taken along the line BB in FIG. FIG. 4 is a plan view (a) and a front view (b) of an electrode lead-out terminal insert type case. FIG. 5 is a plan view of the P electrode lead-out terminal. FIG. 6 is a plan view of the N electrode lead-out terminal. FIG. 7 is a plan view of the U electrode lead-out terminal. FIG. 8 is an exploded perspective view of the three-electrode lead terminals P, N, and U and the insulating material. FIG. 9 is a plan view of a circuit board (without bonding wires). FIG. 10 is an equivalent circuit diagram of the power semiconductor device of this embodiment. FIG. 11 is a circuit diagram of a drive circuit for a three-phase motor.

  As shown in FIGS. 1 to 3, the power semiconductor device of the present embodiment is configured by assembling the heat radiating plate 1, the two circuit boards 2 </ b> H and 2 </ b> L, and the case 3 to form the circuit shown in FIG. 10. .

As shown in FIG. 4, the case 3 holds the electrode lead terminals 4 to 6 and the control electrode lead terminals 7H, 7L, 8H, and 8L of the P, N, and U electrodes that constitute the stacked portion 11. The electrode lead-out terminals 4 to 6 and the control electrode lead-out terminals 7 and 8 of the P, N, and U electrodes are produced by press-molding a metal plate such as a copper plate, and are subjected to nickel plating or the like. Case 3 is a resin molded product.
As shown in FIGS. 5 and 8 (e), the P electrode lead-out terminal 4 includes a parallel plate portion 4a, a vertical plate portion 4b, an outer end connection portion 4c, and two inner end connection portions 4d and 4e. Can be captured separately.
As shown in FIGS. 6 and 8 (c), the N electrode lead-out terminal 5 is connected to the parallel flat plate portion 5a, the vertical flat plate portion 5b, the outer end connection portion 5c, and the two inner end connection portions 5d and 5e. Can be captured separately.
As shown in FIGS. 7 and 8 (a), the U electrode lead-out terminal 6 includes a parallel plate portion 6a, a vertical plate portion 6b, an outer end connection portion 6c, and four inner end connection portions 6d to 6g. Can be captured separately.
Each parallel flat plate part 4a, 5a, 6a is a flat plate-like part arrange | positioned in parallel with the circuit boards 2H and 2L.
The vertical flat plate portions 4b, 5b, 6b are arranged perpendicular to the circuit boards 2H, 2L, and as shown in FIG. 8, the ends of the parallel flat plate portions 4a, 5a, 6a and the outer end connection portions 4c, 5c, It is a flat part which connects the edge part of 6c.
An external wiring from the high potential side of the power source is connected to the outer end connection portion 4c of the P electrode. The external connection from the low potential side of the power source is connected to the outer end connection portion 5c of the N electrode. An output destination device such as a three-phase motor is connected to the outer end connection portion 6c of the U electrode.

The three outer end connection portions 4 c, 5 c, 6 c are arranged on the upper end surface of the case 3 at the same height. The parallel plate portions 4a, 5a, and 6a are stacked at intervals in the order of P, N, and U from the side closer to the circuit boards 2H and 2L, and the intervals are held by the insulating materials 9 and 10. Therefore, the height difference between the outer end connection portions 4c, 5c, and 6c and the parallel plate portions 4a, 5a, and 6a is large in the order of P, N, and U.
As shown in FIG. 8, the insulating materials 9 and 10 are formed in an L-shaped section with a uniform thickness, and the distance between the vertical flat plate portions 4b, 5b and 6b is also held by the insulating materials 9 and 10. The

The tips of the parallel plate portions 4a, 5a, 6a are arranged at the same position. Therefore, the length of the parallel plate portion is longer in the order of P, N, and U. The three layers P, N, and U are stacked on almost the entire parallel plate portion 5a of the N electrode. A range corresponding to the thickness of the insulating material 10 adjacent to the vertical flat plate portion 5 b of the parallel flat plate portion 5 a is excluded from the laminated portion 11.
The three vertical flat plate portions 4b, 5b, and 6b are partially stacked in a direction parallel to the circuit boards 2H and 2L.

  Bolt insertion holes 4k, 5k, and 6k are formed in the outer end connection portions 4c, 5c, and 6c at the same time along the edge of the case 3 during press forming. Three nuts 23 communicating with these bolt insertion holes 4k, 5k, and 6k, one by one, are embedded in the case 3 in total. These bolt insertion holes 4k, 5k, and 6k and the three nuts 23 have a structure for crimping and connecting a ring-shaped terminal provided at an end portion of the external wiring to the outer end connection portions 4c, 5c, and 6c by bolting. is there.

Each of the inner end connection portions 4d, 4e, 5d, 5e, 6d to 6g has a protruding shape that protrudes in the same plane from the side edge of the laminated portion 11, that is, the side edge of each of the parallel plate portions 4a, 5a, 6a. The part is formed by being bent to the circuit board 2H, 2L side in the middle and further bent to the inner side after that.
For the four inner end connection portions 4d, 4e, 6d, and 6e arranged on one side of the stacked portion 11, from the front end side, the P electrode front end side inner end connection portion 4d, the U electrode front end side inner end connection portion 6d, The base end side inner end connection portion 6e of the U electrode and the base end side inner end connection portion 4e of the P electrode are arranged in this order.
Regarding the four inner end connection portions 5d, 5e, 6f, and 6g arranged on the other side of the laminated portion 11, from the front end side, the front end side inner end connection portion 6f of the U electrode and the front end side inner end connection portion of the N electrode 5d, the base end side inner end connection portion 5e of the N electrode, and the base end side inner end connection portion 6g of the U electrode are arranged in this order.
The front end side end surfaces of the inner end connection portions 4d and 6f on the most front end side coincide with the front ends of the parallel plate portions 4a and 6a, that is, the front end of the stacked portion 11.
The four inner end connecting parts 4d, 4e, 6d, 6e on one side are not arranged at equal intervals, and the inner end connecting part 6d and the inner end connecting part 6e are opened relatively widely, so that The connection portions 4d and 6d and the proximal end inner end connection portions 4e and 6e are arranged so as to be unevenly distributed on the distal end side and the proximal end side.
Similarly, the other four inner end connecting portions 5d, 5e, 6f, 6g on the other side are not arranged at equal intervals, and the inner end connecting portion 5d and the inner end connecting portion 5e are opened relatively large. The distal end inner end connecting portions 5d and 6f and the proximal end inner end connecting portions 5e and 6g are arranged so as to be unevenly distributed on the distal end side and the proximal end side.

As shown in FIG. 4, FIG. 5, etc., the base end portion of the parallel plate portion 4a of the P electrode lead-out terminal 4 is formed so as to protrude from the base end portion of the laminated portion 11 to the opposite side of the inner end connecting portion 4e. 11 is widened from the tip portion having the same width as that of 11. A vertical flat plate portion 4b is continuously formed at the base end portion of the widened parallel flat plate portion 4a through a right-angle fold with the same width, and an end portion on the opposite side to the inner end connection portion 4e of the vertical flat plate portion 4b. The outer end connection portion 4c is coupled through a fold that is perpendicular to each other. The P electrode lead-out terminals 4 are formed in a cross-sectional crank shape by these two foldings being opposite to each other.
Since the base end portion of the parallel plate portion 4a is widened on the opposite side of the inner end connection portion 4e, the portion protruding from the laminated portion 11 of the parallel plate portion 4a and the inner end connection portion 4e do not interfere with each other, and two inner end connections are made. The part which protrudes from the lamination | stacking part 11 of the parallel plate part 4a can be formed large, keeping the space | interval of the parts 4d and 4e wide. The cross-sectional area of the current path from the laminated portion 11 to the outer end connection portion 4c is increased by the portion of the parallel flat plate portion 4a that protrudes from the laminated portion 11 and the vertical flat plate portion 4b.

  As shown in FIGS. 4 and 6, the parallel plate portion 5 a of the N electrode lead-out terminal 5 is formed to have the same width as the stacked portion 11 as a whole. A vertical flat plate portion 5b is continuously formed on the parallel flat plate portion 5a through a right-angle fold with the same width, and an outer end connection portion 5c is connected to a central portion of the vertical flat plate portion 5b through a right-angle fold. . The U-electrode lead-out terminals 5 are formed in a cross-sectional crank shape by these two foldings being in opposite directions.

As shown in FIG. 4, FIG. 7, etc., the base end portion of the parallel flat plate portion 6a of the U electrode lead-out terminal 6 is formed so as to protrude from the base end portion of the laminated portion 11 to the opposite side of the inner end connecting portion 6g. 11 is widened from the tip portion having the same width as that of 11. A vertical flat plate portion 6b is continuously formed at the base end portion of the widened parallel flat plate portion 6a through a right-angle fold with the same width, and an end portion on the opposite side to the inner end connection portion 6g of the vertical flat plate portion 6b. The outer end connection portion 6c is coupled through a fold that is perpendicular to each other. The U-electrode lead-out terminal 6 is formed in a cross-sectional crank shape by these two foldings being opposite to each other.
Since the parallel flat plate portion 6a is widened on the opposite side of the inner end connection portion 6g, the portion protruding from the laminated portion 11 of the parallel plate portion 6a and the inner end connection portion 6g do not interfere with each other, and the two inner end connection portions 6f, 6g. The part which protrudes from the lamination | stacking part 11 of the parallel plate part 6a can be formed large, taking the space | interval of this wide. The cross-sectional area of the current path from the laminated portion 11 to the outer end connecting portion 6c is increased by the portion of the parallel flat plate portion 6a that protrudes from the laminated portion 11 and the vertical flat plate portion 6b.

As shown in FIG. 9, the two circuit boards 2H and 2L have the same circuit pattern. The circuit board 2H is connected between P-U, and 16 MOSFET elements 12H connected between P-U are mounted. The circuit board 2L is connected between U and N, and 16 MOSFET elements 12L connected between U and N are mounted.
The circuit boards 2H and 2L respectively have an insulating substrate 13 and conductor patterns 14, 15 and 16 on the insulating substrate 13. The conductor pattern 14 is connected to the gate electrode of the MOSFET element 12H (12L), the conductor pattern 15 is connected to the source electrode of the MOSFET element 12H (12L), and the conductor pattern 16 is connected to the drain electrode of the MOSFET element 12H (12L). A source conductor pattern 15 is formed in a ring shape around the gate conductor pattern 14, and a drain conductor pattern 16 is formed in a ring shape around the source conductor pattern 15.
On the conductor pattern 14, 16 gate resistance elements 17H (17L) corresponding to the respective MOSFET elements 12H (12L) are attached.
MOSFET element 12H (12L) has the back surface having the drain electrode bonded to conductor pattern 16. The gate electrode and the source electrode of the MOSFET element 12H (12L) are formed on the chip surface, and are connected to the conductor patterns 14 and 15 via bonding wires 18 as shown in the assembly diagram of FIG.

The connection region 24 of the inner end connection portion is shown by a surrounding broken line in FIG. Inner end connection portions 4d and 4e of the P electrode lead-out terminal 4 are joined to the drain conductor pattern 16 on the circuit board 2H side by soldering.
The two inner end connection portions 6d and 6e of the U electrode lead-out terminal 6 are joined to the source conductor pattern 15 on the circuit board 2H side by soldering.
The control electrode lead-out terminal 7H is joined to the gate conductor pattern 14 on the circuit board 2H side via solder. The control electrode lead-out terminal 8H is joined to the source conductor pattern 15 on the circuit board 2H side by soldering.

The other two inner end connection portions 6f and 6g of the U electrode lead-out terminal 6 are joined to the drain conductor pattern 16 on the circuit board 2L side by soldering.
The inner end connection portions 5d and 5e of the N electrode lead-out terminal 5 are joined to the source conductor pattern 15 on the circuit board 2L side by soldering.
The control electrode lead-out terminal 7L is joined to the source conductor pattern 15 on the circuit board 2L side by soldering. The control electrode lead-out terminal 8L is joined to the gate conductor pattern 14 on the circuit board 2L side by soldering.

The control electrode lead-out terminals 7H and 8H are installed on the circuit board 2H, and the control electrode lead-out terminals 7L and 8L are provided on the circuit boards 2H and 2L and three-dimensionally intersect with the laminated portion 11.
When the circuit board having the annular conductor patterns 15 and 16 as described above is not used, the gate conductor pattern and the source conductor pattern are routed on the circuit board, and the control electrode lead terminals 7H, 7L, 8H, and 8L It may be routed to the vicinity of the outer end connection portion held by the case 3 to eliminate the above-mentioned erection structure and crossing structure. Further, a circuit corresponding to the two circuit boards 2H and 2L may be configured on a single circuit board. A single circuit board increases the degree of freedom in routing the conductor pattern.

The inner end connection portion of the control electrode lead-out terminal 7H is dropped onto the circuit board 2H through the inner end connection portions 6d and 6e that are spaced apart by a relatively large distance. The inner end connection portions of the control electrode lead terminals 7L and 8L are dropped onto the circuit board 2L through the inner end connection portions 5d and 5e that are separated by a relatively wide distance.
Concave portions 4h, 5h, and 6h are formed at the same position on one side edge of the electrode lead-out terminals 4 to 6 located above the circuit board 2L. Thus, the inner end connecting portion of the control electrode lead-out terminal 7L is avoided from coming into contact with the electrode lead-out terminals 4-6. When the above-described installation structure or crossing structure is eliminated, the parallel plate portions 4a, 5a, 6a can be formed wider without providing the recesses 4h, 5h, 6h.

In manufacturing, the insulating materials 9 and 10 are formed before the electrode lead-out terminals are laminated by a method of applying a resin to the surface of the electrode lead-out terminal, a method of sticking a pre-formed film-like resin to the surface of the electrode lead-out terminal, or the like. It is preferable to do.
After the insulating material 9 is formed on one of the mating surfaces of the P electrode lead terminal 4 and the N electrode lead terminal 5 by such a method, the P electrode lead terminal 4 and the N electrode lead terminal 5 are matched. On the other hand, after the insulating material 10 is formed on one of the mating surfaces of the N electrode lead-out terminal 5 and the U electrode lead-out terminal 6 in the same manner, the N electrode lead-out terminal 5 and the U electrode lead-out terminal 6 are combined. The electrode lead terminals 4 to 6 are stacked in three layers. Thus, the insulating materials 9 and 10 can be formed thin by the method of installing the insulating materials 9 and 10 before laminating the electrode lead-out terminals. In order to reduce the thickness of the device, the thickness of the insulating materials 9 and 10 is preferably about 0.5 (mm) in order to cancel the inductance by mutual inductance. In this case, the insulating materials 9 and 10 can be formed with a high yield by the above method.
Thereafter, the three layers of electrode lead-out terminals 4 to 6 and the control electrode lead-out terminals 7H, 7L, 8H, and 8L sandwiching the nut 23, the insulating materials 9 and 10 are arranged in a mold for molding the case 3, and the case 3 is resin molded.
As a result, as shown in FIG. 4, the electrode lead-out terminals 4 to 6 and the control electrode lead-out terminals 7H, 7L, 8H, 8L are partly adjacent to the outer end connection part exposed on the upper end surface of the case 3 in a frame shape. It is held and fixed to the case 3 in a state of being buried in the case 3. The electrode lead-out terminals 4 to 6 are held in a state in which almost all of the vertical flat plate portions 4b, 5b, 6b and a part of the base end side of the parallel flat plate portions 4a, 5a, 6a continuous therewith are buried in the case 3. Is done. Further, part of the ends of the parallel flat plate portions 4 a, 5 a, 6 a are also held in a manner that they are sandwiched vertically by a holding portion 19 that is formed to protrude from the inner wall of the case 3.

The insulating materials 9 and 10 can also be formed after the three electrode lead terminals 4 to 6 are stacked by the following method. That is, three layers of electrode lead-out terminals 4 to 6 and control electrode lead-out terminals 7H, 7L, 8H, and 8L without gaps between the nut 23 and the insulating materials 9 and 10 in the mold for molding the case 3 And the case 3 is resin-molded. At the time of this resin molding, the gap between the electrode lead-out terminals 4 to 6 is filled with resin, and the insulating materials 9 and 10 are molded as a part of the case 3.
In this method, if the interval between the electrode lead-out terminals 4 to 6 is narrowed, it becomes difficult to fill the resin. Therefore, it is difficult to form the insulating materials 9 and 10 thinly.
However, the process is simplified because the process of forming the case 3 and the insulating materials 9 and 10 is integrated.
Therefore, when the insulating materials 9 and 10 are formed to be relatively thick, the insulating materials 9 and 10 can be advantageously used when the distance between the electrode lead-out terminals is large enough to cause no problem in resin filling.

The electrode lead-out terminal insert type case 3 produced as described above and the circuit boards 2H and 2L after die bonding and wire bonding are arranged on the heat sink 1 as shown in FIG. The circuit boards 2H and 2L are surrounded by the case 3. The case 3 is fitted to the peripheral edge of the heat sink 1 around the circuit boards 2H and 2L. It is preferable to fix the heat radiating plate 1 and the circuit boards 2H and 2L with a bonding material having good thermal conductivity such as solder. The heat radiating plate 1 and the case 3 are fixed by inserting bolts into holes 20 and 21 provided at four corners and fastening them with bolts and nuts.
The circuit boards 2H and 2L are integrated with the heat sink from the beginning of the formation of an insulating layer such as a ceramic substrate deposited on the heat sink 1 with the heat sink 1 as a base and a conductor pattern layer formed thereon. Things can be used.

The arrangement of the circuit boards 2H and 2L and the case 3 is determined, and each inner end connection portion and the circuit board are soldered. Thereafter, as shown in FIGS. 2 and 3, a resin lid 22 is placed on the upper end opening of the case 3.
The outer end connection portions of all the electrode lead terminals 4 to 6, 7 H, 8 H, 7 L, 8 L are arranged on the upper end surface of the frame-like case 3. Therefore, the lid 22 can be easily attached and detached without interfering with the electrode lead-out terminals. If the lid 22 is removed, the inside can be easily inspected and repaired. Other devices such as a control circuit board connected to the control electrode lead terminals 7H, 8H, 7L, and 8L can be arranged on the lid 22 or in place of the lid 22.

When the plan view of FIG. 1 is observed again, the outer end connection portions 4c, 5c, and 6c of the P, N, and U electrode lead-out terminals 4 to 6 are arranged adjacent to one side of the circuit boards 2H and 2L and outside thereof. The laminated portion 11 is formed so as to extend from the one side to the opposite side. The outer end connecting portions 4c, 5c, 6c are arranged at different positions in the order of P, N, U from right to left on the drawing along the one side.
As shown in the cross-sectional view of FIG. 2, the outer end portions of the three outer end connection portions 4c, 5c, 6c are aligned at the same position, and the three outer end connection portions 4c, 5c, 6c are U, N , P in order.
The electrode lead-out terminals 4 to 6 are bent in a right-angle downward direction from the inner ends of the outer end connection portions 4c, 5c, and 6c at a position close to the inner side in the order of U, N, and P, and are immersed in the case 3. Are bent inward at right angles in the order of U, N, and P in the order of the members of the case 3 and protrude from the inner surface of the case 3 in parallel with the circuit boards 2H and 2L to the holding portion 19 on the opposite side. It is extended and formed to cross. With such a structure, the laminated portion 11 is formed to have a length substantially equivalent to the inner dimension of the case 3.
As shown in FIG. 1, the laminated portion 11 is also arranged above the eight MOSFET elements 12H and the eight MOSFET elements 12L arranged on the center side, and the laminated portion 11 is formed wide.

The power semiconductor device of the present embodiment is used in a drive circuit for a three-phase motor as shown in FIG. Three power semiconductor devices of this embodiment are connected in parallel corresponding to three phases of u phase, v phase, and w phase.
Control signal lines from a control circuit (not shown) are connected to control electrode lead terminals 7H, 7L, 8H, and 8L of the power semiconductor device corresponding to each phase, and the MOSFET circuit 12H and the MOSFET element 12L are controlled by the control circuit. Switch alternately. As is well known, the power semiconductor devices corresponding to each of the u-phase, v-phase, and w-phase are controlled with phases shifted from each other by 120 °, and the three-phase alternating current is shifted by 120 ° in the entire circuit of FIG. Current is output to the three-phase motor M, and the three-phase motor M is driven.

The internal inductance was measured for a product having a rated capacity of 400 to 600 (A) / 100,150 (V) according to the present embodiment.
The plate thickness of each electrode lead-out terminal 4-6 was 1.5 (mm), and the thickness of the insulating materials 9 and 10 was 0.5 (mm). The width of the laminated portion 11 was about 29 (mm), the length was about 61 (mm), and the width of one inner end connecting portion was 4.4 (mm). Others were produced with proportions as shown in FIGS.
Using an LCZ meter, the following internal inductance values were obtained by converting from the back electromotive force of di / dt applied at the switching frequency of 1 kHz to 100 kHz.
15.30 (nH) between the P electrode lead terminal and the U electrode lead terminal, 6.80 (nH) between the U electrode lead terminal and the N electrode lead terminal, and 22.10 (nH) between the P electrode lead terminal and the N electrode lead terminal Thus, a low inductance that can withstand high-speed operation at a frequency of 10 to 12 kHz was obtained.
Further, when the thermal resistance Rth (j to c) between the junction and the case of the MOSFET element was measured, Rth (j to c) = 0.1 (° C./W) was obtained.
Further, when the MOSFET elements 2H and 2L are turned on and a 400 (A) direct current is passed between the P electrode lead-out terminal and the N electrode lead-out terminal for 15 minutes, the surface temperature of the outer end connection portion 4c of the P electrode and the N electrode Both of the outer end connection portions 5c were 74 (° C.).

  The present invention is not limited to the above embodiment, and the semiconductor switch element may be an IGBT (Insulated Gate Bipolar Transistor) instead of the MOSFET. In the case of an IGBT, an external diode element is required in parallel with the IGBT.

1 is a plan view (partially transparent) of a power semiconductor device according to an embodiment of the present invention. It is AA sectional drawing in FIG. It is BB sectional drawing in FIG. It is the top view (a) and front view (b) of the electrode lead-out terminal insert type case which concern on this invention embodiment. It is a top view of the P electrode derivation terminal concerning the embodiment of the present invention. It is a top view of the N electrode derivation terminal concerning the embodiment of the present invention. It is a top view of the U electrode derivation terminal concerning the embodiment of the present invention. FIG. 3 is an exploded perspective view of a P, N, U three-electrode lead terminal and an insulating material according to an embodiment of the present invention. 1 is a plan view of a circuit board (without bonding wires) according to an embodiment of the present invention. 1 is an equivalent circuit diagram of a power semiconductor device according to an embodiment of the present invention. It is a circuit diagram of the drive circuit of a three-phase motor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Heat sink 2H, 2L Circuit board 3 Case 4 P electrode derivation terminal 5 N electrode derivation terminal 6 U electrode derivation terminal 4a, 5a, 6a Parallel flat plate part 4b, 5b, 6b Vertical flat plate part 4c, 5c, 6c Outer end connection part 4d, 4e, 5d, 5e, 6d to 6g Inner end connection portion 7H, 7L, 8H, 8L Control electrode lead-out terminal 9, 10 Insulating material 11 Laminated portion 12H, 12L MOSFET element 13 Insulating substrate 14 Gate conductor pattern 15 Source Conductor pattern 16 Drain conductor pattern 17H, 17L Gate resistance element 18 Bonding wire 20, 21 Hole 22 Lid 23 Nut

Claims (16)

It has a circuit in which output lines to the load are drawn from the mutual connection points of both series-connected semiconductor switching elements connected to power lines from the power supply at both ends, and both the semiconductor switching elements are complementarily controlled to open and close The power semiconductor device that converts the power of the power source and outputs the power to the load,
The high potential side of the power line is P, the low potential side is N, the output line is U, and there are three electrode lead-out terminals corresponding to three electrodes of P, N, U,
The three electrode lead-out terminals are stacked above the circuit board on which the semiconductor switching element is mounted, and are stacked at intervals in the order of P, N, U from the side closer to the circuit board, and at least in the stacked portion, the circuit board A power semiconductor device, characterized in that the power semiconductor device is formed in a flat plate shape parallel to the substrate. The power semiconductor device according to claim 1, wherein the stacked portion is disposed above one or more semiconductor switching elements. The outer end connection part to which the external wiring of each electrode lead-out terminal of P, N, U is connected is arranged on the outside adjacent to one side of the circuit board when the circuit board is viewed vertically, The power semiconductor device according to claim 1, wherein the stacked portion is formed so as to extend from the one side to the opposite side. One or more inner end connecting portions connected to the circuit board of the P, N, and U electrode lead-out terminals are formed so as to protrude from the side edge of the laminated portion, bend toward the circuit board side, and further. 4. The power semiconductor device according to claim 1, wherein the power semiconductor device is a projection bent inward. The lower end part bent inside the inner end connection part of each electrode of P, N, U is joined to the conductor pattern on the circuit board,
The semiconductor switching element connected between P-U is joined to a conductor pattern to which the inner end connection portion of the P electrode is joined,
The surface main electrode of the semiconductor switching element connected between the P-U and the conductor pattern to which the inner end connection portion of the U electrode is connected via a bonding wire,
The semiconductor switching element connected between U and N is joined to a conductor pattern to which the inner end connection portion of the U electrode is joined,
5. The main surface electrode of the semiconductor switching element connected between the U and N and a conductor pattern to which an inner end connection portion of the N electrode is joined are connected via a bonding wire. Power semiconductor devices. Outer end connection portions to which external wirings of the electrode lead-out terminals of P, N, and U are connected are arranged at different positions in the order of P, N, and U along one side of the circuit board,
The outer end connection portion of the N electrode is within the formation range of the stacked portion along the one side,
All or part of the outer end connection portion of the P electrode and the outer end connection portion of the U electrode are outside the formation range of the stacked portion along the one side,
The P-electrode lead-out terminal and the U-electrode lead-out terminal have a portion that protrudes out of the range in the direction along the one side from the end of the stacked portion on the one side and is connected to the outer end connection portion. 6. The power semiconductor device according to claim 5, wherein: The fold along the one side is formed in a portion from the outer end connection portion to the laminated portion along the one side of the P electrode lead-out terminal and the U electrode lead-out terminal. Power semiconductor device. 8. The power semiconductor device according to claim 6, wherein an inner end connection portion of the P electrode is formed on the opposite side of the outer end connection portion of the P electrode through the stacked portion. 9. The power semiconductor device according to claim 8, wherein the inner end connecting portion of the N electrode is formed on the opposite side of the inner end connecting portion of the P electrode through the stacked portion. The inner end connection part of the U electrode is formed on both sides of the laminated part,
The inner end connection portion of the U electrode joined to the surface main electrode of the semiconductor switching element connected between the P-U and the conductor pattern connected via the bonding wire is an inner end connection portion of the P electrode. Formed on the same side,
The inner end connection portion of the U electrode joined to the conductor pattern to which the semiconductor switching element connected between U and N is joined is formed on the same side as the inner end connection portion of the N electrode. A power semiconductor device according to claim 9. One inner end connection part of the P electrode is located on the tip side of the laminated part, and one or more inner end connection parts of the U electrode formed on the same side as the inner end connection part of the P electrode are 11. The power semiconductor device according to claim 10, wherein the power semiconductor device is located closer to a proximal end side of the stacked portion than one inner end connection portion of the P electrode located on the distal end side. One inner end connection portion of the U electrode formed on the same side as the inner end connection portion of the N electrode is located on the tip side of the stacked portion, and all of one or more inner end connection portions of the N electrode are 11. The power semiconductor device according to claim 10, wherein the power semiconductor device is located closer to the proximal end side of the stacked portion than one inner end connection portion of the U electrode located on the distal end side. 13. The inner end connecting portion of each of the P, N, and U electrodes is provided so as to be distributed to the distal end side and the proximal end side by two or more on the same side edge, respectively. The power semiconductor device according to any one of the above. A heat sink having a surface in contact with the back surface of the circuit board; and a frame-like insulating case that is fixed to an edge of the heat sink around the circuit board and surrounds the circuit board. 14. The power semiconductor device according to claim 1, wherein the lead-out terminal is held by being partially buried in the insulating case. The power semiconductor device according to claim 1, wherein an interval between the three electrode lead-out terminals is held via an insulating material. The power semiconductor device according to any one of claims 1 to 15, wherein the semiconductor switching element is a MOSFET.

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