JP5123162B2 - Power semiconductor device and manufacturing method thereof - Google Patents

Power semiconductor device and manufacturing method thereof Download PDF

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JP5123162B2
JP5123162B2 JP2008334110A JP2008334110A JP5123162B2 JP 5123162 B2 JP5123162 B2 JP 5123162B2 JP 2008334110 A JP2008334110 A JP 2008334110A JP 2008334110 A JP2008334110 A JP 2008334110A JP 5123162 B2 JP5123162 B2 JP 5123162B2
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electrode lead
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JP2010157565A (en
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康志 根本
紳一郎 鶴島
哲也 須藤
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日本インター株式会社
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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Description

本発明は、両端に電源からの電力線が接続される直列接続の両半導体スイッチング素子の互いの接続点から負荷への出力線を引き出した回路を有し、前記両半導体スイッチング素子が相補的に開閉制御されることにより、前記電源の電力を変換して前記負荷へ出力する電力用半導体装置に係り、特に大電力用途に適した配線構造を有するものに関する。   The present invention has a circuit in which an output line to a load is drawn from a connection point of two series-connected semiconductor switching elements in which power lines from a power source are connected to both ends, and both the semiconductor switching elements are complementarily opened and closed The present invention relates to a power semiconductor device that converts the power of the power source by being controlled and outputs the converted power to the load, and particularly relates to a device having a wiring structure suitable for high power use.

従来、電力用半導体装置において、より大電流をより高周波数で変換することが要求されるに従って増大する電力損失、発熱、破壊、ノイズによる誤動作等の諸問題を解決するために、配線インダクタンスの低減が一解決手法となっている(特許文献1〜5等)。
半導体スイッチング素子としては、主にMOSFET、IGBTなどのトランジスタが用いられている。大電力用途の半導体装置としては、電動ホークリフトなどの3相モータ駆動回路が挙げられる。車両やリフトなどの電動機の高出力化、騒音対策等により 大電流を高周波数(ホークリフトについては10kHz以上)で変換することが要求されている。
Conventionally, in order to solve various problems such as power loss, heat generation, breakdown, malfunction due to noise, etc., which increase as a larger current is required to be converted at a higher frequency in power semiconductor devices, the wiring inductance is reduced. Is a solution (Patent Documents 1 to 5 etc.).
As semiconductor switching elements, transistors such as MOSFETs and IGBTs are mainly used. As a semiconductor device for high power use, there is a three-phase motor drive circuit such as an electric hawk lift. It is required to convert a large current at a high frequency (10 kHz or more for a hawk lift) to increase the output of electric motors such as vehicles and lifts and to take measures against noise.

互いの接続点に出力線が接続され両端に電力線が接続される直列両半導体スイッチング素子の回路は、特許文献1〜3に記載されている。
特許文献1においては、その図10に回路図が示され、その図1〜3等に装置外観図が示されている。特許文献1の図11に示されるように、3相モータの駆動回路においては、直列両半導体スイッチング素子の回路がu相、v相、w相に対応して3セット構成される。
特許文献1〜3記載の装置においては、電力線の高電位側をP、低電位側をN、出力線をUとして、これら3電極に対応する平板状の電極導出端子(電極を外部への導出する導体)が平行配置されている。
Patent Documents 1 to 3 describe circuits of both series semiconductor switching elements in which an output line is connected to each other connection point and a power line is connected to both ends.
In Patent Document 1, a circuit diagram is shown in FIG. 10 and an external view of the apparatus is shown in FIGS. As shown in FIG. 11 of Patent Document 1, in the drive circuit of the three-phase motor, three sets of series semiconductor switching element circuits are configured corresponding to the u-phase, v-phase, and w-phase.
In the devices described in Patent Literatures 1 to 3, the high potential side of the power line is P, the low potential side is N, and the output line is U. The flat electrode lead-out terminals corresponding to these three electrodes (the electrodes are led out to the outside) Are arranged in parallel.

特許文献1〜3記載の発明においては、P,U,Nの電極導出端子を幅広な平板状とすることにより、自己インダクタンスを低減するとともに、逆方向に電流が流れる電極導出端子同士を所定の間隔に近接配置して相互インダクタンスを相殺作用により低減し、もって配線インダクタンスの低減を図らんとするものと解される。
特許文献6に公開されているように、本件出願人も同様の理論に基づく配線インダクタンスの低減等を目的として、P,N,Uの3つの電極導出端子(4,5,6)が、半導体スイッチング素子が実装される回路基板(2H,2L)の上空で、絶縁材(9,10)を介して間隔を隔てて積層され、少なくともその積層部で回路基板と平行な平板状に形成されてなる構造を採用した電力用半導体装置を出願した。
In the inventions described in Patent Documents 1 to 3, the electrode lead-out terminals of P, U, and N are formed in a wide flat plate shape, so that self-inductance is reduced and the electrode lead-out terminals through which current flows in the opposite direction are connected to each other. It is understood that the mutual inductance is reduced by the canceling action by being arranged close to the interval, thereby reducing the wiring inductance.
As disclosed in Patent Document 6, the present applicant also has three electrode lead terminals (4, 5, 6) of P, N, and U for the purpose of reducing wiring inductance based on the same theory. Over the circuit boards (2H, 2L) on which the switching elements are mounted, they are laminated at intervals through insulating materials (9, 10), and are formed in a flat plate shape parallel to the circuit board at least in the laminated parts. An application for a power semiconductor device adopting the following structure was filed.

すなわち、特許文献6記載の発明においては、P電極導出端子と、N電極導出端子と、U電極導出端子と、P電極導出端子とN電極導出端子と間に配置される絶縁材と、N電極導出端子とU電極導出端子と間に配置される絶縁材とからなる5層構造体が採用された。そして、相互インダクタンスの相殺効果を得るために絶縁材の厚みが例えば0.5mmと薄くなる。この5層構造体を製作する方法としては特許文献6段落0064に記載されるように、予め電極導出端子の表面に樹脂を塗布又は樹脂フイルムを貼付した上で積層する方法と、特許文献6段落0065に記載される電極導出端子間の隙間に樹脂を充填する方法を提示した。
特許第3053298号公報 特開2001−332688号公報 特開2004−214452号公報 特開平11−177021号公報 特開平11−177018号公報 特開2006−210500号公報
That is, in the invention described in Patent Document 6, a P electrode lead terminal, an N electrode lead terminal, a U electrode lead terminal, an insulating material disposed between the P electrode lead terminal and the N electrode lead terminal, and the N electrode A five-layer structure composed of an insulating material disposed between the lead terminal and the U electrode lead terminal was employed. In order to obtain a mutual inductance canceling effect, the thickness of the insulating material becomes as thin as 0.5 mm, for example. As a method for manufacturing this five-layer structure, as described in paragraph 0064 of Patent Document 6, a method of laminating after applying a resin or applying a resin film to the surface of the electrode lead-out terminal in advance, and paragraph 6 of Patent Document 6 The method of filling the gap between the electrode lead-out terminals described in 0065 with a resin was presented.
Japanese Patent No. 3053298 JP 2001-332688 A JP 2004-214452 A Japanese Patent Laid-Open No. 11-177021 JP-A-11-177018 JP 2006-210500 A

特許文献6にも記載されるように、電極導出端子間の隙間が狭い場合には、電極導出端子間の隙間に樹脂を充填する方法によると、端子間に樹脂未充填の空隙を残すことがあるため好ましくない。本発明者らはこのような問題が少なく製造精度及び製造効率を追求が望める絶縁樹脂シートを端子間に挟んで積層する方法を研究するに至ったが以下に説明することが課題となった。
まず、電極導出端子、制御用端子の位置精度の信頼性を確保し、半導体スイッチング素子が実装される回路基板への確実な接続、配線インダクタンスの低減等の所望の性能を達成する必要がある。また、電極導出端子間に配置される絶縁樹脂シートの位置精度の信頼性を確保し、絶縁信頼性を確保する必要がある。
As described in Patent Document 6, when the gap between the electrode lead-out terminals is narrow, according to the method of filling the gap between the electrode lead-out terminals with a resin, a resin-unfilled gap may be left between the terminals. This is not preferable. The present inventors have studied a method of laminating and sandwiching an insulating resin sheet between the terminals, which has few such problems and is desired to pursue manufacturing accuracy and manufacturing efficiency, but it has become a problem to be described below.
First, it is necessary to secure the reliability of the positional accuracy of the electrode lead-out terminal and the control terminal, and to achieve desired performance such as reliable connection to a circuit board on which the semiconductor switching element is mounted and reduction of wiring inductance. Moreover, it is necessary to ensure the reliability of the positional accuracy of the insulating resin sheet disposed between the electrode lead-out terminals and to ensure the insulation reliability.

本発明者らの研究によれば、図18に示すように、P電極導出端子4と、N電極導出端子5と、U電極導出端子6と、P電極導出端子とN電極導出端子と間に配置される絶縁樹脂シート9と、N電極導出端子とU電極導出端子と間に配置される絶縁樹脂シート10とからなる5層構造体を、金型41〜44で型閉めし樹脂を充填して樹脂ケースを成型する際に次の問題が生じた。
図18(a)に示すように、P電極導出端子4の縁の端面位置とN電極導出端子5の縁の端面位置とが一致する構造、N電極導出端子5の縁の端面位置とU電極導出端子6の縁の端面位置とが一致する構造がある。また、図18(b)に示すように、P電極導出端子4の縁の端面位置とN電極導出端子5の縁の端面位置とU電極導出端子6の縁の端面位置とが一致する構造がある。
このような隣接する端子の縁の端面位置が一致する構造においては、絶縁樹脂シート9又は10の縁部に沿った各端子間の沿面絶縁距離を十分に確保するために、絶縁樹脂シート9,10の縁部を端子の縁の端面位置より外へ突出させる必要がある。
しかしこの場合には、図18に示すように、型閉め時に、型41,42,43又は44が端子4,5又は6から突出した絶縁樹脂シート9又は10の縁部に干渉して、絶縁樹脂シート9又は10の縁部が損傷、破損するおそれがあり、製造歩留まりを低下させてしまうという問題が生じた。かかる問題は、端子4,5,6及び絶縁樹脂シート9,10の位置精度を向上するだけでは、払拭することはできない。
According to the study by the present inventors, as shown in FIG. 18, between the P electrode lead terminal 4, the N electrode lead terminal 5, the U electrode lead terminal 6, and the P electrode lead terminal and the N electrode lead terminal. A five-layer structure composed of the insulating resin sheet 9 to be disposed and the insulating resin sheet 10 disposed between the N electrode lead terminal and the U electrode lead terminal is closed with molds 41 to 44 and filled with resin. The following problems occurred when molding the resin case.
As shown in FIG. 18 (a), a structure in which the end face position of the edge of the P electrode lead-out terminal 4 and the end face position of the edge of the N electrode lead-out terminal 5 coincide, the end face position of the edge of the N electrode lead-out terminal 5 and the U electrode There is a structure in which the end face position of the edge of the lead-out terminal 6 matches. Further, as shown in FIG. 18 (b), there is a structure in which the end face position of the edge of the P electrode lead terminal 4, the end face position of the edge of the N electrode lead terminal 5, and the end face position of the edge of the U electrode lead terminal 6 are coincident. is there.
In such a structure in which the end face positions of the edges of the adjacent terminals coincide with each other, in order to sufficiently ensure the creeping insulation distance between the terminals along the edge of the insulating resin sheet 9 or 10, the insulating resin sheet 9, It is necessary to project 10 edge portions outward from the end face position of the edge of the terminal.
However, in this case, as shown in FIG. 18, when the mold is closed, the mold 41, 42, 43 or 44 interferes with the edge of the insulating resin sheet 9 or 10 protruding from the terminal 4, 5 or 6, thereby insulating the mold. The edge of the resin sheet 9 or 10 may be damaged or broken, resulting in a problem that the manufacturing yield is lowered. Such a problem cannot be eliminated only by improving the positional accuracy of the terminals 4, 5, 6 and the insulating resin sheets 9, 10.

本発明は以上の従来技術における問題に鑑みてなされたものであって、3枚の電極導出端子とこれらの間に配置される2枚の絶縁樹脂シートとからなる5層構造体を備えた電力用半導体装置において、前記端子間の絶縁樹脂シートの縁部に沿った沿面絶縁距離を十分に確保しつつ、製造歩留まりの向上、導体部材及び絶縁部材の位置精度の向上を図ることを課題とする。   The present invention has been made in view of the above problems in the prior art, and includes a power having a five-layer structure including three electrode lead-out terminals and two insulating resin sheets disposed therebetween. An object of the present invention is to improve the manufacturing yield and the positional accuracy of the conductor member and the insulating member while ensuring a sufficient creeping insulation distance along the edge of the insulating resin sheet between the terminals in the semiconductor device. .

以上の課題を解決するための請求項1記載の発明は、両端に電源からの電力線が接続される直列接続の両半導体スイッチング素子の互いの接続点から負荷への出力線を引き出した回路を有し、前記両半導体スイッチング素子が相補的に開閉制御されることにより、前記電源の電力を変換して前記負荷へ出力する電力用半導体装置であって、
前記電力線の高電位側をP、低電位側をN、前記出力線をUとして、P,N,Uの3電極に対応する3枚の電極導出端子と、2枚の絶縁樹脂シートとを有し、
前記3枚の電極導出端子が、前記半導体スイッチング素子が実装される回路基板の上空で、前記絶縁樹脂シートを介して積層され、少なくともその積層部で前記回路基板と平行な平板状に形成されてなり、
前記積層部において、前記絶縁樹脂シートに隣接する一方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置より内側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置と一致又は該位置の外側に配置され
前記積層部に前記3枚の電極導出端子及び前記2枚の絶縁樹脂シートのそれぞれを貫通する孔が積層されてなる積層孔が形成され、
前記積層孔の内周において、前記絶縁樹脂シートに隣接する一方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置より外側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置と一致又は該位置の内側に配置され、
一の前記積層孔を構成する前記3枚の電極導出端子の各孔が一定の積層方向に沿って次第に大きくなる大小関係を有して形成されてなることを特徴とする電力用半導体装置である。
The invention described in claim 1 for solving the above-described problems has a circuit in which an output line to a load is drawn from a connection point between two series-connected semiconductor switching elements in which power lines from a power source are connected to both ends. The power semiconductor device that converts the power of the power source and outputs the power to the load by complementary open / close control of the semiconductor switching elements,
With the high potential side of the power line as P, the low potential side as N, and the output line as U, there are three electrode lead-out terminals corresponding to the three electrodes P, N, and U, and two insulating resin sheets. And
The three electrode lead-out terminals are stacked above the circuit board on which the semiconductor switching element is mounted via the insulating resin sheet, and are formed in a flat plate shape parallel to the circuit board at least in the stacked portion. Become
In the laminated portion, the other electrode lead-out terminal adjacent to the insulating resin sheet is arranged such that the end face position of the edge of one electrode lead-out terminal adjacent to the insulating resin sheet is located inside the end face position of the edge of the insulating resin sheet. The end face position of the edge of the insulating resin sheet is aligned with the end face position of the edge of the insulating resin sheet or arranged outside the position ,
A laminated hole is formed by laminating holes through each of the three electrode lead-out terminals and the two insulating resin sheets in the laminated portion,
In the inner periphery of the laminated hole, the end surface position of the inner edge of one electrode lead-out terminal adjacent to the insulating resin sheet is disposed outside the end surface position of the inner edge of the insulating resin sheet, and the other end adjacent to the insulating resin sheet. The end face position of the inner edge of the electrode lead-out terminal coincides with the end face position of the inner edge of the insulating resin sheet or is arranged inside the position,
1. The power semiconductor device according to claim 1, wherein each of the three electrode lead-out terminals constituting one of the stacked holes is formed to have a size relationship that gradually increases along a certain stacking direction. .

請求項記載の発明は、両端に電源からの電力線が接続される直列接続の両半導体スイッチング素子の互いの接続点から負荷への出力線を引き出した回路を有し、前記両半導体スイッチング素子が相補的に開閉制御されることにより、前記電源の電力を変換して前記負荷へ出力する電力用半導体装置であって、
前記電力線の高電位側をP、低電位側をN、前記出力線をUとして、P,N,Uの3電極に対応する3枚の電極導出端子と、2枚の絶縁樹脂シートとを有し、
前記3枚の電極導出端子が、前記半導体スイッチング素子が実装される回路基板の上空で、前記絶縁樹脂シートを介して積層され、少なくともその積層部で前記回路基板と平行な平板状に形成されてなり、
前記積層部において、前記絶縁樹脂シートに隣接する一方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置より内側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置と一致又は該位置の外側に配置され、
前記積層部に前記3枚の電極導出端子及び前記2枚の絶縁樹脂シートのそれぞれを貫通する孔が積層されてなる積層孔が形成され、
前記積層孔の内周において、前記絶縁樹脂シートに隣接する一方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置より外側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置と一致又は該位置の内側に配置され、
前記回路基板を包囲する枠状で前記3つの電極導出端子の一部を埋没させてこれらを保持する樹脂ケースを有し、
前記半導体スイッチング素子のスイッチングを制御するための制御用電極導出端子が前記積層部の上空で前記3つの電極導出端子に交差する構造を有し、
前記樹脂ケースから延設されて連続して形成された樹脂部が、前記積層部の上空で前記制御用電極導出端子を保持するとともに一の前記積層孔に入ってその内面に付着形成されてなる電力用半導体装置である。
The invention according to claim 2 has a circuit in which an output line to a load is drawn from a mutual connection point of both semiconductor switching elements connected in series, to which power lines from a power source are connected at both ends. A power semiconductor device that converts the power of the power source and outputs it to the load by complementary opening and closing control,
With the high potential side of the power line as P, the low potential side as N, and the output line as U, there are three electrode lead-out terminals corresponding to the three electrodes P, N, and U, and two insulating resin sheets. And
The three electrode lead-out terminals are stacked above the circuit board on which the semiconductor switching element is mounted via the insulating resin sheet, and are formed in a flat plate shape parallel to the circuit board at least in the stacked portion. Become
In the laminated portion, the other electrode lead-out terminal adjacent to the insulating resin sheet is arranged such that the end face position of the edge of one electrode lead-out terminal adjacent to the insulating resin sheet is located inside the end face position of the edge of the insulating resin sheet. The end face position of the edge of the insulating resin sheet is aligned with the end face position of the edge of the insulating resin sheet or arranged outside the position,
A laminated hole is formed by laminating holes through each of the three electrode lead-out terminals and the two insulating resin sheets in the laminated portion,
In the inner periphery of the laminated hole, the end surface position of the inner edge of one electrode lead-out terminal adjacent to the insulating resin sheet is disposed outside the end surface position of the inner edge of the insulating resin sheet, and the other end adjacent to the insulating resin sheet. The end face position of the inner edge of the electrode lead-out terminal coincides with the end face position of the inner edge of the insulating resin sheet or is arranged inside the position,
A resin case that holds and retains a part of the three electrode lead-out terminals in a frame shape surrounding the circuit board;
The control electrode lead-out terminal for controlling the switching of the semiconductor switching element has a structure that intersects the three electrode lead-out terminals above the stacked portion,
The resin part continuously extended from the resin case is formed so as to hold the control electrode lead-out terminal above the laminated part and to be attached to the inner surface of the one laminated hole. it is a semiconductor device that power.

請求項記載の発明は、両端に電源からの電力線が接続される直列接続の両半導体スイッチング素子の互いの接続点から負荷への出力線を引き出した回路を有し、前記両半導体スイッチング素子が相補的に開閉制御されることにより、前記電源の電力を変換して前記負荷へ出力する電力用半導体装置であって、
前記電力線の高電位側をP、低電位側をN、前記出力線をUとして、P,N,Uの3電極に対応する3枚の電極導出端子と、2枚の絶縁樹脂シートとを有し、
前記3枚の電極導出端子が、前記半導体スイッチング素子が実装される回路基板の上空で、前記絶縁樹脂シートを介して積層され、少なくともその積層部で前記回路基板と平行な平板状に形成されてなり、
前記積層部において、前記絶縁樹脂シートに隣接する一方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置より内側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置と一致又は該位置の外側に配置され、
前記積層部に前記3枚の電極導出端子及び前記2枚の絶縁樹脂シートのそれぞれを貫通する孔が積層されてなる積層孔が形成され、
前記積層孔の内周において、前記絶縁樹脂シートに隣接する一方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置より外側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置と一致又は該位置の内側に配置されてなる電力用半導体装置の製造方法であって、
前記3枚の電極導出端子を前記絶縁樹脂シートを介して積層して3枚の電極導出端子と2枚の絶縁樹脂シートとからなる5層構造体を構成する工程と、
前記5層構造体に構成される2以上の前記積層孔に位置決めピンを挿入して層間の相対位置を位置決めする工程と、
前記位置決めピンを成形型に固定する工程と、
前記位置決めピンにより位置決め固定された前記5層構造体を前記成形型に収めて型閉めする工程と、
型閉めされた前記成形型に樹脂を充填し前記3枚の電極導出端子の一部に付着する樹脂ケースを成型する工程とを備える電力用半導体装置の製造方法である。
The invention according to claim 3 has a circuit in which an output line to the load is drawn from a connection point between the two semiconductor switching elements connected in series, to which power lines from the power supply are connected at both ends. A power semiconductor device that converts the power of the power source and outputs it to the load by complementary opening and closing control,
With the high potential side of the power line as P, the low potential side as N, and the output line as U, there are three electrode lead-out terminals corresponding to the three electrodes P, N, and U, and two insulating resin sheets. And
The three electrode lead-out terminals are stacked above the circuit board on which the semiconductor switching element is mounted via the insulating resin sheet, and are formed in a flat plate shape parallel to the circuit board at least in the stacked portion. Become
In the laminated portion, the other electrode lead-out terminal adjacent to the insulating resin sheet is arranged such that the end face position of the edge of one electrode lead-out terminal adjacent to the insulating resin sheet is located inside the end face position of the edge of the insulating resin sheet. The end face position of the edge of the insulating resin sheet is aligned with the end face position of the edge of the insulating resin sheet or arranged outside the position,
A laminated hole is formed by laminating holes through each of the three electrode lead-out terminals and the two insulating resin sheets in the laminated portion,
In the inner periphery of the laminated hole, the end surface position of the inner edge of one electrode lead-out terminal adjacent to the insulating resin sheet is disposed outside the end surface position of the inner edge of the insulating resin sheet, and the other end adjacent to the insulating resin sheet. An end surface position of the inner edge of the electrode lead-out terminal is the same as the end surface position of the inner edge of the insulating resin sheet, or a manufacturing method of a power semiconductor device arranged inside the position ,
Laminating the three electrode lead-out terminals via the insulating resin sheet to form a five-layer structure comprising three electrode lead-out terminals and two insulating resin sheets;
Inserting a positioning pin into two or more of the laminated holes configured in the five-layer structure to position a relative position between layers;
Fixing the positioning pin to a mold; and
Storing the five-layer structure positioned and fixed by the positioning pin in the mold and closing the mold;
A method of manufacturing a power semiconductor device comprising: filling a mold in a closed mold and molding a resin case attached to a part of the three electrode lead-out terminals.

請求項記載の発明は、請求項に記載の電力用半導体装置の製造方法であって、
前記3枚の電極導出端子を前記絶縁樹脂シートを介して積層して3枚の電極導出端子と2枚の絶縁樹脂シートとからなる5層構造体を構成する工程と、
前記5層構造体に構成される2以上の前記積層孔に、各電極導出端子の孔に嵌合する外径を有した3段状の位置決めピンを、最も大きな孔を有する前記電極導出端子側から挿入して層間の相対位置を位置決めする工程と、
前記位置決めピンを成形型に固定する工程と、
前記位置決めピンにより位置決め固定された前記5層構造体を前記成形型に収めて型閉めする工程と、
型閉めされた前記成形型に樹脂を充填し前記3枚の電極導出端子の一部に付着する樹脂ケースを成型する工程とを備える電力用半導体装置の製造方法である。
Invention of Claim 4 is a manufacturing method of the semiconductor device for electric power of Claim 1 , Comprising:
Laminating the three electrode lead-out terminals via the insulating resin sheet to form a five-layer structure comprising three electrode lead-out terminals and two insulating resin sheets;
In the two or more laminated holes configured in the five-layer structure, a three-stage positioning pin having an outer diameter that fits into the hole of each electrode lead-out terminal, the electrode lead-out terminal side having the largest hole Inserting the relative position between the layers,
Fixing the positioning pin to a mold; and
Storing the five-layer structure positioned and fixed by the positioning pin in the mold and closing the mold;
A method of manufacturing a power semiconductor device comprising: filling a mold in a closed mold and molding a resin case attached to a part of the three electrode lead-out terminals.

請求項記載の発明は、請求項に記載の電力用半導体装置の製造方法であって、
前記3枚の電極導出端子を前記絶縁樹脂シートを介して積層して3枚の電極導出端子と2枚の絶縁樹脂シートとからなる5層構造体を構成する工程と、
前記5層構造体に構成される2以上の前記積層孔に位置決めピンを挿入して層間の相対位置を位置決めするとともに、他の位置決めピンを前記制御用電極導出端子の下方に配置される前記積層孔に下から挿入して上端部を当該積層孔から上方へ突出させて前記制御用電極導出端子に接触させることにより当該制御用電極導出端子を支持し、前記5層構造体に対する前記制御用電極導出端子の相対位置を位置決めする工程と、
前記位置決めピンを成形型に固定する工程と、
前記位置決めピンにより位置決め固定された前記5層構造体及び前記制御用電極導出端子を前記成形型に収めて型閉めする工程と、
型閉めされた前記成形型に樹脂を充填し前記3枚の電極導出端子及び前記制御用電極導出端子の一部に付着する樹脂ケースと、前記樹脂ケースから延設されて連続して形成され、前記積層部の上空で前記制御用電極導出端子を保持するとともに、当該制御用電極導出端子下方の前記他の位置決めピンとこれが挿入される積層孔との隙間に入って当該積層孔の内面に付着する樹脂部を成型する工程とを備える電力用半導体装置の製造方法である。
Invention of Claim 5 is a manufacturing method of the semiconductor device for electric power of Claim 2 , Comprising:
Laminating the three electrode lead-out terminals via the insulating resin sheet to form a five-layer structure comprising three electrode lead-out terminals and two insulating resin sheets;
The laminated layer in which positioning pins are inserted into two or more laminated holes configured in the five-layer structure to position relative positions between the layers, and another positioning pin is disposed below the control electrode lead-out terminal The control electrode lead-out terminal is supported by inserting the hole into the hole from below and projecting the upper end portion upward from the laminated hole to contact the control electrode lead-out terminal, and the control electrode for the five-layer structure Positioning the relative position of the lead terminal;
Fixing the positioning pin to a mold; and
Storing the five-layer structure positioned and fixed by the positioning pin and the control electrode lead-out terminal in the mold, and closing the mold;
A resin case that is filled with resin in the mold that is closed and adheres to a part of the three electrode lead-out terminals and the control electrode lead-out terminal, and is continuously formed extending from the resin case, The control electrode lead-out terminal is held above the stack portion, and enters the gap between the other positioning pin below the control electrode lead-out terminal and the stack hole into which it is inserted, and adheres to the inner surface of the stack hole. And a step of molding a resin part.

本件請求項1記載の発明によれば、3枚の電極導出端子と2枚の絶縁樹脂シートとからなる5層構造体の積層部において、絶縁樹脂シートに隣接する一方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置より内側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置と一致又は該位置の外側に配置されているので、一方の電極導出端子の縁から絶縁樹脂シートの縁部に沿って他方の電極導出端子に至る沿面絶縁距離が、絶縁樹脂シートの厚みより長く確保され、沿面絶縁距離を十分に確保することができるという効果がある。
また本件請求項1記載の発明によれば、絶縁樹脂シートの縁部は突出せず、片側の電極導出端子に沿って延在するから、型閉め時に型が絶縁樹脂シートの縁部に干渉しても、この縁部は片側の電極導出端子で支持され、この縁部の損傷、破損が抑えられるという効果があり、もって製造歩留まりを向上することができるという効果がある。
According to the first aspect of the present invention, in the laminated portion of the five-layer structure composed of three electrode lead terminals and two insulating resin sheets, the edge of one electrode lead terminal adjacent to the insulating resin sheet The end surface position is arranged inside the end surface position of the edge of the insulating resin sheet, and the end surface position of the edge of the other electrode lead-out terminal adjacent to the insulating resin sheet matches or matches the end surface position of the edge of the insulating resin sheet. The creeping insulation distance from the edge of one electrode lead-out terminal to the other electrode lead-out terminal along the edge of the insulating resin sheet is ensured to be longer than the thickness of the insulating resin sheet. There is an effect that a sufficient distance can be secured.
Further, according to the present invention, since the edge of the insulating resin sheet does not protrude and extends along the electrode lead-out terminal on one side, the mold interferes with the edge of the insulating resin sheet when the mold is closed. However, this edge portion is supported by the electrode lead-out terminal on one side, and there is an effect that damage and breakage of this edge portion can be suppressed, and thus the manufacturing yield can be improved.

本件請求項又は3,4に記載の発明によれば、5層構造体に構成される積層孔に位置決めピンを挿入して成形型に固定することにより、5層構造体の層間の相対位置の位置精度、成形型(従って樹脂部)に対する位置精度を向上することができるという効果があり、型閉め時に型が絶縁樹脂シートの縁部に干渉することの発生率を抑えることができる。 According to the first or third or fourth aspect of the present invention, the relative position between the layers of the five-layer structure is obtained by inserting the positioning pin into the laminated hole formed in the five-layer structure and fixing the pin to the mold. The positional accuracy with respect to the molding die (and hence the resin portion) can be improved, and the rate of occurrence of interference of the die with the edge of the insulating resin sheet when the die is closed can be suppressed.

本件請求項又はに記載の発明によれば、位置決めピンにより精度良く位置決め固定された3枚の電極導出端子、2枚の絶縁樹脂シート及び上空に交差する制御用電極端子が樹脂ケースに連続する樹脂部によって一体に連結固定されるので、これら各部が樹脂部を介して連結固定された強固な構造により各部の位置が精度良く固定され、維持することができ、従って、一方の電極導出端子の縁から絶縁樹脂シートの縁部に沿って他方の電極導出端子に至る沿面絶縁距離や、電極導出端子と制御用電極導出端子との間の距離も精度良く確保し維持することができるという効果がある。したがって、後に続く組立工程を精度良く行なうことができる。 According to the second or fifth aspect of the present invention, the three electrode lead-out terminals, the two insulating resin sheets, and the control electrode terminals that intersect the sky are continuously connected to the resin case. Since these parts are integrally connected and fixed by the resin part, the position of each part can be accurately fixed and maintained by a strong structure in which these parts are connected and fixed via the resin part. The creeping insulation distance from the edge of the insulating resin sheet to the other electrode lead-out terminal along the edge of the insulating resin sheet and the distance between the electrode lead-out terminal and the control electrode lead-out terminal can be ensured and maintained with high accuracy. There is. Therefore, the subsequent assembly process can be performed with high accuracy.

以下に本発明の一実施の形態につき図面を参照して説明する。以下は本発明の一実施形態であって本発明を限定するものではない。
図1は、本実施形態の電力用半導体装置の断面である。本実施形態の電力用半導体装置に適用される電極導出端子インサート型のケースの平面図を図2に、斜視図を図3に示す。図4は、P電極導出端子の平面図である。図5は、N電極導出端子の平面図である。図6は、U電極導出端子の平面図である。図7は、P−N間に配置される絶縁樹脂シートの平面図である。図8は、N−U間に配置される絶縁樹脂シートの平面図である。図9は、P,N,Uの3電極導出端子及び絶縁樹脂シートの分解斜視図である。図10は、回路基板(ボンディングワイヤ無し)の平面図である。図11は、本実施形態の電力用半導体装置の等価回路図である。図12は、3相モータの駆動回路の回路図である。
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following is one embodiment of the present invention and does not limit the present invention.
FIG. 1 is a cross-sectional view of the power semiconductor device of this embodiment. FIG. 2 shows a plan view of an electrode lead-out terminal insert type case applied to the power semiconductor device of this embodiment, and FIG. 3 shows a perspective view thereof. FIG. 4 is a plan view of the P electrode lead-out terminal. FIG. 5 is a plan view of the N electrode lead-out terminal. FIG. 6 is a plan view of the U electrode lead-out terminal. FIG. 7 is a plan view of an insulating resin sheet disposed between PN. FIG. 8 is a plan view of an insulating resin sheet disposed between N-U. FIG. 9 is an exploded perspective view of the three-electrode lead terminals P, N, and U and the insulating resin sheet. FIG. 10 is a plan view of a circuit board (without bonding wires). FIG. 11 is an equivalent circuit diagram of the power semiconductor device of the present embodiment. FIG. 12 is a circuit diagram of a drive circuit for a three-phase motor.

本実施形態の電力用半導体装置は、以下に説明するように特許文献6記載の電力用半導体装置と共通の構成を有する。
図1に示すように本実施形態の電力用半導体装置は、放熱板1と、2つの回路基板2H、2L(図10に平面図を示す)と、ケース3とが組立てられて構成され、図11に示す回路を構成する。
The power semiconductor device of the present embodiment has a configuration common to the power semiconductor device described in Patent Document 6 as described below.
As shown in FIG. 1, the power semiconductor device of the present embodiment is configured by assembling a heat sink 1, two circuit boards 2H and 2L (shown in a plan view in FIG. 10), and a case 3. The circuit shown in FIG.

図2に示すようにケース3には、積層部11を構成するP,N,U各電極の電極導出端子4〜6及び制御用電極導出端子7H,7L,8H,8Lが保持されている。P,N,U各電極の電極導出端子4〜6及び制御用電極導出端子7、8は、銅板などの金属板をプレス成型して作製されるものであり、ニッケルめっき等が施される。ケース3は、樹脂成型品である。   As shown in FIG. 2, the case 3 holds the electrode lead-out terminals 4 to 6 and the control electrode lead-out terminals 7H, 7L, 8H, and 8L of the P, N, and U electrodes that constitute the laminated portion 11. The electrode lead-out terminals 4 to 6 and the control electrode lead-out terminals 7 and 8 of the P, N, and U electrodes are produced by press-molding a metal plate such as a copper plate, and are subjected to nickel plating or the like. Case 3 is a resin molded product.

図4及び図9に示すように、P電極導出端子4は、平行平板部4aと、垂直平板部4bと、外端接続部4cと、2つの内端接続部4d,4eとに分けて捉えることができる。
図5及び図9に示すように、N電極導出端子5は、平行平板部5aと、垂直平板部5bと、外端接続部5cと、2つの内端接続部5d,5eとに分けて捉えることができる。
図6及び図9に示すように、U電極導出端子6は、平行平板部6aと、垂直平板部6bと、外端接続部6cと、4つの内端接続部6d〜6gとに分けて捉えることができる。
各平行平板部4a,5a,6aは、回路基板2H、2Lに平行に配置される平板状部分である。
各垂直平板部4b,5b,6bは、回路基板2H、2Lに対し垂直に配置され、図9に示すように各平行平板部4a,5a,6aの端部と外端接続部4c,5c,6cの端部とを連結する平板状部分である。
P電極の外端接続部4cは、電源の高電位側からの外部配線が接続される。N電極の外端接続部5cは、電源の低電位側からの外部配線が接続される。U電極の外端接続部6cには、3相モータなどの出力先の装置が接続される。
As shown in FIGS. 4 and 9, the P electrode lead-out terminal 4 is divided into a parallel plate portion 4a, a vertical plate portion 4b, an outer end connection portion 4c, and two inner end connection portions 4d and 4e. be able to.
As shown in FIGS. 5 and 9, the N electrode lead-out terminal 5 is divided into a parallel plate portion 5a, a vertical plate portion 5b, an outer end connection portion 5c, and two inner end connection portions 5d and 5e. be able to.
As shown in FIGS. 6 and 9, the U electrode lead-out terminal 6 is divided into a parallel plate portion 6a, a vertical plate portion 6b, an outer end connection portion 6c, and four inner end connection portions 6d to 6g. be able to.
Each parallel flat plate part 4a, 5a, 6a is a flat plate-like part arrange | positioned in parallel with the circuit boards 2H and 2L.
The vertical flat plate portions 4b, 5b, 6b are arranged perpendicular to the circuit boards 2H, 2L. As shown in FIG. 9, the end portions of the parallel flat plate portions 4a, 5a, 6a and the outer end connection portions 4c, 5c, It is a flat part which connects the edge part of 6c.
An external wiring from the high potential side of the power source is connected to the outer end connection portion 4c of the P electrode. The external connection from the low potential side of the power source is connected to the outer end connection portion 5c of the N electrode. An output destination device such as a three-phase motor is connected to the outer end connection portion 6c of the U electrode.

3つの外端接続部4c,5c,6cは、ケース3の上端面上に同一高さで配置される。各平行平板部4a,5a,6aは、回路基板2H、2Lに近い方からP,N,Uの順に間隔を隔てて積層され、その間隔は、絶縁樹脂シート9,10によって保持される。したがって、外端接続部4c,5c,6cと平行平板部4a,5a,6aとの高低差は、P,N,Uの順で大きい。
図9に示すように絶縁樹脂シート9,10は、均一な厚さで形成されている。
The three outer end connection portions 4 c, 5 c, 6 c are arranged on the upper end surface of the case 3 at the same height. The parallel flat plate portions 4a, 5a, 6a are stacked at intervals in the order of P, N, U from the side closer to the circuit boards 2H, 2L, and the intervals are held by the insulating resin sheets 9, 10. Therefore, the height difference between the outer end connection portions 4c, 5c, and 6c and the parallel plate portions 4a, 5a, and 6a is large in the order of P, N, and U.
As shown in FIG. 9, the insulating resin sheets 9 and 10 are formed with a uniform thickness.

各平行平板部4a,5a,6aの先端は、同一位置に配置される。したがって、平行平板部の長さは、P,N,Uの順で長い。P,N,Uの3層は、N電極の平行平板部5aのほぼ全体において積層している。平行平板部5aの垂直平板部5bに近接する絶縁樹脂シート10の厚み相当の範囲は積層部11から除かれる。   The tips of the parallel plate portions 4a, 5a, 6a are arranged at the same position. Therefore, the length of the parallel plate portion is longer in the order of P, N, and U. The three layers P, N, and U are stacked on almost the entire parallel plate portion 5a of the N electrode. A range corresponding to the thickness of the insulating resin sheet 10 adjacent to the vertical flat plate portion 5 b of the parallel flat plate portion 5 a is excluded from the laminated portion 11.

各外端接続部4c,5c,6cには、ケース3の縁に沿った同位置に揃うように、ボルト挿入孔4k,5k,6kがプレス形成時に空けられている。これらのボルト挿入孔4k,5k,6kに連通するナットが1つずつ、計3つケース3に埋め込まれている。これらのボルト挿入孔4k,5k,6k及び3つのナットは、外部配線の端部に設けたリング状の端子を外端接続部4c,5c,6cにボルト締めにより圧着接続するための構造である。   Bolt insertion holes 4k, 5k, and 6k are formed in the outer end connection portions 4c, 5c, and 6c at the same time along the edge of the case 3 during press forming. Three nuts communicating with these bolt insertion holes 4k, 5k, 6k, one by one, are embedded in the case 3. These bolt insertion holes 4k, 5k, and 6k and the three nuts are structures for crimping and connecting ring-shaped terminals provided at the end portions of the external wiring to the outer end connection portions 4c, 5c, and 6c by bolting. .

各内端接続部4d,4e,5d,5e,6d〜6gは、積層部11の側縁、すなわち、各平行平板部4a,5a,6aの側縁から同一面内で突出形成された突起状部分で、途中で回路基板2H、2L側に折り曲げられ、さらにそれより先で内側に折り曲がられて形成されている。
積層部11の片側に配置された4つの内端接続部4d,4e,6d,6eについては、先端側からP電極の先端側内端接続部4d、U電極の先端側内端接続部6d、U電極の基端側内端接続部6e、P電極の基端側内端接続部4eの順で配置されている。
積層部11の他の片側に配置された4つの内端接続部5d,5e,6f,6gについては、先端側からU電極の先端側内端接続部6f、N電極の先端側内端接続部5d、N電極の基端側内端接続部5e、U電極の基端側内端接続部6gの順で配置されている。
最も先端側の内端接続部4d,6fの先端側端面は、平行平板部4a、6aの先端、すなわち、積層部11の先端に一致する。
片側4つの内端接続部4d,4e,6d,6eは均等な間隔に配置されず、内端接続部6dと内端接続部6eとの間が相対的に大きく開くことによって、先端側内端接続部4d, 6dと基端側内端接続部4e,6eとが先端側と基端側に偏在するように配置されている。
同様に、他の片側4つの内端接続部5d,5e,6f,6gは均等な間隔に配置されず、内端接続部5dと内端接続部5eとの間が相対的に大きく開くことによって、先端側内端接続部5d, 6fと基端側内端接続部5e,6gとが先端側と基端側に偏在するように配置されている。
Each of the inner end connection portions 4d, 4e, 5d, 5e, 6d to 6g has a protruding shape that protrudes in the same plane from the side edge of the laminated portion 11, that is, the side edge of each of the parallel plate portions 4a, 5a, 6a. The part is formed by being bent to the circuit board 2H, 2L side in the middle and further bent to the inner side after that.
For the four inner end connection portions 4d, 4e, 6d, and 6e arranged on one side of the stacked portion 11, from the front end side, the P electrode front end side inner end connection portion 4d, the U electrode front end side inner end connection portion 6d, The base end side inner end connection portion 6e of the U electrode and the base end side inner end connection portion 4e of the P electrode are arranged in this order.
Regarding the four inner end connection portions 5d, 5e, 6f, and 6g arranged on the other side of the laminated portion 11, from the front end side, the front end side inner end connection portion 6f of the U electrode and the front end side inner end connection portion of the N electrode 5d, the base end side inner end connection portion 5e of the N electrode, and the base end side inner end connection portion 6g of the U electrode are arranged in this order.
The front end side end surfaces of the inner end connection portions 4d and 6f on the most front end side coincide with the front ends of the parallel plate portions 4a and 6a, that is, the front end of the stacked portion 11.
The four inner end connecting parts 4d, 4e, 6d, 6e on one side are not arranged at equal intervals, and the inner end connecting part 6d and the inner end connecting part 6e are opened relatively widely, so that The connection portions 4d and 6d and the proximal end inner end connection portions 4e and 6e are arranged so as to be unevenly distributed on the distal end side and the proximal end side.
Similarly, the other four inner end connecting portions 5d, 5e, 6f, 6g on the other side are not arranged at equal intervals, and the inner end connecting portion 5d and the inner end connecting portion 5e are opened relatively large. The distal end inner end connecting portions 5d and 6f and the proximal end inner end connecting portions 5e and 6g are arranged so as to be unevenly distributed on the distal end side and the proximal end side.

図2、図4、図9等に示すように、P電極導出端子4の平行平板部4aの基端部は、積層部11の基端部より内端接続部4eの逆側に突出形成され、積層部11と同一幅の先端部より拡幅されている。この拡幅された平行平板部4aの基端部に同一幅で直角な折りを介して連続して垂直平板部4bが形成され、さらに垂直平板部4bの内端接続部4eと逆側の端部に直角な折りを介して外端接続部4cが連結されている。これら2回の折りが相互逆方向となることにより、P電極導出端子4は断面クランク状に形成されている。
内端接続部4eの逆側に平行平板部4aの基端部を拡幅したため、平行平板部4aの積層部11から突出する部分と内端接続部4eとが干渉せず、2つの内端接続部4d,4eの間隔を広く取りつつ、平行平板部4aの積層部11から突出する部分を大きく形成することができる。平行平板部4aの積層部11から突出する部分と垂直平板部4bとにより積層部11から外端接続部4cまでの電流経路の断面積が大きくとられている。
As shown in FIGS. 2, 4, 9, and the like, the base end portion of the parallel plate portion 4 a of the P electrode lead-out terminal 4 is formed so as to protrude from the base end portion of the laminated portion 11 to the opposite side of the inner end connection portion 4 e. The width is wider than the tip portion having the same width as the stacked portion 11. A vertical flat plate portion 4b is continuously formed at the base end portion of the widened parallel flat plate portion 4a through a right-angle fold with the same width, and an end portion on the opposite side to the inner end connection portion 4e of the vertical flat plate portion 4b. The outer end connection portion 4c is coupled through a fold that is perpendicular to each other. The P electrode lead-out terminals 4 are formed in a cross-sectional crank shape by these two foldings being opposite to each other.
Since the base end portion of the parallel plate portion 4a is widened on the opposite side of the inner end connection portion 4e, the portion protruding from the laminated portion 11 of the parallel plate portion 4a and the inner end connection portion 4e do not interfere with each other, and two inner end connections are made. The part which protrudes from the lamination | stacking part 11 of the parallel plate part 4a can be formed large, keeping the space | interval of the parts 4d and 4e wide. The cross-sectional area of the current path from the laminated portion 11 to the outer end connection portion 4c is increased by the portion of the parallel flat plate portion 4a that protrudes from the laminated portion 11 and the vertical flat plate portion 4b.

図2、図5、図9等に示すように、N電極導出端子5の平行平板部5aは全体として積層部11と同一幅で形成されている。平行平板部5aに同一幅で直角な折りを介して連続して垂直平板部5bが形成され、さらに垂直平板部5bの中央部に直角な折りを介して外端接続部5cが連結されている。これら2回の折りが相互逆方向となることにより、U電極導出端子5は断面クランク状に形成されている。   As shown in FIGS. 2, 5, 9, and the like, the parallel plate portion 5 a of the N electrode lead-out terminal 5 is formed with the same width as the stacked portion 11 as a whole. A vertical flat plate portion 5b is continuously formed on the parallel flat plate portion 5a through a right-angle fold with the same width, and an outer end connection portion 5c is connected to a central portion of the vertical flat plate portion 5b through a right-angle fold. . The U-electrode lead-out terminals 5 are formed in a cross-sectional crank shape by these two foldings being in opposite directions.

図2、図6、図9等に示すように、U電極導出端子6の平行平板部6aの基端部は、積層部11の基端部より内端接続部6gの逆側に突出形成され、積層部11と同一幅の先端部より拡幅されている。この拡幅された平行平板部6aの基端部に同一幅で直角な折りを介して連続して垂直平板部6bが形成され、さらに垂直平板部6bの内端接続部6gと逆側の端部に直角な折りを介して外端接続部6cが連結されている。これら2回の折りが相互逆方向となることにより、U電極導出端子6は断面クランク状に形成されている。
内端接続部6gの逆側に平行平板部6aを拡幅したため、平行平板部6aの積層部11から突出する部分と内端接続部6gとが干渉せず、2つの内端接続部6f, 6gの間隔を広く取りつつ、平行平板部6aの積層部11から突出する部分を大きく形成することができる。平行平板部6aの積層部11から突出する部分と垂直平板部6bとにより積層部11から外端接続部6cまでの電流経路の断面積が大きくとられている。
As shown in FIGS. 2, 6, 9, and the like, the base end portion of the parallel plate portion 6 a of the U electrode lead-out terminal 6 is formed to protrude from the base end portion of the stacked portion 11 to the opposite side of the inner end connection portion 6 g. The width is wider than the tip portion having the same width as the stacked portion 11. A vertical flat plate portion 6b is continuously formed at the base end portion of the widened parallel flat plate portion 6a through a right-angle fold with the same width, and an end portion on the opposite side to the inner end connection portion 6g of the vertical flat plate portion 6b. The outer end connection portion 6c is coupled through a fold that is perpendicular to each other. The U-electrode lead-out terminal 6 is formed in a cross-sectional crank shape by these two foldings being opposite to each other.
Since the parallel flat plate portion 6a is widened on the opposite side of the inner end connection portion 6g, the portion protruding from the laminated portion 11 of the parallel plate portion 6a and the inner end connection portion 6g do not interfere with each other, and the two inner end connection portions 6f, 6g. The part which protrudes from the lamination | stacking part 11 of the parallel plate part 6a can be formed large, taking the space | interval of this wide. The cross-sectional area of the current path from the laminated portion 11 to the outer end connecting portion 6c is increased by the portion of the parallel flat plate portion 6a that protrudes from the laminated portion 11 and the vertical flat plate portion 6b.

図10に示すように、2つの回路基板2H、2Lは、同一の回路パターンを有するものである。回路基板2HはP−U間に接続されるもので、P−U間に接続されるMOSFET素子12Hが16個実装される。回路基板2LはU−N間に接続されるもので、U−N間に接続されるMOSFET素子12Lが16個実装される。
回路基板2H、2Lは、それぞれ絶縁基板13と絶縁基板13上の導体パターン14,15,16とを有する。導体パターン14は、MOSFET素子12H(12L)のゲート電極、導体パターン15は、MOSFET素子12H(12L)のソース電極, 導体パターン16は、MOSFET素子12H(12L)のドレイン電極と接続する。ゲート用導体パターン14の周りに、ソース用導体パターン15が環状に形成され、さらにソース用導体パターン15の周りに、ドレイン用導体パターン16が環状に形成された回路パターンを有する。
導体パターン14上には各MOSFET素子12H(12L)に対応した16個のゲート抵抗素子17H(17L)が付設されている。
MOSFET素子12H(12L)は、そのドレイン電極を有する裏面を導体パターン16に接合している。MOSFET素子12H(12L)のゲート電極、ソース電極はチップ表面に形成されており、ボンディングワイヤを介して、導体パターン14,15にそれぞれ接続される。
As shown in FIG. 10, the two circuit boards 2H and 2L have the same circuit pattern. The circuit board 2H is connected between P-U, and 16 MOSFET elements 12H connected between P-U are mounted. The circuit board 2L is connected between U and N, and 16 MOSFET elements 12L connected between U and N are mounted.
The circuit boards 2H and 2L respectively have an insulating substrate 13 and conductor patterns 14, 15 and 16 on the insulating substrate 13. The conductor pattern 14 is connected to the gate electrode of the MOSFET element 12H (12L), the conductor pattern 15 is connected to the source electrode of the MOSFET element 12H (12L), and the conductor pattern 16 is connected to the drain electrode of the MOSFET element 12H (12L). A source conductor pattern 15 is formed in a ring shape around the gate conductor pattern 14, and a drain conductor pattern 16 is formed in a ring shape around the source conductor pattern 15.
On the conductor pattern 14, 16 gate resistance elements 17H (17L) corresponding to the respective MOSFET elements 12H (12L) are attached.
MOSFET element 12H (12L) has the back surface having the drain electrode bonded to conductor pattern 16. The gate electrode and source electrode of the MOSFET element 12H (12L) are formed on the chip surface, and are connected to the conductor patterns 14 and 15 via bonding wires, respectively.

内端接続部の接続領域を図10において囲み破線で示す。P電極導出端子4の内端接続部4d,4eは回路基板2H側のドレイン用導体パターン16に半田付けにより接合される。
U電極導出端子6の2つの内端接続部6d,6eは回路基板2H側のソース用導体パターン15に半田付けにより接合される。
制御用電極導出端子7Hは、回路基板2H側のゲート用導体パターン14に半田を介して接合される。制御用電極導出端子8Hは、回路基板2H側のソース用導体パターン15に半田付けにより接合される。
A connection region of the inner end connection portion is shown by a surrounding broken line in FIG. Inner end connection portions 4d and 4e of the P electrode lead-out terminal 4 are joined to the drain conductor pattern 16 on the circuit board 2H side by soldering.
The two inner end connection portions 6d and 6e of the U electrode lead-out terminal 6 are joined to the source conductor pattern 15 on the circuit board 2H side by soldering.
The control electrode lead-out terminal 7H is joined to the gate conductor pattern 14 on the circuit board 2H side via solder. The control electrode lead-out terminal 8H is joined to the source conductor pattern 15 on the circuit board 2H side by soldering.

U電極導出端子6の他の2つの内端接続部6f,6gは回路基板2L側のドレイン用導体パターン16に半田付けにより接合される。
N電極導出端子5の内端接続部5d,5eは回路基板2L側のソース用導体パターン15に半田付けにより接合される。
制御用電極導出端子7Lは、回路基板2L側のソース用導体パターン15に半田付けにより接合される。制御用電極導出端子8Lは、回路基板2L側のゲート用導体パターン14に半田付けにより接合される。
The other two inner end connection portions 6f and 6g of the U electrode lead-out terminal 6 are joined to the drain conductor pattern 16 on the circuit board 2L side by soldering.
The inner end connection portions 5d and 5e of the N electrode lead-out terminal 5 are joined to the source conductor pattern 15 on the circuit board 2L side by soldering.
The control electrode lead-out terminal 7L is joined to the source conductor pattern 15 on the circuit board 2L side by soldering. The control electrode lead-out terminal 8L is joined to the gate conductor pattern 14 on the circuit board 2L side by soldering.

制御用電極導出端子7H,8Hは回路基板2H上に架設され、制御用電極導出端子7L,8Lは、回路基板2H,2L上に架設されるとともに、積層部11と立体交差している。すなわち、本電力用半導体装置は、制御用電極導出端子7L,8Lが積層部11の上空で3つの電極導出端子4〜6に交差する構造を有する。   The control electrode lead-out terminals 7H and 8H are installed on the circuit board 2H, and the control electrode lead-out terminals 7L and 8L are provided on the circuit boards 2H and 2L and three-dimensionally intersect with the laminated portion 11. In other words, the power semiconductor device has a structure in which the control electrode lead terminals 7L and 8L intersect the three electrode lead terminals 4 to 6 above the stacked portion 11.

制御用電極導出端子7Hの内端接続部は、比較的広い間隔を隔てた内端接続部6dと6eの間を通して回路基板2Hに落とされる。制御用電極導出端子7L,8Lの内端接続部は、比較的広い間隔を隔てた内端接続部5dと5eの間を通して回路基板2Lに落とされる。
電極導出端子4〜6及び絶縁樹脂シート9,10の回路基板2L上空に位置する一側縁には、同一位置に凹部4h,5h,6h,9h,10hが形成されている。これにより、制御用電極導出端子7Lの内端接続部が電極導出端子4〜6及び絶縁樹脂シート9,10に接触しないように回避されている。
The inner end connection portion of the control electrode lead-out terminal 7H is dropped onto the circuit board 2H through the inner end connection portions 6d and 6e that are spaced apart by a relatively large distance. The inner end connection portions of the control electrode lead terminals 7L and 8L are dropped onto the circuit board 2L through the inner end connection portions 5d and 5e that are separated by a relatively wide distance.
Concave portions 4h, 5h, 6h, 9h, and 10h are formed at the same position on one side edge of the electrode lead terminals 4 to 6 and the insulating resin sheets 9 and 10 that are located above the circuit board 2L. Thus, the inner end connecting portion of the control electrode lead-out terminal 7 </ b> L is avoided so as not to contact the electrode lead-out terminals 4 to 6 and the insulating resin sheets 9 and 10.

次に、特許文献6記載の電力用半導体装置に対して本実施形態の電力用半導体装置の異なった部分を中心に説明する。
図4〜9に示すように、電極導出端子4〜6及び絶縁樹脂シート9,10には、孔a1〜a5が形成されている。これらの孔a1〜a5は、電極導出端子4〜6及び絶縁樹脂シート9,10のそれぞれを貫通する孔である。これら5つの孔a1〜a5が積層することにより、積層部11に積層孔aが形成される。積層部11には同様の積層孔bがもう一つ形成されている。積層孔bは孔b1〜b5からなる。孔a1〜a5及び孔b1〜b5は円形の孔である。積層孔aと積層孔bとは積層部11の長手方向に沿って異なる位置に形成されている。
Next, different parts of the power semiconductor device of the present embodiment from the power semiconductor device described in Patent Document 6 will be mainly described.
As shown in FIGS. 4 to 9, holes a <b> 1 to a <b> 5 are formed in the electrode lead terminals 4 to 6 and the insulating resin sheets 9 and 10. These holes a1 to a5 are holes that penetrate the electrode lead terminals 4 to 6 and the insulating resin sheets 9 and 10, respectively. By laminating these five holes a1 to a5, a laminated hole a is formed in the laminated portion 11. Another stacked hole b is formed in the stacked portion 11. The laminated hole b is composed of holes b1 to b5. The holes a1 to a5 and the holes b1 to b5 are circular holes. The stacked hole a and the stacked hole b are formed at different positions along the longitudinal direction of the stacked portion 11.

3枚の電極導出端子4〜6の各孔a1,a3,a5及び孔b1,b3,b5は、一定の積層方向(本実施形態において下から上への積層方向)に沿って次第に大きくなる大小関係を有して形成されている。これは、図13に示すような3段状の位置決めピン30を上から挿入し各孔a1,a3,a5(孔b1,b3,b5)に嵌合させて位置決めを行うためである。図13は、積層孔a,b共通の積層孔断面図である。   The holes a1, a3, a5 and the holes b1, b3, b5 of the three electrode lead-out terminals 4-6 gradually increase in size along a certain stacking direction (the stacking direction from bottom to top in this embodiment). It is formed with a relationship. This is because a three-stage positioning pin 30 as shown in FIG. 13 is inserted from above and fitted into the holes a1, a3, a5 (holes b1, b3, b5) for positioning. FIG. 13 is a cross-sectional view of the laminated holes common to the laminated holes a and b.

さらに積層部11には、他の2つの積層孔c、dが形成されている。2つの積層孔c、dのそれぞれは、電極導出端子4〜6及び絶縁樹脂シート9,10のそれぞれに貫通して設けられた矩形状の孔c1〜c5、孔d1〜d5から構成される。積層孔cと積層孔dとは積層部11の幅方向に沿って異なる位置であって、制御用電極導出端子7L,8Lの下方に配置される。   Furthermore, the other two laminated holes c and d are formed in the laminated part 11. Each of the two laminated holes c and d is composed of rectangular holes c1 to c5 and holes d1 to d5 provided through the electrode lead terminals 4 to 6 and the insulating resin sheets 9 and 10, respectively. The stacked hole c and the stacked hole d are located at different positions along the width direction of the stacked portion 11 and are disposed below the control electrode lead terminals 7L and 8L.

3枚の電極導出端子4〜6の各孔c1,c3,c5及び孔d1,d3,d5の大小関係は、図14、図15に示される。図14は、積層孔c、dを通る垂直断面を見せた端子及び樹脂部の斜視図である。図15は、積層孔c、dを通る垂直断面を描いた端子及び樹脂部の断面図である。図14及び図15に示すように、中間の孔c3及び孔d3が一番小さく形成されており、上下の孔c1,c5及び孔d1,d5は、それより大きくされている。   FIG. 14 and FIG. 15 show the magnitude relationship between the holes c1, c3, c5 and the holes d1, d3, d5 of the three electrode lead-out terminals 4-6. FIG. 14 is a perspective view of a terminal and a resin portion showing a vertical cross section passing through the laminated holes c and d. FIG. 15 is a cross-sectional view of a terminal and a resin portion depicting a vertical cross section passing through the laminated holes c and d. As shown in FIGS. 14 and 15, the middle hole c3 and the hole d3 are formed to be the smallest, and the upper and lower holes c1 and c5 and the holes d1 and d5 are made larger than that.

図16は、樹脂成型時のU電極導出端子6、制御用電極導出端子7L及び位置決めピン31、32の斜視図である。
樹脂成型時には、積層孔c、dに下から位置決めピン31、32が挿入される。位置決めピン31、32は上端方向に沿って細くなるテーパ状である。位置決めピン31、32の上端面が制御用電極導出端子7L,8Lを支持し、U電極導出端子6に対する高さを決める。
樹脂ケース(外囲部分)から延設されて連続して形成された端子保持用樹脂部19a、19bが制御用電極導出端子を支持する。端子保持用樹脂部19bは、樹脂ケース(外囲部分)の内壁から突出して制御用電極導出端子7H,8Hの基端部周りに付着接合しこれらを支持する。
端子保持用樹脂部19aは、積層部11の先端方向に位置する内壁から突出し、積層部11の先端部を上下に挟み込んで保持するとともに、積層部11の上に延設される部分が積層孔c、dの間の部分の上方に位置する制御用電極導出端子7L,8Lに付着接合してこれらを保持するとともに、積層孔c、d内に没入して積層孔c、dの内面に付着接合することにより、端子7L,8L支持の足場を固めるとともに、積層部11の層間位置を固定する。
FIG. 16 is a perspective view of the U electrode lead-out terminal 6, the control electrode lead-out terminal 7L, and the positioning pins 31 and 32 during resin molding.
At the time of resin molding, positioning pins 31 and 32 are inserted into the laminated holes c and d from below. The positioning pins 31 and 32 have a tapered shape that becomes narrower along the upper end direction. The upper end surfaces of the positioning pins 31 and 32 support the control electrode lead terminals 7L and 8L, and determine the height with respect to the U electrode lead terminal 6.
Terminal holding resin portions 19a and 19b extending from the resin case (outer portion) and continuously formed support the control electrode lead-out terminals. The terminal holding resin portion 19b protrudes from the inner wall of the resin case (outer portion), adheres and joins around the base end portions of the control electrode lead terminals 7H and 8H, and supports them.
The terminal holding resin portion 19a protrudes from the inner wall located in the front end direction of the laminated portion 11, sandwiches and holds the front end portion of the laminated portion 11 up and down, and a portion extending on the laminated portion 11 is a laminated hole. The control electrode lead-out terminals 7L and 8L located above the portion between c and d are adhered and joined to hold them, and they are immersed in the laminated holes c and d to adhere to the inner surfaces of the laminated holes c and d. By joining, the scaffold for supporting the terminals 7L and 8L is solidified, and the interlayer position of the laminated portion 11 is fixed.

以上説明した積層部11の外縁、内縁における絶縁樹脂シート9,10の縁の端面位置は、以下の規律に従って決められている。
すなわち外縁については、積層部において、絶縁樹脂シートに隣接する一方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置より内側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置と一致又は該位置の外側に配置される。
図17は、型閉め時の様子を示す断面模式図である。例えば図17(a)の左側及び図17(b)に示すように、積層部11において、絶縁樹脂シート9に隣接する一方の電極導出端子4の縁の端面位置が当該絶縁樹脂シート9の縁の端面位置より内側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子5の縁の端面位置が当該絶縁樹脂シート9の縁の端面位置の外側(一致してもよい)に配置されている。その他の部分も同じ規律に従って配置されている。
The end face positions of the edges of the insulating resin sheets 9 and 10 at the outer edge and inner edge of the laminated portion 11 described above are determined according to the following rules.
That is, for the outer edge, the end surface position of the edge of one electrode lead-out terminal adjacent to the insulating resin sheet is disposed inside the end surface position of the edge of the insulating resin sheet in the laminated portion, and the other edge adjacent to the insulating resin sheet is disposed. The end face position of the edge of the electrode lead-out terminal coincides with the end face position of the edge of the insulating resin sheet or is disposed outside the position.
FIG. 17 is a schematic cross-sectional view showing a state when the mold is closed. For example, as shown in the left side of FIG. 17A and FIG. 17B, the end surface position of the edge of one electrode lead-out terminal 4 adjacent to the insulating resin sheet 9 is the edge of the insulating resin sheet 9 in the laminated portion 11. The edge surface position of the other electrode lead-out terminal 5 adjacent to the insulating resin sheet is disposed outside (may be coincident with) the edge surface position of the edge of the insulating resin sheet 9. ing. Other parts are also arranged according to the same rules.

また、孔の内縁については外側と内側の関係が逆になるだけで同様の規律となる。すなわち、積層孔の内周において、絶縁樹脂シートに隣接する一方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置より外側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置と一致又は該位置の内側に配置される。
本規律は積層孔a,b,c,dに適用されている。例えば図13に示すように、積層孔a、bの内周において、絶縁樹脂シート10に隣接する一方の電極導出端子6の内縁の端面位置が当該絶縁樹脂シート10の内縁の端面位置より外側に配置され、当該絶縁樹脂シート10に隣接する他方の電極導出端子5の内縁の端面位置が当該絶縁樹脂シート10の内縁の端面位置と一致している(内側に配置してもよい)。その他の部分も同じ規律に従って配置されている。
In addition, the inner edge of the hole has the same discipline only when the relationship between the outer side and the inner side is reversed. That is, on the inner periphery of the laminated hole, the end surface position of the inner edge of one electrode lead-out terminal adjacent to the insulating resin sheet is arranged outside the end surface position of the inner edge of the insulating resin sheet, and the other end adjacent to the insulating resin sheet The end face position of the inner edge of the electrode lead-out terminal coincides with or is located inside the end face position of the inner edge of the insulating resin sheet.
This rule is applied to the laminated holes a, b, c and d. For example, as shown in FIG. 13, the end surface position of the inner edge of one electrode lead-out terminal 6 adjacent to the insulating resin sheet 10 is outside the end surface position of the inner edge of the insulating resin sheet 10 in the inner periphery of the laminated holes a and b. The end surface position of the inner edge of the other electrode lead-out terminal 5 that is disposed and is adjacent to the insulating resin sheet 10 coincides with the end surface position of the inner edge of the insulating resin sheet 10 (may be disposed inside). Other parts are also arranged according to the same rules.

以上のような規律に従って積層部11の各層の外縁、内縁が配置されることによって、一方の電極導出端子の縁から絶縁樹脂シート9,10の縁部に沿って他方の電極導出端子に至る沿面絶縁距離が、絶縁樹脂シート9,10の厚みより長く確保され、沿面絶縁距離を十分に確保することができる。また、絶縁樹脂シート9,10の縁部は突出せず、片側の電極導出端子に沿って延在するから、型閉め時に型51〜54が絶縁樹脂シート9,10の縁部に干渉しても、この縁部は片側の電極導出端子で支持され、この縁部の損傷、破損が抑えられ、もって製造歩留まりを向上することができる。   By arranging the outer edge and inner edge of each layer of the laminated portion 11 in accordance with the above rules, the creeping surface extends from the edge of one electrode lead-out terminal to the other electrode lead-out terminal along the edge of the insulating resin sheets 9 and 10. The insulation distance is secured longer than the thickness of the insulating resin sheets 9 and 10, and the creeping insulation distance can be sufficiently secured. Moreover, since the edge part of the insulating resin sheets 9 and 10 does not protrude and extends along the electrode lead-out terminal on one side, the molds 51 to 54 interfere with the edge part of the insulating resin sheets 9 and 10 when the mold is closed. However, this edge part is supported by the electrode lead-out terminal on one side, and damage and breakage of this edge part can be suppressed, thereby improving the manufacturing yield.

次に、本電力用半導体装置の製造方法につき、製造手順に沿って説明する。
(工程1)まず、3枚の電極導出端子4〜6を絶縁樹脂シート9,10を介して積層して3枚の電極導出端子4〜6と2枚の絶縁樹脂シート9,10とからなる5層構造体を構成する。電極導出端子4〜6及び絶縁樹脂シート9,10は、それぞれ製作しておく。絶縁樹脂シート9,10の材料としては例えばPPSが適用される。次工程で層間の位置補正を行うから、本工程においては電極導出端子4〜6及び絶縁樹脂シート9,10を単に重ねるだけで、層間の固定は行わない。したがって、接着剤や糊、加熱融着工程等は不要である。すなわち、層間を相対的に摺動可能な状態に保持する。
Next, a method for manufacturing the power semiconductor device will be described along a manufacturing procedure.
(Step 1) First, three electrode lead-out terminals 4 to 6 are laminated via insulating resin sheets 9 and 10, and are composed of three electrode lead-out terminals 4 to 6 and two insulating resin sheets 9 and 10. A five-layer structure is formed. The electrode lead-out terminals 4 to 6 and the insulating resin sheets 9 and 10 are respectively manufactured. As a material of the insulating resin sheets 9 and 10, for example, PPS is applied. Since the interlayer position is corrected in the next process, in this process, the electrode lead-out terminals 4 to 6 and the insulating resin sheets 9 and 10 are simply overlapped, and the interlayer is not fixed. Therefore, an adhesive, glue, a heat fusion process, etc. are unnecessary. That is, the layers are held in a relatively slidable state.

(工程2)上記工程1の実施とともに又は後に、5層構造体に構成される2つの積層孔a,bに位置決めピン30を挿入して層間の相対位置を位置決めする。このとき、図13に示すように、5層構造体に構成される2つの積層孔a,bに、各電極導出端子4,5,6の孔に嵌合する外径を有した3段状の位置決めピン30を、最も大きな孔を有する電極導出端子6側から挿入して層間の相対位置を位置決めする。
一方、図16に示すように、他の位置決めピン31,32を制御用電極導出端子7L,8Lの下方に配置される積層孔c、dに下から挿入して上端部を積層孔c、dから上方へ突出させて制御用電極導出端子7L,8Lに接触させることにより制御用電極導出端子7L,8Lを支持し、5層構造体に対する制御用電極導出端子7L,8Lの相対位置を位置決めする。
なお、本工程2を上記工程1の実施とともに実施する場合とは、電極導出端子4〜6及び絶縁樹脂シート9,10の孔a1〜a5,b1〜b5に順次位置決めピン30を挿入して、積層しながら位置決めピン30に係止する場合である。
既に構成した5層構造体に積層孔a,bに順次位置決めピン30を挿入する場合は、上記工程1の後に本工程2を実施する関係になる。
(Step 2) With or after the implementation of step 1, positioning pins 30 are inserted into the two laminated holes a and b formed in the five-layer structure to position the relative positions between the layers. At this time, as shown in FIG. 13, the two laminated holes a and b formed in the five-layer structure have a three-stage shape having an outer diameter that fits into the holes of the electrode lead-out terminals 4, 5, and 6. The positioning pin 30 is inserted from the electrode lead-out terminal 6 side having the largest hole to position the relative position between the layers.
On the other hand, as shown in FIG. 16, the other positioning pins 31 and 32 are inserted from below into the laminated holes c and d arranged below the control electrode lead-out terminals 7L and 8L, and the upper ends thereof are laminated holes c and d. The control electrode lead-out terminals 7L, 8L are supported by projecting upward from the control electrodes 7L, 8L, and the relative positions of the control electrode lead-out terminals 7L, 8L with respect to the five-layer structure are positioned. .
In addition, the case where this process 2 is implemented together with the implementation of the above-described process 1 means that the positioning pins 30 are sequentially inserted into the holes a1 to a5 and b1 to b5 of the electrode lead terminals 4 to 6 and the insulating resin sheets 9 and 10, This is a case where the positioning pin 30 is locked while being stacked.
In the case where the positioning pins 30 are sequentially inserted into the stacked holes a and b in the already configured five-layer structure, this step 2 is executed after the step 1 described above.

(工程3)上記工程1,2の実施とともに又は前後して、位置決めピン30,31,32を成形型に固定する。
位置決めピン30,31,32を成形型に固定するタイミングは、上記工程1,2の実施と同時でも、前後しても良い。
(Step 3) The positioning pins 30, 31, and 32 are fixed to the mold together with or before or after the implementation of the above steps 1 and 2.
The timing for fixing the positioning pins 30, 31, 32 to the mold may be the same as or before or after the above-described steps 1 and 2.

(工程4)位置決めピン30,31,32により位置決め固定された5層構造体及び制御用電極導出端子7L,8Lを成形型に収めて型閉めする。 (Step 4) The five-layer structure positioned and fixed by the positioning pins 30, 31, and 32 and the control electrode lead-out terminals 7L and 8L are placed in a mold and closed.

(工程5)型閉めされた成形型に樹脂を充填し3枚の電極導出端子4〜6及び制御用電極導出端子7H,8H,7L,8Lの一部に付着する樹脂ケース(外囲部分)と、樹脂ケース(外囲部分)から延設されて連続して形成され、積層部11の上空で制御用電極導出端子7L,8Lを保持するとともに、当該制御用電極導出端子7L,8L下方の位置決めピン30,30とこれが挿入される積層孔c,dとの隙間に入って当該積層孔c,dの内面に付着する樹脂部19aを成型する。また樹脂部19bも同時に成形する。 (Step 5) Resin case (enclosed portion) filled with resin in the mold that is closed and adhered to a part of the three electrode lead terminals 4 to 6 and the control electrode lead terminals 7H, 8H, 7L, 8L The control electrode lead-out terminals 7L and 8L are held in the sky above the laminated portion 11 and are formed below the control electrode lead-out terminals 7L and 8L. A resin portion 19a that enters the gap between the positioning pins 30 and 30 and the laminated holes c and d into which the positioning pins 30 and 30 are inserted and adheres to the inner surfaces of the laminated holes c and d is molded. The resin part 19b is also molded at the same time.

(工程6)以上のようにして作製した電極導出端子インサート型のケース3と、ダイボンディング及びワイヤボンディング済みの回路基板2H,2Lを図1に示すように放熱板1上に配置する。回路基板2H,2Lはケース3に包囲される。ケース3は、回路基板2H,2L周囲の放熱板1の周縁部に合わさる。放熱板1と回路基板2H,2Lとの固定は、半田その他熱伝導性の良い接合材により行うことが好ましい。放熱板1とケース3との固定は、それぞれ4角に設けられた孔20,21にボルトを挿入してボルト、ナットで締結することにより行う。
なお、回路基板2H,2Lは、放熱板1をベースとして放熱板1上に被着形成したセラミック基板等の絶縁層及びさらにその上に形成した導体パターン層によりなる形成当初より放熱板と一体のものでも良い。
(Step 6) The electrode lead-out terminal insert type case 3 manufactured as described above and the circuit boards 2H and 2L after die bonding and wire bonding are arranged on the heat sink 1 as shown in FIG. The circuit boards 2H and 2L are surrounded by the case 3. The case 3 is fitted to the peripheral edge of the heat sink 1 around the circuit boards 2H and 2L. It is preferable to fix the heat radiating plate 1 and the circuit boards 2H and 2L with a bonding material having good thermal conductivity such as solder. The heat radiating plate 1 and the case 3 are fixed by inserting bolts into holes 20 and 21 provided at four corners and fastening them with bolts and nuts.
The circuit boards 2H and 2L are integrated with the heat sink from the beginning of the formation of an insulating layer such as a ceramic substrate deposited on the heat sink 1 with the heat sink 1 as a base and a conductor pattern layer formed thereon. Things can be used.

(工程7)回路基板2H,2Lとケース3の配置を決め、各内端接続部と回路基板とを半田付けする。その後、図1に示されるように、ケース3の上端開口部に樹脂製の蓋22を被せる。
すべての電極導出端子4〜6,7H,8H,7L,8Lの外端接続部は枠状のケース3の上端面に配置される。そのため、蓋22は電極導出端子に干渉せず容易に着脱可能である。蓋22を外せば、内部の検査、修理がしやすい。蓋22上に又は蓋22に代えて他の装置、例えば制御用電極導出端子7H,8H,7L,8Lに接続する制御回路基板などを配置できる。
(Step 7) The arrangement of the circuit boards 2H and 2L and the case 3 is determined, and each inner end connection portion and the circuit board are soldered. Thereafter, as shown in FIG. 1, a resin lid 22 is placed on the upper end opening of the case 3.
The outer end connection portions of all the electrode lead terminals 4 to 6, 7 H, 8 H, 7 L, 8 L are arranged on the upper end surface of the frame-like case 3. Therefore, the lid 22 can be easily attached and detached without interfering with the electrode lead-out terminals. If the lid 22 is removed, the inside can be easily inspected and repaired. Other devices such as a control circuit board connected to the control electrode lead terminals 7H, 8H, 7L, and 8L can be arranged on the lid 22 or in place of the lid 22.

本実施形態の電力用半導体装置を図12に示すような3相モータの駆動回路に用いる。本実施形態の電力用半導体装置がu相、v相、w相の3相に対応して3つ並列に接続される。
各相に対応した電力用半導体装置の制御用電極導出端子7H,7L,8H,8Lに図示しない制御回路からの制御信号線が接続され、この制御回路の制御によりMOSFET素子12HとMOSFET素子12Lとが交互にスイッチングする。周知のようにu相、v相、w相の各相に対応した電力用半導体装置は相互に120°ずれた位相で制御され、図12の回路全体で位相が120°ずれた3相の交流電流を3相モータMへ出力し、3相モータMを駆動する。
The power semiconductor device of this embodiment is used in a drive circuit for a three-phase motor as shown in FIG. Three power semiconductor devices of this embodiment are connected in parallel corresponding to three phases of u phase, v phase, and w phase.
Control signal lines from a control circuit (not shown) are connected to control electrode lead terminals 7H, 7L, 8H, and 8L of the power semiconductor device corresponding to each phase, and the MOSFET circuit 12H and the MOSFET element 12L are controlled by the control circuit. Switch alternately. As is well known, power semiconductor devices corresponding to each of the u-phase, v-phase, and w-phase are controlled with phases shifted from each other by 120 °, and a three-phase alternating current whose phase is shifted by 120 ° in the entire circuit of FIG. Current is output to the three-phase motor M, and the three-phase motor M is driven.

本発明は以上の実施形態に限定されるものではなく、半導体スイッチ素子はMOSFETに代えIGBT(絶縁ゲート型バイポーラトランジスタ)としてもよい。IGBTとする場合は、IGBTと並列に外付けのダイオード素子が必要となる。   The present invention is not limited to the above embodiment, and the semiconductor switch element may be an IGBT (Insulated Gate Bipolar Transistor) instead of the MOSFET. In the case of an IGBT, an external diode element is required in parallel with the IGBT.

本発明実施形態に係る電力用半導体装置の断面である。1 is a cross-sectional view of a power semiconductor device according to an embodiment of the present invention. 本発明実施形態に係る電力用半導体装置に適用される電極導出端子インサート型のケースの平面図である。It is a top view of the electrode lead-out terminal insert type case applied to the power semiconductor device according to the embodiment of the present invention. 本発明実施形態に係る電力用半導体装置に適用される電極導出端子インサート型のケースの斜視図であるIt is a perspective view of the electrode lead-out terminal insert type case applied to the power semiconductor device according to the embodiment of the present invention. 本発明実施形態に係るP電極導出端子の平面図である。It is a top view of the P electrode derivation terminal concerning the embodiment of the present invention. 本発明実施形態に係るN電極導出端子の平面図であるIt is a top view of the N electrode derivation terminal concerning the embodiment of the present invention. 本発明実施形態に係るU電極導出端子の平面図である。It is a top view of the U electrode derivation terminal concerning the embodiment of the present invention. 本発明実施形態に係るP−N間に配置される絶縁樹脂シートの平面図である。It is a top view of the insulating resin sheet arrange | positioned between PN which concerns on this invention embodiment. 本発明実施形態に係るN−U間に配置される絶縁樹脂シートの平面図である。It is a top view of the insulating resin sheet arrange | positioned between NU which concerns on this invention embodiment. 本発明実施形態に係るP,N,Uの3電極導出端子及び絶縁樹脂シートの分解斜視図である。It is a disassembled perspective view of 3 electrode lead-out terminals of P, N, and U and an insulating resin sheet according to an embodiment of the present invention. 本発明実施形態に係る回路基板(ボンディングワイヤ無し)の平面図である。1 is a plan view of a circuit board (without bonding wires) according to an embodiment of the present invention. 本発明実施形態に係る電力用半導体装置の等価回路図である。1 is an equivalent circuit diagram of a power semiconductor device according to an embodiment of the present invention. 3相モータの駆動回路の回路図である。It is a circuit diagram of the drive circuit of a three-phase motor. 本発明実施形態に係る積層孔断面図である。1 is a cross-sectional view of a laminated hole according to an embodiment of the present invention. 本発明実施形態に係る積層孔を通る垂直断面を見せた端子及び樹脂部の斜視図である。It is the perspective view of the terminal and resin part which showed the vertical cross section which passes along the laminated hole which concerns on this invention embodiment. 本発明実施形態に係る積層孔を通る垂直断面を描いた端子及び樹脂部の断面図である。It is sectional drawing of the terminal and resin part which drew the vertical cross section which passes along the laminated hole which concerns on this invention embodiment. 本発明実施形態に係る樹脂成型時のU電極導出端子、制御用電極導出端子及び位置決めピンの斜視図である。It is a perspective view of a U electrode lead-out terminal, a control electrode lead-out terminal, and a positioning pin at the time of resin molding according to an embodiment of the present invention. 本発明実施形態に係る型閉め時の様子を示す断面模式図である。It is a cross-sectional schematic diagram which shows the mode at the time of the mold closing which concerns on this invention embodiment. 対比技術に係る型閉め時の様子を示す断面模式図である。It is a cross-sectional schematic diagram which shows the mode at the time of the mold closing which concerns on contrast technology.

符号の説明Explanation of symbols

1 放熱板
2H,2L 回路基板
3 ケース
4 P電極導出端子
5 N電極導出端子
6 U電極導出端子
4a,5a,6a 平行平板部
4b,5b,6b 垂直平板部
4c,5c,6c 外端接続部
4d,4e,5d,5e, 6d〜6g 内端接続部
7H,7L,8H,8L 制御用電極導出端子
9,10 絶縁樹脂シート
11 積層部
12H,12L MOSFET素子
13 絶縁基板
14 ゲート用導体パターン
15 ソース用導体パターン
16 ドレイン用導体パターン
17H,17L ゲート抵抗素子
19a 端子保持用樹脂部
19b 端子保持用樹脂部
20,21 孔
22 蓋
a,b,c,d 積層孔
30 位置決めピン
31,32 位置決めピン
DESCRIPTION OF SYMBOLS 1 Heat sink 2H, 2L Circuit board 3 Case 4 P electrode derivation terminal 5 N electrode derivation terminal 6 U electrode derivation terminal 4a, 5a, 6a Parallel flat plate part 4b, 5b, 6b Vertical flat plate part 4c, 5c, 6c Outer end connection part 4d, 4e, 5d, 5e, 6d to 6g Inner end connection portion 7H, 7L, 8H, 8L Control electrode lead-out terminal 9, 10 Insulating resin sheet 11 Laminated portion 12H, 12L MOSFET element 13 Insulating substrate 14 Gate conductor pattern 15 Conductor pattern for source 16 Conductor pattern for drain 17H, 17L Gate resistor 19a Terminal holding resin part 19b Terminal holding resin part 20, 21 hole 22 Lid a, b, c, d Laminated hole 30 Positioning pin 31, 32 Positioning pin

Claims (5)

両端に電源からの電力線が接続される直列接続の両半導体スイッチング素子の互いの接続点から負荷への出力線を引き出した回路を有し、前記両半導体スイッチング素子が相補的に開閉制御されることにより、前記電源の電力を変換して前記負荷へ出力する電力用半導体装置であって、
前記電力線の高電位側をP、低電位側をN、前記出力線をUとして、P,N,Uの3電極に対応する3枚の電極導出端子と、2枚の絶縁樹脂シートとを有し、
前記3枚の電極導出端子が、前記半導体スイッチング素子が実装される回路基板の上空で、前記絶縁樹脂シートを介して積層され、少なくともその積層部で前記回路基板と平行な平板状に形成されてなり、
前記積層部において、前記絶縁樹脂シートに隣接する一方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置より内側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置と一致又は該位置の外側に配置され
前記積層部に前記3枚の電極導出端子及び前記2枚の絶縁樹脂シートのそれぞれを貫通する孔が積層されてなる積層孔が形成され、
前記積層孔の内周において、前記絶縁樹脂シートに隣接する一方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置より外側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置と一致又は該位置の内側に配置され、
一の前記積層孔を構成する前記3枚の電極導出端子の各孔が一定の積層方向に沿って次第に大きくなる大小関係を有して形成されてなることを特徴とする電力用半導体装置。
It has a circuit in which output lines to the load are drawn from the mutual connection points of both series-connected semiconductor switching elements connected to power lines from the power supply at both ends, and both the semiconductor switching elements are complementarily controlled to open and close The power semiconductor device that converts the power of the power source and outputs the power to the load,
With the high potential side of the power line as P, the low potential side as N, and the output line as U, there are three electrode lead-out terminals corresponding to the three electrodes P, N, and U, and two insulating resin sheets. And
The three electrode lead-out terminals are stacked above the circuit board on which the semiconductor switching element is mounted via the insulating resin sheet, and are formed in a flat plate shape parallel to the circuit board at least in the stacked portion. Become
In the laminated portion, the other electrode lead-out terminal adjacent to the insulating resin sheet is arranged such that the end face position of the edge of one electrode lead-out terminal adjacent to the insulating resin sheet is located inside the end face position of the edge of the insulating resin sheet. The end face position of the edge of the insulating resin sheet is aligned with the end face position of the edge of the insulating resin sheet or arranged outside the position ,
A laminated hole is formed by laminating holes through each of the three electrode lead-out terminals and the two insulating resin sheets in the laminated portion,
In the inner periphery of the laminated hole, the end surface position of the inner edge of one electrode lead-out terminal adjacent to the insulating resin sheet is disposed outside the end surface position of the inner edge of the insulating resin sheet, and the other end adjacent to the insulating resin sheet. The end face position of the inner edge of the electrode lead-out terminal coincides with the end face position of the inner edge of the insulating resin sheet or is arranged inside the position,
A power semiconductor device, wherein each hole of the three electrode lead-out terminals constituting one of the stacked holes is formed to have a size relationship that gradually increases along a certain stacking direction .
両端に電源からの電力線が接続される直列接続の両半導体スイッチング素子の互いの接続点から負荷への出力線を引き出した回路を有し、前記両半導体スイッチング素子が相補的に開閉制御されることにより、前記電源の電力を変換して前記負荷へ出力する電力用半導体装置であって、
前記電力線の高電位側をP、低電位側をN、前記出力線をUとして、P,N,Uの3電極に対応する3枚の電極導出端子と、2枚の絶縁樹脂シートとを有し、
前記3枚の電極導出端子が、前記半導体スイッチング素子が実装される回路基板の上空で、前記絶縁樹脂シートを介して積層され、少なくともその積層部で前記回路基板と平行な平板状に形成されてなり、
前記積層部において、前記絶縁樹脂シートに隣接する一方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置より内側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置と一致又は該位置の外側に配置され、
前記積層部に前記3枚の電極導出端子及び前記2枚の絶縁樹脂シートのそれぞれを貫通する孔が積層されてなる積層孔が形成され、
前記積層孔の内周において、前記絶縁樹脂シートに隣接する一方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置より外側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置と一致又は該位置の内側に配置され、
前記回路基板を包囲する枠状で前記3つの電極導出端子の一部を埋没させてこれらを保持する樹脂ケースを有し、
前記半導体スイッチング素子のスイッチングを制御するための制御用電極導出端子が前記積層部の上空で前記3つの電極導出端子に交差する構造を有し、
前記樹脂ケースから延設されて連続して形成された樹脂部が、前記積層部の上空で前記制御用電極導出端子を保持するとともに一の前記積層孔に入ってその内面に付着形成されてなる電力用半導体装置。
It has a circuit in which output lines to the load are drawn from the mutual connection points of both series-connected semiconductor switching elements connected to power lines from the power supply at both ends, and both the semiconductor switching elements are complementarily controlled to open and close The power semiconductor device that converts the power of the power source and outputs the power to the load,
With the high potential side of the power line as P, the low potential side as N, and the output line as U, there are three electrode lead-out terminals corresponding to the three electrodes P, N, and U, and two insulating resin sheets. And
The three electrode lead-out terminals are stacked above the circuit board on which the semiconductor switching element is mounted via the insulating resin sheet, and are formed in a flat plate shape parallel to the circuit board at least in the stacked portion. Become
In the laminated portion, the other electrode lead-out terminal adjacent to the insulating resin sheet is arranged such that the end face position of the edge of one electrode lead-out terminal adjacent to the insulating resin sheet is located inside the end face position of the edge of the insulating resin sheet. The end face position of the edge of the insulating resin sheet is aligned with the end face position of the edge of the insulating resin sheet or arranged outside the position,
A laminated hole is formed by laminating holes through each of the three electrode lead-out terminals and the two insulating resin sheets in the laminated portion,
In the inner periphery of the laminated hole, the end surface position of the inner edge of one electrode lead-out terminal adjacent to the insulating resin sheet is disposed outside the end surface position of the inner edge of the insulating resin sheet, and the other end adjacent to the insulating resin sheet. The end face position of the inner edge of the electrode lead-out terminal coincides with the end face position of the inner edge of the insulating resin sheet or is arranged inside the position,
A resin case that holds and retains a part of the three electrode lead-out terminals in a frame shape surrounding the circuit board;
The control electrode lead-out terminal for controlling the switching of the semiconductor switching element has a structure that intersects the three electrode lead-out terminals above the stacked portion,
The resin part continuously extended from the resin case is formed so as to hold the control electrode lead-out terminal above the laminated part and to be attached to the inner surface of the one laminated hole. semiconductor device for that power.
両端に電源からの電力線が接続される直列接続の両半導体スイッチング素子の互いの接続点から負荷への出力線を引き出した回路を有し、前記両半導体スイッチング素子が相補的に開閉制御されることにより、前記電源の電力を変換して前記負荷へ出力する電力用半導体装置であって、
前記電力線の高電位側をP、低電位側をN、前記出力線をUとして、P,N,Uの3電極に対応する3枚の電極導出端子と、2枚の絶縁樹脂シートとを有し、
前記3枚の電極導出端子が、前記半導体スイッチング素子が実装される回路基板の上空で、前記絶縁樹脂シートを介して積層され、少なくともその積層部で前記回路基板と平行な平板状に形成されてなり、
前記積層部において、前記絶縁樹脂シートに隣接する一方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置より内側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の縁の端面位置が当該絶縁樹脂シートの縁の端面位置と一致又は該位置の外側に配置され、
前記積層部に前記3枚の電極導出端子及び前記2枚の絶縁樹脂シートのそれぞれを貫通する孔が積層されてなる積層孔が形成され、
前記積層孔の内周において、前記絶縁樹脂シートに隣接する一方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置より外側に配置され、当該絶縁樹脂シートに隣接する他方の電極導出端子の内縁の端面位置が当該絶縁樹脂シートの内縁の端面位置と一致又は該位置の内側に配置されてなる電力用半導体装置の製造方法であって、
前記3枚の電極導出端子を前記絶縁樹脂シートを介して積層して3枚の電極導出端子と2枚の絶縁樹脂シートとからなる5層構造体を構成する工程と、
前記5層構造体に構成される2以上の前記積層孔に位置決めピンを挿入して層間の相対位置を位置決めする工程と、
前記位置決めピンを成形型に固定する工程と、
前記位置決めピンにより位置決め固定された前記5層構造体を前記成形型に収めて型閉めする工程と、
型閉めされた前記成形型に樹脂を充填し前記3枚の電極導出端子の一部に付着する樹脂ケースを成型する工程とを備える電力用半導体装置の製造方法。
It has a circuit in which output lines to the load are drawn from the mutual connection points of both series-connected semiconductor switching elements connected to power lines from the power supply at both ends, and both the semiconductor switching elements are complementarily controlled to open and close The power semiconductor device that converts the power of the power source and outputs the power to the load,
With the high potential side of the power line as P, the low potential side as N, and the output line as U, there are three electrode lead-out terminals corresponding to the three electrodes P, N, and U, and two insulating resin sheets. And
The three electrode lead-out terminals are stacked above the circuit board on which the semiconductor switching element is mounted via the insulating resin sheet, and are formed in a flat plate shape parallel to the circuit board at least in the stacked portion. Become
In the laminated portion, the other electrode lead-out terminal adjacent to the insulating resin sheet is arranged such that the end face position of the edge of one electrode lead-out terminal adjacent to the insulating resin sheet is located inside the end face position of the edge of the insulating resin sheet. The end face position of the edge of the insulating resin sheet is aligned with the end face position of the edge of the insulating resin sheet or arranged outside the position,
A laminated hole is formed by laminating holes through each of the three electrode lead-out terminals and the two insulating resin sheets in the laminated portion,
In the inner periphery of the laminated hole, the end surface position of the inner edge of one electrode lead-out terminal adjacent to the insulating resin sheet is disposed outside the end surface position of the inner edge of the insulating resin sheet, and the other end adjacent to the insulating resin sheet. An end surface position of the inner edge of the electrode lead-out terminal is the same as the end surface position of the inner edge of the insulating resin sheet, or a manufacturing method of a power semiconductor device arranged inside the position ,
Laminating the three electrode lead-out terminals via the insulating resin sheet to form a five-layer structure comprising three electrode lead-out terminals and two insulating resin sheets;
Inserting a positioning pin into two or more of the laminated holes configured in the five-layer structure to position a relative position between layers;
Fixing the positioning pin to a mold; and
Storing the five-layer structure positioned and fixed by the positioning pin in the mold and closing the mold;
A method of manufacturing a power semiconductor device, comprising: filling a mold in a closed mold and molding a resin case attached to a part of the three electrode lead-out terminals.
請求項に記載の電力用半導体装置の製造方法であって、
前記3枚の電極導出端子を前記絶縁樹脂シートを介して積層して3枚の電極導出端子と2枚の絶縁樹脂シートとからなる5層構造体を構成する工程と、
前記5層構造体に構成される2以上の前記積層孔に、各電極導出端子の孔に嵌合する外径を有した3段状の位置決めピンを、最も大きな孔を有する前記電極導出端子側から挿入して層間の相対位置を位置決めする工程と、
前記位置決めピンを成形型に固定する工程と、
前記位置決めピンにより位置決め固定された前記5層構造体を前記成形型に収めて型閉めする工程と、
型閉めされた前記成形型に樹脂を充填し前記3枚の電極導出端子の一部に付着する樹脂ケースを成型する工程とを備える電力用半導体装置の製造方法。
A method of manufacturing a power semiconductor device according to claim 1 ,
Laminating the three electrode lead-out terminals via the insulating resin sheet to form a five-layer structure comprising three electrode lead-out terminals and two insulating resin sheets;
In the two or more laminated holes configured in the five-layer structure, a three-stage positioning pin having an outer diameter that fits into the hole of each electrode lead-out terminal, the electrode lead-out terminal side having the largest hole Inserting the relative position between the layers,
Fixing the positioning pin to a mold; and
Storing the five-layer structure positioned and fixed by the positioning pin in the mold and closing the mold;
A method of manufacturing a power semiconductor device, comprising: filling a mold in a closed mold and molding a resin case attached to a part of the three electrode lead-out terminals.
請求項に記載の電力用半導体装置の製造方法であって、
前記3枚の電極導出端子を前記絶縁樹脂シートを介して積層して3枚の電極導出端子と2枚の絶縁樹脂シートとからなる5層構造体を構成する工程と、
前記5層構造体に構成される2以上の前記積層孔に位置決めピンを挿入して層間の相対位置を位置決めするとともに、他の位置決めピンを前記制御用電極導出端子の下方に配置される前記積層孔に下から挿入して上端部を当該積層孔から上方へ突出させて前記制御用電極導出端子に接触させることにより当該制御用電極導出端子を支持し、前記5層構造体に対する前記制御用電極導出端子の相対位置を位置決めする工程と、
前記位置決めピンを成形型に固定する工程と、
前記位置決めピンにより位置決め固定された前記5層構造体及び前記制御用電極導出端子を前記成形型に収めて型閉めする工程と、
型閉めされた前記成形型に樹脂を充填し前記3枚の電極導出端子及び前記制御用電極導出端子の一部に付着する樹脂ケースと、前記樹脂ケースから延設されて連続して形成され、前記積層部の上空で前記制御用電極導出端子を保持するとともに、当該制御用電極導出端子下方の前記他の位置決めピンとこれが挿入される積層孔との隙間に入って当該積層孔の内面に付着する樹脂部を成型する工程とを備える電力用半導体装置の製造方法。
A method of manufacturing a power semiconductor device according to claim 2 ,
Laminating the three electrode lead-out terminals via the insulating resin sheet to form a five-layer structure comprising three electrode lead-out terminals and two insulating resin sheets;
The laminated layer in which positioning pins are inserted into two or more laminated holes configured in the five-layer structure to position relative positions between the layers, and another positioning pin is disposed below the control electrode lead-out terminal The control electrode lead-out terminal is supported by inserting the hole into the hole from below and projecting the upper end portion upward from the laminated hole to contact the control electrode lead-out terminal, and the control electrode for the five-layer structure Positioning the relative position of the lead terminal;
Fixing the positioning pin to a mold; and
Storing the five-layer structure positioned and fixed by the positioning pin and the control electrode lead-out terminal in the mold, and closing the mold;
A resin case that is filled with resin in the mold that is closed and adheres to a part of the three electrode lead-out terminals and the control electrode lead-out terminal, and is continuously formed extending from the resin case, The control electrode lead-out terminal is held above the stack portion, and enters the gap between the other positioning pin below the control electrode lead-out terminal and the stack hole into which it is inserted, and adheres to the inner surface of the stack hole. The manufacturing method of the semiconductor device for electric power provided with the process of shape | molding the resin part.
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