JP5811072B2 - Power module - Google Patents

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JP5811072B2
JP5811072B2 JP2012243069A JP2012243069A JP5811072B2 JP 5811072 B2 JP5811072 B2 JP 5811072B2 JP 2012243069 A JP2012243069 A JP 2012243069A JP 2012243069 A JP2012243069 A JP 2012243069A JP 5811072 B2 JP5811072 B2 JP 5811072B2
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phase
terminal
insulating substrate
output terminal
switching element
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智明 満永
智明 満永
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Toyota Motor Corp
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    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
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    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
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    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Description

本発明は、パワーモジュールに関し、特に一対のスイッチング素子を備えたパワーモジュールに関する。   The present invention relates to a power module, and particularly to a power module including a pair of switching elements.

一対のスイッチング素子を備えた電力制御用のパワーモジュールにおいては、大電流が断続的に流れるため、スイッチング時のサージ電圧を抑制する観点から、回路のインダクタンスの低減が要求されている。例えば、特許文献1には、一方のスイッチング素子のP端子板(Pバスバ)と、他方のスイッチング素子のN端子板(Nバスバ)とが、それらを流れる電流の方向が反対となるように絶縁基板を挟んで配置されたパワーモジュールが開示されている。また、特許文献2には、P端子板とN端子板とが、双方のスイッチング素子の出力端子板を挟んで上下に配置されたパワーモジュールが開示されている。   In a power control power module including a pair of switching elements, since a large current flows intermittently, a reduction in circuit inductance is required from the viewpoint of suppressing a surge voltage during switching. For example, in Patent Document 1, the P terminal plate (P bus bar) of one switching element and the N terminal plate (N bus bar) of the other switching element are insulated so that the directions of currents flowing through them are opposite. A power module arranged with a substrate interposed therebetween is disclosed. Patent Document 2 discloses a power module in which a P terminal plate and an N terminal plate are arranged up and down across the output terminal plates of both switching elements.

特開2009−295633号公報JP 2009-295633 A 特開2001−332688号公報JP 2001-332688 A

しかしながら、上記特許文献1に記載されているようなパワーモジュールでは、P端子板及びN端子板だけが電流の方向が反対となるように配置されているため、インダクタンスを低減する効果が不十分である。   However, in the power module as described in Patent Document 1, since only the P terminal plate and the N terminal plate are arranged so that the directions of the currents are opposite, the effect of reducing the inductance is insufficient. is there.

また、上記特許文献2に記載されているようなパワーモジュールでは、図21に示すように、第1トランジスタTr1のP端子板P、第2トランジスタTr2のN端子板N、及び第1トランジスタTr1と第2トランジスタTr2とに共通の出力端子板Uを備えている。特許文献2のようなパワーモジュールでは、図22に示すように、出力端子板Uを挟んで上下に配置されたP端子板PとN端子板Nとが離れているため、P端子板PとN端子板Nとの間でインダクタンスを低減する効果が乏しい。特許文献2のようなパワーモジュールでは、領域z1及び領域z2においてのみインダクタンスを低減する効果が得られるため、インダクタンスを低減する効果が不十分である。   Further, in the power module described in Patent Document 2, as shown in FIG. 21, the P terminal plate P of the first transistor Tr1, the N terminal plate N of the second transistor Tr2, and the first transistor Tr1 An output terminal plate U common to the second transistor Tr2 is provided. In a power module such as Patent Document 2, as shown in FIG. 22, the P terminal plate P and the N terminal plate N that are arranged above and below the output terminal plate U are separated from each other. The effect of reducing the inductance with the N terminal plate N is poor. In the power module as in Patent Document 2, the effect of reducing the inductance is obtained only in the region z1 and the region z2, and thus the effect of reducing the inductance is insufficient.

本発明は上記課題に鑑みてなされたものであり、インダクタンスを低減する効果を向上させることができるパワーモジュールを提供することを目的とする。   This invention is made | formed in view of the said subject, and it aims at providing the power module which can improve the effect of reducing an inductance.

本発明は、高電位側のP端子とP端子よりも低電位側の第1出力端子とを有する第1スイッチング素子と、低電位側のN端子とN端子よりも高電位側の第2出力端子とを有する第2スイッチング素子とを備え、P端子を流れる電流の方向とN端子を流れる電流の方向が互いに正反対の平行な方向となるように、P端子とN端子とが並列に配置され、P端子を流れる電流の方向と第1出力端子を流れる電流の方向が互いに正反対の平行な方向となるように、第1出力端子が、N端子と第1出力端子との間にP端子を挟むように配置され、N端子を流れる電流の方向と第2出力端子を流れる電流の方向が互いに正反対の平行な方向となるように、第2出力端子が、P端子と第2出力端子との間にN端子を挟むように配置されているパワーモジュールである。   The present invention includes a first switching element having a P terminal on the high potential side and a first output terminal on the lower potential side than the P terminal, and a second output on the higher potential side than the N terminal on the low potential side and the N terminal. And the P terminal and the N terminal are arranged in parallel so that the direction of the current flowing through the P terminal and the direction of the current flowing through the N terminal are opposite to each other in parallel. The first output terminal is connected between the N terminal and the first output terminal so that the direction of the current flowing through the P terminal and the direction of the current flowing through the first output terminal are parallel to each other. The second output terminal is disposed between the P terminal and the second output terminal so that the direction of the current flowing through the N terminal and the direction of the current flowing through the second output terminal are parallel to each other. Power module arranged with N terminal in between It is.

この構成によれば、高電位側のP端子と低電位側の第1出力端子とを有する第1スイッチング素子と、低電位側のN端子と高電位側の第2出力端子とを有する第2スイッチング素子とを備えたパワーモジュールにおいて、P端子を流れる電流の方向とN端子を流れる電流の方向が互いに正反対の平行な方向となるように、P端子とN端子とが並列に配置され、P端子を流れる電流の方向と第1出力端子を流れる電流の方向が互いに正反対の平行な方向となるように、第1出力端子が、N端子と第1出力端子との間にP端子を挟むように配置され、N端子を流れる電流の方向と第2出力端子を流れる電流の方向が互いに正反対の平行な方向となるように、第2出力端子がP端子と第2出力端子との間にN端子を挟むように配置されている。このため、P端子とN端子とを流れる電流、P端子と第1出力端子とを流れる電流、及びN端子と第2出力端子とを流れる電流により互いに三箇所で磁界が相殺され、インダクタンスを低減する効果を向上させることができる。   According to this configuration, the first switching element having the P terminal on the high potential side and the first output terminal on the low potential side, the second terminal having the N terminal on the low potential side and the second output terminal on the high potential side. In a power module including a switching element, the P terminal and the N terminal are arranged in parallel so that the direction of the current flowing through the P terminal and the direction of the current flowing through the N terminal are parallel to each other. The first output terminal sandwiches the P terminal between the N terminal and the first output terminal so that the direction of the current flowing through the terminal and the direction of the current flowing through the first output terminal are parallel to each other. The second output terminal is arranged between the P terminal and the second output terminal so that the direction of the current flowing through the N terminal and the direction of the current flowing through the second output terminal are parallel to each other. The terminals are arranged so as to sandwich the terminals. For this reason, the magnetic field is canceled at three points by the current flowing through the P terminal and the N terminal, the current flowing through the P terminal and the first output terminal, and the current flowing through the N terminal and the second output terminal, thereby reducing inductance. The effect to do can be improved.

この場合、第1面及び第2面を有する絶縁基板をさらに備え、P端子及びN端子はそれぞれ厚さよりも幅が大きい板状をなし、P端子は絶縁基板の第1面に配置され、N端子は絶縁基板の第2面に配置され、P端子及びN端子は絶縁基板を間に挟むように積層配置されていることが好適である。   In this case, the semiconductor device further includes an insulating substrate having a first surface and a second surface, each of the P terminal and the N terminal having a plate shape having a width larger than the thickness, and the P terminal is disposed on the first surface of the insulating substrate. It is preferable that the terminals are disposed on the second surface of the insulating substrate, and the P terminal and the N terminal are stacked so as to sandwich the insulating substrate therebetween.

この構成によれば、第1面及び第2面を有する絶縁基板をさらに備え、P端子及びN端子はそれぞれ厚さよりも幅が大きい板状をなし、P端子は絶縁基板の第1面に配置され、N端子は絶縁基板の第2面に配置され、P端子及びN端子は絶縁基板を間に挟むように積層配置されている。このため、絶縁基板を挟んで積層配置された幅の広い板状のP端子及びN端子に反対方向に電流が流れることになり、インダクタンスを低減する効果をさらに向上させることができる。   According to this configuration, the insulating substrate having the first surface and the second surface is further provided, the P terminal and the N terminal are each formed in a plate shape having a width larger than the thickness, and the P terminal is disposed on the first surface of the insulating substrate. The N terminal is disposed on the second surface of the insulating substrate, and the P terminal and the N terminal are stacked so as to sandwich the insulating substrate therebetween. For this reason, a current flows in the opposite direction to the wide plate-like P terminal and N terminal arranged in layers with the insulating substrate interposed therebetween, and the effect of reducing the inductance can be further improved.

この場合、第1スイッチング素子は絶縁基板の第1面に配置され、第2スイッチング素子は絶縁基板の第2面に配置されていることが好適である。   In this case, it is preferable that the first switching element is disposed on the first surface of the insulating substrate, and the second switching element is disposed on the second surface of the insulating substrate.

この構成によれば、第1スイッチング素子及び第2スイッチング素子それぞれの相が絶縁基板を挟んで積層配置されているため、絶縁基板への投影面積が小さくなり、パワーモジュールを小型化することができる。   According to this configuration, since the phases of the first switching element and the second switching element are stacked with the insulating substrate interposed therebetween, the projected area onto the insulating substrate is reduced, and the power module can be reduced in size. .

この場合、絶縁基板の第1面に配置されたU相用の第1スイッチング素子、絶縁基板の第1面に配置されたV相用の第1スイッチング素子及び絶縁基板の第1面に配置されたW相用の第1スイッチング素子と、絶縁基板の第2面に配置されたU相用の第2スイッチング素子、絶縁基板の第2面に配置されたV相用の第2スイッチング素子及び絶縁基板の第2面に配置されたW相用の第2スイッチング素子とを備え、U相用の第1スイッチング素子、V相用の第1スイッチング素子及びW相用の第1スイッチング素子は、U相用の第1出力端子、V相用の第1出力端子及びW相用の第1出力端子と、共通するP端子とをそれぞれ有し、U相用の第2スイッチング素子、V相用の第2スイッチング素子及びW相用の第2スイッチング素子は、U相用の第2出力端子、V相用の第2出力端子及びW相用の第2出力端子と、共通するN端子とをそれぞれ有することが好適である。   In this case, the U-phase first switching element disposed on the first surface of the insulating substrate, the V-phase first switching element disposed on the first surface of the insulating substrate, and the first surface of the insulating substrate. First switching element for W phase, second switching element for U phase disposed on the second surface of the insulating substrate, second switching element for V phase disposed on the second surface of the insulating substrate, and insulation A second switching element for W phase disposed on the second surface of the substrate, the first switching element for U phase, the first switching element for V phase, and the first switching element for W phase are U A first output terminal for the phase, a first output terminal for the V phase, a first output terminal for the W phase, and a common P terminal, and a second switching element for the U phase, The second switching element and the second switching element for the W phase are the U phase. A second output terminal of a second output terminal for the second output terminal and a W-phase for the V-phase, it is preferable to have each an N terminal in common.

この構成によれば、絶縁基板の第1面にU相用、V相用及びW相用の三相分の第1スイッチング素子が配置され、絶縁基板の第2面にU相用、V相用及びW相用の三相分の第2スイッチング素子が配置され、U相用、V相用及びW相用の三相分の第1スイッチング素子はそれぞれU相用、V相用及びW相用の三相分の第1出力端子と共通するP端子とを有し、U相用、V相用及びW相用の三相分の第2スイッチング素子はそれぞれU相用、V相用及びW相用の三相分の第2出力端子と共通するN端子とを有する。したがって、三相分のP端子とN端子とのPN配線において、単純な回路配線パターンで互いの電流の方向が正反対になるように並列に配置することができ(PN並走)、三相分のPN配線のインダクタンスを効率良く低減することができる。   According to this configuration, the first switching elements for three phases for the U phase, the V phase, and the W phase are disposed on the first surface of the insulating substrate, and the U phase and V phase are disposed on the second surface of the insulating substrate. Second switching elements for three phases for the first and second phases are arranged, and the first switching elements for three phases for the U phase, the V phase and the W phase are respectively for the U phase, the V phase and the W phase. A first output terminal for three phases and a common P terminal, and second switching elements for three phases for U phase, V phase and W phase are for U phase, V phase and It has a second output terminal for three phases for the W phase and an N terminal in common. Therefore, in the PN wiring of the P terminal and the N terminal for three phases, it can be arranged in parallel so that the directions of the currents are opposite to each other with a simple circuit wiring pattern (PN parallel running). The inductance of the PN wiring can be efficiently reduced.

本発明のパワーモジュールによれば、インダクタンスを低減する効果を向上させることができる。   According to the power module of the present invention, the effect of reducing inductance can be improved.

実施形態に係るパワーモジュールを示す平面図である。It is a top view which shows the power module which concerns on embodiment. 図1に記載のパワーモジュールのA−A線における断面図である。It is sectional drawing in the AA line of the power module of FIG. 図1に記載のパワーモジュールのB−B線における断面図である。It is sectional drawing in the BB line of the power module of FIG. P放熱板を示す平面図である。It is a top view which shows P heat sink. P端子板を示す平面図である。It is a top view which shows a P terminal board. 上相出力端子板を示す平面図である。It is a top view which shows an upper phase output terminal board. 実施形態に係るパワーモジュールの1相分の回路図である。It is a circuit diagram for one phase of the power module concerning an embodiment. 実施形態に係るパワーモジュールの上相側を製造する工程を示すフローチャートである。It is a flowchart which shows the process of manufacturing the upper phase side of the power module which concerns on embodiment. 図1に記載のパワーモジュールの上相側の製造工程において第1リフロー処理が施される時点でのA−A線における断面図である。It is sectional drawing in the AA line | wire in the time of a 1st reflow process being performed in the manufacturing process of the upper phase side of the power module shown in FIG. 図1に記載のパワーモジュールの上相側の製造工程において第1リフロー処理が施される時点でのB−B線における断面図である。It is sectional drawing in the BB line | wire at the time of a 1st reflow process being performed in the manufacturing process by the side of the upper phase of the power module shown in FIG. 図1に記載のパワーモジュールの上相側の製造工程においてスイッチング素子と制御端子とがワイヤボンディングされた時点でのA−A線における断面図である。It is sectional drawing in the AA line | wire at the time of a switching element and a control terminal being wire-bonded in the manufacturing process of the upper phase side of the power module shown in FIG. 図1に記載のパワーモジュールの上相側の製造工程において第2リフロー処理が施される時点でのA−A線における断面図である。It is sectional drawing in the AA line | wire at the time of a 2nd reflow process being performed in the manufacturing process by the side of the upper phase of the power module shown in FIG. 図1に記載のパワーモジュールの上相側の製造工程において第2リフロー処理が施される時点でのB−B線における断面図である。It is sectional drawing in the BB line | wire at the time of performing a 2nd reflow process in the manufacturing process of the upper phase side of the power module shown in FIG. 図1に記載のパワーモジュールの上相側の製造工程においてモールド成型がなされた時点でのA−A線における断面図である。It is sectional drawing in the AA line | wire at the time of mold shaping | molding in the manufacturing process by the side of the upper phase of the power module shown in FIG. 図1に記載のパワーモジュールの上相側の製造工程においてモールド成型がなされた時点でのB−B線における断面図である。It is sectional drawing in the BB line at the time of mold shaping | molding in the manufacturing process of the upper phase side of the power module shown in FIG. 図1に記載のパワーモジュールの上相側の製造工程においてモールド成型がなされた時点での平面図である。FIG. 2 is a plan view at the time when molding is performed in the manufacturing process on the upper phase side of the power module illustrated in FIG. 1. 図16に記載のパワーモジュールにP端子板が接合された時点での平面図である。It is a top view at the time of joining a P terminal board to the power module of FIG. 図17に記載のパワーモジュールのA−A線における断面図である。It is sectional drawing in the AA line of the power module of FIG. 図17に記載のパワーモジュールのB−B線における断面図である。It is sectional drawing in the BB line of the power module of FIG. 本実施形態のパワーモジュールにおける上相出力端子板、P端子板、N端子板及び下相出力端子板を流れる電流とその作用とを示す図である。It is a figure which shows the electric current which flows through the upper phase output terminal board in the power module of this embodiment, a P terminal board, an N terminal board, and a lower phase output terminal board, and its effect | action. 従来のパワーモジュールの1相分の回路図である。It is a circuit diagram for one phase of the conventional power module. 従来のパワーモジュールにおけるP端子板、出力端子板及びN端子板を流れる電流とその作用とを示す図である。It is a figure which shows the electric current which flows through the P terminal board in the conventional power module, an output terminal board, and an N terminal board, and its effect | action.

以下、図面を参照して、本発明の実施形態に係るパワーモジュールについて説明する。図1の平面図に示すように、本実施形態のパワーモジュール10は、封止樹脂20に封止されたU相モジュール30U、V相モジュール30V及びW相モジュール30Wを備えている。本実施形態のパワーモジュール10は、各相が2個のスイッチング素子を用いたU相、V相及びW相の三相インバータとして構成されている。   Hereinafter, a power module according to an embodiment of the present invention will be described with reference to the drawings. As shown in the plan view of FIG. 1, the power module 10 of this embodiment includes a U-phase module 30U, a V-phase module 30V, and a W-phase module 30W that are sealed with a sealing resin 20. The power module 10 of this embodiment is configured as a three-phase inverter of U phase, V phase, and W phase using two switching elements for each phase.

図1の平面図、図2のA−A線による断面図及び図3のB−B線による断面図に示すように、パワーモジュール10は、絶縁基板40の絶縁基板上面40tに、図4の平面図に示すようなU相モジュール30U、V相モジュール30V及びW相モジュール30Wの三相に共通のP放熱板Rが配置されている。P放熱板RはP端子板接合用端子JTを有する。同様に、絶縁基板40の絶縁基板下面40bに、U相モジュール30U、V相モジュール30V及びW相モジュール30Wの三相に共通のN放熱板Rが配置されている。N放熱板RはN端子板接合用端子JTを有する。絶縁基板40は、インダクタンスを低減する効果を向上させるため、0.5mm以下の厚さであることが好ましい。 As shown in the plan view of FIG. 1, the cross-sectional view taken along the line AA in FIG. 2, and the cross-sectional view taken along the line BB in FIG. 3, the power module 10 As shown in the plan view, a common P heat radiation plate RP is disposed in the three phases of the U-phase module 30U, the V-phase module 30V, and the W-phase module 30W. P radiating plate R P has the P terminal plate connecting terminal JT P. Similarly, the insulating substrate bottom surface 40b of the insulating substrate 40, U-phase module 30 U, common N radiating plate R N to the three-phase V-phase modules 30V and W-phase module 30W are arranged. N radiating plate R N has the N terminal plate connecting terminal JT N. Insulating substrate 40 preferably has a thickness of 0.5 mm or less in order to improve the effect of reducing inductance.

図1及び図3に示すように、P放熱板RにはP端子板接合用端子JTを介して、図5の平面図に示すようなU相モジュール30U、V相モジュール30V及びW相モジュール30Wの三相に共通のP端子板Pが接合されている。P端子板Pは、厚さよりも幅が広い板状のバスバとなっている。同様に、N放熱板RにはN端子板接合用端子JTを介して、U相モジュール30U、V相モジュール30V及びW相モジュール30Wの三相に共通の厚さよりも幅が広い板状のN端子板Nが接合されている。N端子板Nは、厚さよりも幅が広い板状のバスバとなっている。 As shown in FIGS. 1 and 3, the P radiating plate R P through P terminal board connecting terminal JT P, U-phase module 30U as shown in the plan view of FIG. 5, V-phase module 30V and the W-phase A common P terminal plate P is joined to the three phases of the module 30W. The P terminal board P is a plate-like bus bar that is wider than the thickness. Similarly, the N radiating plate R N through N terminal board connecting terminal JT N, U-phase module 30 U, V-phase module 30V and the W-phase module common wide plate-like than the thickness in the three phases of 30W N terminal plates N are joined. The N terminal plate N is a plate-like bus bar that is wider than the thickness.

P放熱板Rの絶縁基板40の反対側の面には、U相モジュール30U、V相モジュール30V及びW相モジュール30Wの三相ごとに、ハンダ80を介して第1トランジスタTr1及び第1ダイオードD1が接合されている。第1トランジスタTr1は、たとえばパワーMOSトランジスタやIGBT(絶縁ゲート型バイポーラトランジスタ)等であり、第1ダイオードD1は、還流ダイオードとして機能する。第1トランジスタTr1及び第1ダイオードD1のP放熱板Rと反対側の面には、それぞれハンダ80を介してスペーサ60が接合されている。 On the opposite side of the P radiator plate R P of the insulating substrate 40, U-phase module 30 U, each three-phase V-phase modules 30V and W-phase module 30 W, the first transistor Tr1 and the first diode via a solder 80 D1 is joined. The first transistor Tr1 is, for example, a power MOS transistor or an IGBT (insulated gate bipolar transistor), and the first diode D1 functions as a freewheeling diode. The surface opposite to the P radiator plate R P of the first transistor Tr1 and the first diode D1, the spacer 60 via the solder 80 respectively are joined.

スペーサ60の第1トランジスタTr1又は第1ダイオードD1と反対側の面には、それぞれハンダ80を介してU相モジュール30U、V相モジュール30V及びW相モジュール30Wの三相ごとに図6に示すような上相出力端子板Uが接合されている。上相出力端子板Uは、スペーサ60に接合された位置から先端が屈曲して、P放熱板Rと絶縁基板上面40tからの距離が同じ位置で封止樹脂20から突出している。第1トランジスタTr1には、ボンディングワイヤ70を介して制御端子50が接合されている。このようにして、絶縁基板上面40tには、U相、V相及びW相の上相UPが形成される。 As shown in FIG. 6 for each of the three phases of the U-phase module 30U, the V-phase module 30V, and the W-phase module 30W on the surface of the spacer 60 opposite to the first transistor Tr1 or the first diode D1, respectively. upper phase output terminal plates U P are joined such. Upper phase output terminal plates U P is bent tip from the bonded position in the spacer 60, a distance from the insulating substrate top surface 40t and P radiating plate R P is protruded from the sealing resin 20 at the same position. A control terminal 50 is bonded to the first transistor Tr1 via a bonding wire 70. In this way, the upper phase UP of the U phase, the V phase, and the W phase is formed on the upper surface 40t of the insulating substrate.

同様にして、N放熱板Rの絶縁基板40の反対側の面には、ハンダ80、第2トランジスタTr2、第2ダイオードD2、スペーサ60、下相出力端子板UNが順次接合されている。このようにして、絶縁基板下面40bには、U相、V相及びW相の下相BPが形成される。U相、V相及びW相の各相には、図7に示すような上相UPに第1トランジスタTr1及び第1ダイオードD1を用い、下相に第2トランジスタTr2及び第2ダイオード2を用いたインバータ回路が形成される。 Similarly, the opposite surface of the insulating substrate 40 of N radiating plate R N, the solder 80, the second transistor Tr2, a second diode D2, the spacer 60, the lower phase output terminal plates UN are successively joined. In this way, the lower phase BP of the U phase, the V phase, and the W phase is formed on the lower surface 40b of the insulating substrate. For each of the U phase, V phase and W phase, the first transistor Tr1 and the first diode D1 are used for the upper phase UP as shown in FIG. 7, and the second transistor Tr2 and the second diode 2 are used for the lower phase. Inverter circuit is formed.

図2及び図7に示すように、パワーモジュール10では、領域Z1において、絶縁基板40を間に挟んでP端子板PとN端子板Nとがその電流の向きが互いに正反対の平行な方向になるように配置されている。領域Z2において、P端子板Pと上相出力端子板Uとがその電流の向きが互いに正反対の平行な方向になるように配置されている。領域Z3において、N端子板Nと下相出力端子板Uとがその電流の向きが互いに正反対の平行な方向になるように配置されている。図3に示すように、領域Z4において、絶縁基板40を間に挟んでP放熱板RとN放熱板Rとがその電流の向きが互いに正反対の平行な方向になるように配置されている。P端子板P,N端子板Nと、上相出力端子板U,下相出力端子板Uとの間は、絶縁紙や上相出力端子板U,下相出力端子板Uにラミネート等による絶縁体を配置することで絶縁されている。 As shown in FIGS. 2 and 7, in the power module 10, in the region Z <b> 1, the P terminal plate P and the N terminal plate N are in parallel directions in which the directions of currents are opposite to each other with the insulating substrate 40 interposed therebetween. It is arranged to be. In the region Z2, the orientation of the P terminal plate P and the upper phase output terminal plates U P and its current is arranged to be opposite in a direction parallel to each other. In the region Z3, and the N terminal plate N and the lower-phase output terminal plates U N direction of the current is arranged to be opposite in a direction parallel to each other. As shown in FIG. 3, in the region Z4, is sandwiched therebetween arranged as P radiator plate R P and N radiating plate R N and the direction of the current is opposite the direction parallel to each other between the insulating substrate 40 Yes. P terminal plate P, a N terminal plate N, the upper-phase output terminal plates U P, is between the lower phase output terminal plates U N, insulating paper and the upper phase output terminal plates U P, the lower phase output terminal plates U N It is insulated by placing an insulator such as a laminate.

以下、本実施形態のパワーモジュール10の製造工程について説明する。以下の説明では、絶縁基板上面40t上に上相UPを形成する工程について説明する。図8のフローチャート、図9のA−A線による断面図及び図10のB−B線による断面図に示すように、リードフレームとなるP放熱板Rに、ハンダ80、第1トランジスタTr1、第1ダイオードD1、スペーサ60が順次接合され、第1リフロー処理が施される(S11)。図8及び図11のA−A線による断面図に示すように、第1トランジスタTr1と制御端子50とがボンディングワイヤ70によりワイヤボンディングされる(S12)。 Hereinafter, the manufacturing process of the power module 10 of this embodiment is demonstrated. In the following description, a process of forming the upper phase UP on the insulating substrate upper surface 40t will be described. As shown in the flowchart of FIG. 8, the cross-sectional view taken along line AA in FIG. 9, and the cross-sectional view taken along line BB in FIG. 10, solder P , first transistor Tr 1, The first diode D1 and the spacer 60 are sequentially joined, and the first reflow process is performed (S11). 8 and 11, the first transistor Tr1 and the control terminal 50 are wire-bonded by the bonding wire 70 (S12).

図8、図12のA−A線による断面図及び図13のB−B線による断面図に示すように、U相モジュール30U、V相モジュール30V及びW相モジュール30Wの三相ごとに、出力側のリードフレームである上相出力端子板Uが接合され、第2リフロー処理がなされる(S13)。この工程後には、後のモールド成型による封止樹脂20の終端において、上相出力端子板UとP放熱板Rとが、絶縁基板上面40tからの距離が同じ位置で封止樹脂20から突出するように配置される。図8に示すように、封止樹脂20と各部品との密着性を高めるためにプライマーコーティング処理がなされる(S14)。 As shown in the cross-sectional view taken along the line AA in FIGS. 8 and 12 and the cross-sectional view taken along the line BB in FIG. upper phase output terminal plates U P is a lead frame side are joined, the second reflow process is performed (S13). After this step, at the end of the sealing resin 20 by molding after the upper phase output terminal plates U P and the P radiating plate R P is the distance from the insulating substrate top surface 40t from the sealing resin 20 at the same position It is arranged to protrude. As shown in FIG. 8, a primer coating process is performed to improve the adhesion between the sealing resin 20 and each component (S14).

図8、図14のA−A線による断面図、図15のB−B線による断面図及び図16の平面図に示すように、モールド成型がなされた封止樹脂20による封止が行われる(S15)。本実施形態では、封止樹脂20の終端において、上相出力端子板UとP放熱板Rとが、絶縁基板上面40tからの距離が同じ位置で封止樹脂20から突出するように配置されている。したがって、絶縁基板上面40tから当該距離だけ離れた線をモールド成型のパーティングラインとすることにより、上相出力端子板UとP放熱板Rとのパーティングラインを一致させて、容易にモールド成型を行うことができる。 As shown in the cross-sectional view taken along the line AA in FIGS. 8 and 14, the cross-sectional view taken along the line BB in FIG. 15, and the plan view in FIG. 16, the sealing with the sealing resin 20 that has been molded is performed. (S15). In the present embodiment, at the end of the sealing resin 20, the upper-phase output terminal plates U P and the P radiating plate R P is arranged so that a distance from the insulating substrate top surface 40t protrudes from the sealing resin 20 at the same position Has been. Therefore, a line apart the distance from the insulating substrate top surface 40t by the parting line of the molding, by matching the parting line between the upper phase output terminal plates U P and P radiating plate R P, easily Molding can be performed.

図8、図17の平面図、図18のA−A線による断面図及び図19のB−B線による断面図に示すように、領域Z5の部分でP端子板PとP端子板接合用端子JTとが接合される(S16)。絶縁基板下面40b上に下相BPを形成する工程も上記と同様に行うことができる。 As shown in the plan views of FIGS. 8 and 17, the cross-sectional view taken along the line AA in FIG. 18, and the cross-sectional view taken along the line BB in FIG. and the terminal JT P is joined (S16). The step of forming the lower phase BP on the insulating substrate lower surface 40b can be performed in the same manner as described above.

本実施形態によれば、高電位側のP端子板Pと低電位側の上相出力端子板Uとに接合された第1トランジスタTr1と、低電位側のN端子板Nと高電位側の下相出力端子板Uとに接合された第2トランジスタTr2とを備えたパワーモジュール10において、P端子板Pを流れる電流の方向とN端子板Nを流れる電流の方向が互いに正反対の平行な方向となるようにP端子板PとN端子板Nとが並列に配置され、P端子板Pを流れる電流の方向と上相出力端子板Uを流れる電流の方向が互いに正反対の平行な方向となるように、上相出力端子板Uが、N端子板Nと上相出力端子板Uとの間にP端子板Pを挟むように配置され、N端子板Nを流れる電流の方向と下相出力端子板Uを流れる電流の方向が互いに正反対の平行な方向となるように、下相出力端子板UがP端子板Pと下相出力端子板Uとの間にN端子板Nを挟むように配置されている。 According to this embodiment, the first transistor Tr1, which is joined to the upper phase output terminal plates U P P-terminal plate P and the low potential side of the high potential side, the low potential side of the N terminal plate N and the high potential side in the power module 10 and a second transistor Tr2, which is joined to the lower-phase output terminal plates U N of parallel directions opposite to each other in the current flowing direction and N terminal plate N of the current flowing through the P terminal plate P such become so the P terminal plate P and N terminal plate N direction are arranged in parallel, the opposite of the parallel direction of the current flowing direction and the upper phase output terminal plates U P of the current flowing through the P terminal plate P such that the direction, the upper-phase output terminal plates U P is disposed so as to sandwich the P terminal plate P between the N terminal plate N and the upper phase output terminal plates U P, the current flowing through the N terminal plate N parallel towards the direction opposite to each other in the current flowing direction and the lower-phase output terminal plates U N And so that, are arranged so as to sandwich the N terminal plate N between the lower phase output terminal plates U N is P terminal plate P and the lower-phase output terminal plates U N.

このため、図2、図7及び図20に示すように、領域Z1においてP端子板PとN端子板Pとを流れる電流、領域Z2においてP端子板と上相出力端子板Uとを流れる電流、及び領域Z3においてN端子板Nと下相出力端子板Uとを流れる電流により互いに三箇所で磁界が相殺され、インダクタンスを低減する効果を向上させることができる。さらに、本実施形態では、領域Z4において、絶縁基板40を間に挟んでP放熱板RとN放熱板Rとがその電流の向きが互いに正反対の平行な方向になるように配置されているため、領域Z4においても、インダクタンスを低減する効果を向上させることができる。領域Z1〜Z4において、インダクタンスを低減することで、スイッチング時のサージ電圧をさらに抑制することができ、より高周波での動作を行うことが可能となり、周辺部品であるコンデンサ、リアクトルの小型化及び低コスト化への効果が期待できる。 Therefore, as shown in FIGS. 2, 7 and 20, the current flowing through the P terminal plate P and N terminal plate P in the region Z1, flows the upper phase output terminal plates U P and P terminal plate in the region Z2 current, and the magnetic field are canceled out by each other three positions by a current flowing through the N terminal plate N and the lower-phase output terminal plates U N in the region Z3, it is possible to improve the effect of reducing the inductance. Furthermore, in the present embodiment, in the region Z4, is sandwiched therebetween arranged as P radiator plate R P and N radiating plate R N and the direction of the current is opposite the direction parallel to each other between the insulating substrate 40 Therefore, also in the region Z4, the effect of reducing the inductance can be improved. In the regions Z1 to Z4, by reducing the inductance, the surge voltage at the time of switching can be further suppressed, operation at a higher frequency can be performed, and the peripheral components such as capacitors and reactors can be downsized and reduced. The effect on cost can be expected.

また、本実施形態では、絶縁基板上面40t及び絶縁基板40bを有する絶縁基板40をさらに備え、P端子板P及びN端子板Pはそれぞれ厚さよりも幅が大きい板状をなし、P端子板Nは絶縁基板上面40tに配置され、N端子板Nは絶縁基板下面40bに配置され、P端子板P及びN端子板Nは絶縁基板40を間に挟むように積層配置されている。このため、絶縁基板40を挟んで積層配置された幅の広い板状のP端子板P及びN端子板Nに反対方向に電流が流れることになり、インダクタンスを低減する効果をさらに向上させることができる。   In the present embodiment, the insulating substrate 40 further includes an insulating substrate upper surface 40t and an insulating substrate 40b. The P terminal plate P and the N terminal plate P each have a plate shape whose width is larger than the thickness, and the P terminal plate N Is arranged on the upper surface 40t of the insulating substrate, the N terminal plate N is arranged on the lower surface 40b of the insulating substrate, and the P terminal plate P and the N terminal plate N are laminated so as to sandwich the insulating substrate 40 therebetween. For this reason, a current flows in the opposite direction to the wide plate-like P terminal plate P and N terminal plate N that are stacked with the insulating substrate 40 interposed therebetween, and the effect of reducing the inductance can be further improved. it can.

また、本実施形態では、第1トランジスタTr1の上相UP及び第2トランジスタTr2の下相BPそれぞれが絶縁基板40を挟んで積層配置されているため、絶縁基板40への投影面積が小さくなり、パワーモジュールを小型化することができる。   Further, in the present embodiment, since the upper phase UP of the first transistor Tr1 and the lower phase BP of the second transistor Tr2 are stacked with the insulating substrate 40 interposed therebetween, the projected area onto the insulating substrate 40 is reduced. The power module can be reduced in size.

また、本実施形態では、絶縁基板上面40tにU相モジュール30U、V相モジュール30V及びW相モジュール30Wの三相分の第1トランジスタTr1が配置され、絶縁基板下面40bにU相モジュール30U、V相モジュール30V及びW相モジュール30Wの三相分の第2トランジスタTr2が配置され、U相用、V相用及びW相用の三相分の第1トランジスタTr1はそれぞれU相用、V相用及びW相用の三相分の上相出力端子板Uと共通するP端子板Pとに接合され、U相用、V相用及びW相用の三相分の第2スイッチング素子はそれぞれU相用、V相用及びW相用の三相分の下相出力端子板Uと共通するN端子板Nとに接合されている。したがって、三相分のP端子板PとN端子板NとのPN配線において、単純な回路配線パターンで互いの電流の方向が正反対になるように並列に配置することができ(PN並走)、三相分のPN配線のインダクタンスを効率良く低減することができる。 In this embodiment, the first transistor Tr1 for three phases of the U-phase module 30U, the V-phase module 30V, and the W-phase module 30W is disposed on the insulating substrate upper surface 40t, and the U-phase modules 30U, V are disposed on the insulating substrate lower surface 40b. The second transistors Tr2 for the three phases of the phase module 30V and the W phase module 30W are arranged, and the first transistors Tr1 for the three phases for the U phase, the V phase, and the W phase are for the U phase and the V phase, respectively. and is bonded to the P terminal plate P in common with the upper-phase output terminal plates U P for three phases for W-phase, U-phase, the second switching elements of three phases for the V-phase and W-phase, respectively U-phase, are joined to the N terminal plate N common to the lower-phase output terminal plates U N for three phases for V-phase and W-phase. Therefore, in the PN wiring of the P terminal board P and the N terminal board N for three phases, it can be arranged in parallel so that the directions of the currents are opposite to each other with a simple circuit wiring pattern (PN parallel running). The inductance of the three-phase PN wiring can be efficiently reduced.

なお、本発明は上記実施形態に限定されず、様々な変形態様が可能である。   In addition, this invention is not limited to the said embodiment, A various deformation | transformation aspect is possible.

10…パワーモジュール、20…封止樹脂、30U…U相モジュール、30V…V相モジュール、30W…W相モジュール、40…絶縁基板、40t…絶縁基板上面、40b…絶縁基板下面、50…制御端子、60…スペーサ、70…ボンディングワイヤ、80…ハンダ、R…P放熱板、R…N放熱板、JT…P端子板接合用端子、JT…N端子板接合用端子、P…P端子板、N…N端子板、U…上相出力端子板、U…下相出力端子板、U…出力端子板、Tr1…第1トランジスタ、Tr2…第2トランジスタ、D1…第1ダイオード、D2…第2ダイオード、UP…上相、BP…下相、Z1〜Z5,z1〜z2…領域。 DESCRIPTION OF SYMBOLS 10 ... Power module, 20 ... Sealing resin, 30U ... U phase module, 30V ... V phase module, 30W ... W phase module, 40 ... Insulating substrate, 40t ... Insulating substrate upper surface, 40b ... Insulating substrate lower surface, 50 ... Control terminal , 60 ... spacer 70 ... bonding wire, 80 ... solder, R P ... P radiating plate, R N ... N radiating plate, JT P ... P terminal board connecting terminal, JT N ... N terminal plate connecting terminal, P ... P terminal plate, N ... N terminal plate, U P ... upper phase output terminal plate, U N ... lower phase output terminal plate, U ... output terminal plate, Tr1 ... first transistor, Tr2 ... second transistor, D1 ... first Diode, D2 ... second diode, UP ... upper phase, BP ... lower phase, Z1-Z5, z1-z2 ... region.

Claims (4)

高電位側のP端子と前記P端子よりも低電位側の第1出力端子とを有する第1スイッチング素子と、
低電位側のN端子と前記N端子よりも高電位側の第2出力端子とを有する第2スイッチング素子と、
を備え、
前記P端子を流れる電流の方向と前記N端子を流れる電流の方向が互いに正反対の平行な方向となるように、前記P端子と前記N端子とが並列に配置され、
前記P端子を流れる電流の方向と前記第1出力端子を流れる電流の方向が互いに正反対の平行な方向となるように、前記第1出力端子が、前記N端子と前記第1出力端子との間に前記P端子を挟むように配置され、
前記N端子を流れる電流の方向と前記第2出力端子を流れる電流の方向が互いに正反対の平行な方向となるように、前記第2出力端子が、前記P端子と前記第2出力端子との間に前記N端子を挟むように配置されている、パワーモジュール。
A first switching element having a P terminal on the high potential side and a first output terminal on the lower potential side than the P terminal;
A second switching element having an N terminal on a low potential side and a second output terminal on a higher potential side than the N terminal;
With
The P terminal and the N terminal are arranged in parallel so that the direction of the current flowing through the P terminal and the direction of the current flowing through the N terminal are parallel to each other.
The first output terminal is between the N terminal and the first output terminal so that the direction of the current flowing through the P terminal and the direction of the current flowing through the first output terminal are parallel to each other. Arranged to sandwich the P terminal,
The second output terminal is between the P terminal and the second output terminal so that the direction of the current flowing through the N terminal and the direction of the current flowing through the second output terminal are parallel to each other. A power module disposed so as to sandwich the N terminal therebetween.
第1面及び第2面を有する絶縁基板をさらに備え、
前記P端子及び前記N端子はそれぞれ厚さよりも幅が大きい板状をなし、
前記P端子は前記絶縁基板の前記第1面に配置され、
前記N端子は前記絶縁基板の前記第2面に配置され、
前記P端子及び前記N端子は前記絶縁基板を間に挟むように積層配置されている、請求項1に記載のパワーモジュール。
An insulating substrate having a first surface and a second surface;
The P terminal and the N terminal each have a plate shape whose width is larger than the thickness,
The P terminal is disposed on the first surface of the insulating substrate;
The N terminal is disposed on the second surface of the insulating substrate;
The power module according to claim 1, wherein the P terminal and the N terminal are stacked so as to sandwich the insulating substrate therebetween.
前記第1スイッチング素子は前記絶縁基板の前記第1面に配置され、
前記第2スイッチング素子は前記絶縁基板の前記第2面に配置されている、請求項2に記載のパワーモジュール。
The first switching element is disposed on the first surface of the insulating substrate;
The power module according to claim 2, wherein the second switching element is disposed on the second surface of the insulating substrate.
前記絶縁基板の前記第1面に配置されたU相用の前記第1スイッチング素子、前記絶縁基板の前記第1面に配置されたV相用の前記第1スイッチング素子及び前記絶縁基板の前記第1面に配置されたW相用の前記第1スイッチング素子と、
前記絶縁基板の前記第2面に配置されたU相用の前記第2スイッチング素子、前記絶縁基板の前記第2面に配置されたV相用の前記第2スイッチング素子及び前記絶縁基板の前記第2面に配置されたW相用の前記第2スイッチング素子と、
を備え、
前記U相用の前記第1スイッチング素子、前記V相用の前記第1スイッチング素子及び前記W相用の前記第1スイッチング素子は、前記U相用の前記第1出力端子、前記V相用の前記第1出力端子及び前記W相用の前記第1出力端子と、共通する前記P端子とをそれぞれ有し、
前記U相用の前記第2スイッチング素子、前記V相用の前記第2スイッチング素子及び前記W相用の前記第2スイッチング素子は、前記U相用の前記第2出力端子、前記V相用の前記第2出力端子及び前記W相用の前記第2出力端子と、共通する前記N端子とをそれぞれ有する、請求項3に記載のパワーモジュール。
The first switching element for U-phase disposed on the first surface of the insulating substrate, the first switching element for V-phase disposed on the first surface of the insulating substrate, and the first switching element for the insulating substrate. The first switching element for the W phase disposed on one surface;
The second switching element for U-phase disposed on the second surface of the insulating substrate, the second switching element for V-phase disposed on the second surface of the insulating substrate, and the second switching element for the insulating substrate. The second switching element for W phase disposed on two surfaces;
With
The first switching element for the U phase, the first switching element for the V phase, and the first switching element for the W phase are the first output terminal for the U phase, the V phase The first output terminal and the first output terminal for the W phase, and the common P terminal,
The second switching element for the U phase, the second switching element for the V phase, and the second switching element for the W phase are the second output terminal for the U phase, the second phase switching element for the V phase, 4. The power module according to claim 3, further comprising the second output terminal, the second output terminal for the W phase, and the common N terminal. 5.
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