JPH11177021A - Electrode structure for semiconductor switch - Google Patents

Electrode structure for semiconductor switch

Info

Publication number
JPH11177021A
JPH11177021A JP33886497A JP33886497A JPH11177021A JP H11177021 A JPH11177021 A JP H11177021A JP 33886497 A JP33886497 A JP 33886497A JP 33886497 A JP33886497 A JP 33886497A JP H11177021 A JPH11177021 A JP H11177021A
Authority
JP
Japan
Prior art keywords
electrode
main current
semiconductor switch
semiconductor
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33886497A
Other languages
Japanese (ja)
Inventor
Kouichi Makinose
公一 牧野瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Industries Corp
Original Assignee
Toyoda Automatic Loom Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Automatic Loom Works Ltd filed Critical Toyoda Automatic Loom Works Ltd
Priority to JP33886497A priority Critical patent/JPH11177021A/en
Publication of JPH11177021A publication Critical patent/JPH11177021A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49431Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49433Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide electrode structure of a semiconductor switch, in which generation of a switching loss or a serge voltage can be reduced by preventing generation of inductance. SOLUTION: Plural semiconductor chips 2 are directly placed on a drain electrode 3 used also as a heat radiating plate, and source electrodes 4 and 5 and a gate electrode 6 are placed on positions so that the semiconductor chip 2 can be surrounded. The source electrodes 4 and 5 and the gate electrode 6 are placed by strongly fixing resin 7 for insulation between those electrodes and the drain electrode 3 and electrically insulating them, and each electrode is connected through plural thin bonding wires 8 with the semiconductor chip 2 in parallel. The source electrode 4 is formed in a 'U' shape so that the top plate can be made wide and large, and the top plate of the 'U'-shaped source electrode and the drain electrode are arranged adjacent in parallel. Thus, currents are allowed to flow on each electrode so that inductance on each electrode can be offset by the mutual inductance effect.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、パッケージングさ
れた電力用の半導体スイッチに関し、パッケージ内配線
のインダクタンスによるサージ電圧およびスイッチング
ロスの低減を図るよう改良された電極構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packaged power semiconductor switch, and more particularly to an improved electrode structure for reducing a surge voltage and a switching loss due to an inductance of wiring in a package.

【0002】[0002]

【従来の技術】今日、大電流のスイッチングを行う電力
用の半導体スイッチが広く使用されている。例えば、電
気自動車やバッテリー・フォークリフト等のような電気
モータ駆動の車両に使用されるモータ・コントロール装
置においては、走行用または荷役用のモータに電力を供
給するインバータのスイッチング用デバイスとして、上
述の半導体スイッチが使用されている。このような半導
体スイッチは大電流のスイッチングを行うため熱が発生
する。このため、半導体スイッチの内部回路は放熱する
ための金属性のパッケージケースで覆われている。
2. Description of the Related Art Today, power semiconductor switches for switching large currents are widely used. For example, in a motor control device used for an electric motor-driven vehicle such as an electric vehicle or a battery forklift, the semiconductor switching device described above is used as a switching device of an inverter that supplies power to a traveling or cargo handling motor. Switch is used. Such a semiconductor switch generates heat due to switching of a large current. For this reason, the internal circuit of the semiconductor switch is covered with a metal package case for radiating heat.

【0003】図3は、この半導体スイッチ1を例えばM
OSFETとした場合の内部回路の具体的な構成の一例
を示すものである(以降、MOSFET構造のものを半
導体スイッチの具体例として説明する)。この図におい
て、複数個の半導体チップ2が放熱板と兼用のドレイン
電極3上に直接載置され、さらにソース電極4とゲート
電極6が前記半導体チップ2を挟むような位置で載置さ
れる。ここで前記ソース電極4とゲート電極6はドレイ
ン電極3との間に絶縁用樹脂7を狭着して電気的に絶縁
した上で載置され、また各電極は細いボンディングワイ
ヤ8を複数本並列で半導体チップ2と接続される構成と
なる。
FIG. 3 shows that this semiconductor switch 1 is, for example, M
This shows an example of a specific configuration of an internal circuit in the case of using an OSFET (hereinafter, a MOSFET structure is described as a specific example of a semiconductor switch). In this figure, a plurality of semiconductor chips 2 are directly mounted on a drain electrode 3 also serving as a heat sink, and further, a source electrode 4 and a gate electrode 6 are mounted at positions so as to sandwich the semiconductor chip 2. Here, the source electrode 4 and the gate electrode 6 are placed after being electrically insulated by tightly attaching an insulating resin 7 between the drain electrode 3 and a plurality of thin bonding wires 8 in parallel with each electrode. Thus, the configuration is such that the semiconductor chip 2 is connected.

【0004】このように構成された内部回路において、
ゲート電極6に入力電圧をかけることで半導体チップ2
がオン状態となり、ドレイン電極3→半導体チップ2裏
面→半導体チップ2表面→ボンディングワイヤ8→ソー
ス電極4の順に電流を流すという動作を行う。
In the internal circuit configured as described above,
By applying an input voltage to the gate electrode 6, the semiconductor chip 2
Is turned on, and an operation is performed in which a current flows in the order of drain electrode 3 → back surface of semiconductor chip 2 → front surface of semiconductor chip 2 → bonding wire 8 → source electrode 4.

【0005】そしてこのように構成された内部回路は、
一つの樹脂パッケージに一体に組み込まれ、各電極は該
パッケージの外側に表出して外部と接続される外部端子
に繋げられる。
[0005] The internal circuit thus configured is
The electrodes are integrated into one resin package, and each electrode is exposed outside the package and connected to an external terminal connected to the outside.

【0006】さらに、内部回路が空気中に存在する酸素
やイオンと化学反応を起こすことを防止するために、パ
ッケージ内部の空洞部分には下からゲル、およびエポキ
シ樹脂が充填されている構成となる。
Furthermore, in order to prevent the internal circuit from causing a chemical reaction with oxygen or ions present in the air, the cavity inside the package is filled with gel and epoxy resin from below. .

【0007】そしてこのように構成される半導体スイッ
チ1で、例えば上述した電気自動車等で通常使用される
スイッチング周波数は約10kHz程度となる。
In the semiconductor switch 1 configured as described above, the switching frequency usually used in, for example, the above-described electric vehicle or the like is about 10 kHz.

【0008】[0008]

【発明が解決しようとする課題】以上説明したように構
成される半導体スイッチを実際に前述したようなスイッ
チング周波数で使用する場合、内部回路の配線中で、特
に図中に示す各電極、およびボンディングワイヤのよう
な細い配線中で、電流が幾何的に狭い空間に集中して流
れるために、大きなインダクタンスが発生することが不
可避なものとなり、その影響によってスイッチング素子
のターンオフ時にはかなり大きなスイッチング電力のロ
ス(以下、スイッチングロスという)が発生し、また一
方スイッチング素子のターンオン時にはかなり大きなサ
ージ電圧を発生させる要因の1つとなっている。
In the case where the semiconductor switch constructed as described above is actually used at the switching frequency as described above, each of the electrodes and the bonding shown in FIG. In a thin wiring such as a wire, a current flows intensively in a narrow space geometrically, so that it is inevitable that a large inductance is generated.As a result, a considerable loss of switching power is caused when the switching element is turned off. (Hereinafter, referred to as switching loss), and is one of the causes of generating a considerably large surge voltage when the switching element is turned on.

【0009】このスイッチングロスとは、前記半導体ス
イッチのような制御端子を持つデバイスがスイッチング
を行うときに内部で発生する電力損失のことであり、前
記モータコントロール装置中には通常5〜6個の半導体
スイッチが使用されるためこれらに発生するスイッチン
グロスは累計すると多大なものとなっていた。そしてこ
の大きな損失分は例えば前記電気自動車等の駆動・操作
に大きな影響を与えると共に、損失分の電力が発熱に変
わり半導体スイッチの熱損傷の原因となっていた。
The switching loss is a power loss that occurs internally when a device having a control terminal such as the semiconductor switch performs switching. Usually, 5 to 6 switching devices are included in the motor control device. Since semiconductor switches are used, the switching losses that occur in these switches have been enormous when accumulated. The large loss has a great effect on, for example, the driving and operation of the electric vehicle and the like, and the power of the loss changes into heat generation, which causes heat damage to the semiconductor switch.

【0010】また一方、サージ電圧の発生によってもス
イッチング素子を電気的におよび熱的に損傷させる原因
となっていた。本発明は、上記課題に鑑みてなされたも
のであり、インダクタンスの発生を防止することで、ス
イッチングロスおよびサージ電圧の発生を低減すること
が可能な半導体スイッチの電極構造を提供することを目
的とする。
[0010] On the other hand, the occurrence of a surge voltage has also caused electrical and thermal damage to the switching element. The present invention has been made in view of the above problems, and an object of the present invention is to provide an electrode structure of a semiconductor switch capable of reducing the occurrence of switching loss and surge voltage by preventing the occurrence of inductance. I do.

【0011】[0011]

【課題を解決するための手段】本発明は、主に上記MO
SFETからなる半導体スイッチの課題を解決するもの
であるが、これに限らず、同様な課題を有するバイポー
ラトランジスタやサイリスタ等その他の半導体スイッチ
にも適用可能である。なお、半導体スイッチの種類で各
電極の呼称が異なるため、便宜上、各電極の機能を考慮
して”主電流入力用電極”、”主電流出力用電極”、”
制御電極”という呼称を使用する。例えばMOSFET
の場合は、ドレイン電極が主電流入力用電極に、ソース
電極が主電流出力用電極に、ゲート電極が制御電極に、
それぞれ相当する。
The present invention mainly relates to the above-mentioned MO.
The present invention solves the problem of the semiconductor switch composed of the SFET, but is not limited thereto, and is applicable to other semiconductor switches such as a bipolar transistor and a thyristor having the same problem. Since the names of the electrodes differ depending on the type of the semiconductor switch, for convenience, the “main current input electrode”, “main current output electrode”, “
The term "control electrode" is used. For example, MOSFET
In the case of, the drain electrode is the main current input electrode, the source electrode is the main current output electrode, the gate electrode is the control electrode,
Each corresponds.

【0012】そして上記課題は請求項1記載の発明によ
れば、制御電極に供給される制御信号に従って主電流入
力用電極から半導体チップを介して主電流出力用電極に
電流を供給する半導体スイッチの電極構造において、電
流の集中によるインダクタンスの発生を低減できる程度
に、前記主電流入力用電極または前記主電流出力用電極
の少なくとも一方の電極を広く大きく形成した半導体ス
イッチの電極構造を提供することにより達成できる。
According to the first aspect of the present invention, there is provided a semiconductor switch for supplying a current from a main current input electrode to a main current output electrode via a semiconductor chip in accordance with a control signal supplied to a control electrode. In the electrode structure, by providing an electrode structure of a semiconductor switch in which at least one of the main current input electrode and the main current output electrode is formed so as to be large enough to reduce the occurrence of inductance due to current concentration. Can be achieved.

【0013】この場合、各電極の厚さは通常使用される
もの以上で任意に設定でき、表面積は広ければ広いほど
効果的となる。すなわち、主電流出力用電極および主電
流入力用電極が適切な厚みを持ってより表面積が広くな
るよう形成されることにより、流れる電流の空間的拡散
が図られ、もって電流集中によるインダクタンスの発生
を防止できる。
In this case, the thickness of each electrode can be arbitrarily set to a value larger than that usually used, and the larger the surface area, the more effective. In other words, the main current output electrode and the main current input electrode are formed to have an appropriate thickness and have a larger surface area, so that the flowing current can be spatially diffused, thereby reducing inductance due to current concentration. Can be prevented.

【0014】請求項2の記載は、前記請求項1記載の発
明において、前記主電流出力用電極および前記主電流入
力用電極が平行に近接するよう配置する構成である。こ
の場合、両電極の間隔は任意に設定でき、近ければ近い
程効果的となる。すなわち、前記請求項1の発明により
電極が大きくなった分、半導体スイッチ全体のサイズが
大きくなるところ、両電極を平行に近接するよう配置す
ることで半導体スイッチ全体のサイズがコンパクトにな
ると同時に、相互インダクタンスの効果によって両電極
に発生したインダクタンスを相殺し合って全体的なイン
ダクタンスの低減が可能となる。
According to a second aspect of the present invention, in the first aspect of the present invention, the main current output electrode and the main current input electrode are arranged so as to be close to each other in parallel. In this case, the interval between the two electrodes can be set arbitrarily, and the closer the electrode is, the more effective. That is, the size of the entire semiconductor switch is increased by the size of the electrode according to the first aspect of the present invention. However, by arranging both electrodes in parallel and close to each other, the size of the entire semiconductor switch is reduced, and Due to the effect of the inductance, the inductance generated at both electrodes is canceled out, and the overall inductance can be reduced.

【0015】請求項3の記載は、前記請求項2記載の発
明において、前記主電流出力用電極に流れる電流が、前
記主電流入力用電極に流れる電流と幾何的に(空間的
に)逆方向かつ平行に流れるよう両電極が配置する構成
である。
According to a third aspect of the present invention, in the second aspect of the present invention, the current flowing through the main current output electrode is in a geometrically (spatially) opposite direction to the current flowing through the main current input electrode. Further, both electrodes are arranged so as to flow in parallel.

【0016】これにより、両電極に流れる電流の方向が
逆方向であれば両電極に発生する磁界・磁束方向も全く
逆方向となり、つまり前記請求項2の発明における相互
インダクタンスによるインダクタンスの相殺がより一層
効果的となる。
Accordingly, if the directions of the currents flowing through the two electrodes are opposite, the directions of the magnetic fields and magnetic fluxes generated at the two electrodes are also completely opposite, that is, the mutual inductance in the invention of the second aspect more effectively cancels out the inductance. It will be more effective.

【0017】請求項4の記載は、前記請求項1ないし3
のいずれか記載の発明において、前記半導体チップが、
前記主電流入力用電極または前記主電流出力用電極のど
ちらか一方と兼用であり広く大きく形成された基板上に
接続される構成である。
[0017] Claim 4 describes the first to third aspects.
In the invention according to any one of the above,
The main current input electrode or the main current output electrode is also used as one of the main current input electrode and the main current output electrode, and is connected to a wide and large substrate.

【0018】これにより、基板と兼用となる主電流用電
極と半導体チップとの間においてのインダクタンスが低
減され、かつ半導体チップの放熱が効率良く行われる。
請求項5の記載は、前記請求項1ないし3のいずれか記
載の発明において、前記半導体スイッチが、一つのパッ
ケージ内に複数個組み込まれ、隣り合う2つの半導体ス
イッチ中にそれぞれ備える主電流入力用電極同士および
主電流出力用電極同士が、該2つの半導体スイッチ間に
設定した境界線を対称中心線として線対称構造となる構
成である。
Thus, the inductance between the main current electrode, which also serves as the substrate, and the semiconductor chip is reduced, and the semiconductor chip is efficiently radiated.
According to a fifth aspect of the present invention, in the invention according to any one of the first to third aspects, a plurality of the semiconductor switches are incorporated in one package, and each of the semiconductor switches is provided in two adjacent semiconductor switches. The electrodes and the main current output electrodes have a line-symmetric structure with a boundary line set between the two semiconductor switches as a center line of symmetry.

【0019】これにより、隣り合う半導体スイッチ単位
同士で影響し合って相互インダクタンスによる個々のイ
ンダクタンスの相殺がより一層効果的となる。
As a result, the mutual influence of the adjacent semiconductor switch units affects each other, and the mutual inductance is more effectively offset.

【0020】[0020]

【発明の実施の形態】以下、本発明の実施形態例につい
て、図面を参照して詳細に説明する。尚、以下の実施形
態例において、上述した半導体スイッチはMOSFET
構造であり、主電流入力用電極がドレイン電極、主電流
出力用電極がソース電極、制御電極がゲート電極とな
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiment, the above-described semiconductor switch is a MOSFET.
The main current input electrode is a drain electrode, the main current output electrode is a source electrode, and the control electrode is a gate electrode.

【0021】図1は本発明の第1実施例の半導体スイッ
チの電極構造を説明する図であり、図1(a)は斜視
図、図1(b)は矢印A方向から見た側断面図となる。
またこの図において、パッケージケースおよび内部に充
填するゲル、エポキシ樹脂は省略し、内部回路のみを示
してある。
FIG. 1 is a view for explaining an electrode structure of a semiconductor switch according to a first embodiment of the present invention. FIG. 1 (a) is a perspective view, and FIG. 1 (b) is a side sectional view as seen from the direction of arrow A. Becomes
Also, in this figure, the package case and the gel and epoxy resin filling the inside are omitted, and only the internal circuit is shown.

【0022】先ず図(a)において、複数個の半導体チ
ップ2が、放熱板と兼用のドレイン電極3上に直接載置
され、さらにソース電極4、5とゲート電極6が前記半
導体チップ2を挟むような位置に載置される。前記ソー
ス電極4、5とゲート電極6はドレイン電極3との間に
絶縁用樹脂7を狭着して電気的に絶縁した上で載置さ
れ、また各電極は細いボンディングワイヤ8を複数本並
列で半導体チップ2と接続される構成となる。
First, in FIG. 1A, a plurality of semiconductor chips 2 are directly mounted on a drain electrode 3 also serving as a heat sink, and further, source electrodes 4, 5 and a gate electrode 6 sandwich the semiconductor chip 2. It is placed in such a position. The source electrodes 4 and 5 and the gate electrode 6 are placed after being electrically insulated by tightly attaching an insulating resin 7 between the drain electrode 3 and each electrode having a plurality of thin bonding wires 8 arranged in parallel. Thus, the configuration is such that the semiconductor chip 2 is connected.

【0023】ここで従来の半導体スイッチとの相違点
は、図に示すようにソース電極4が側部より上方に向け
て広く、大きく形成されていることであり、また図に示
す状態から矢印Bの内側の方向に直角に曲げて、図
(b)に示す通りの「コ」の字型に形成されていること
にある。そして、ドレイン電極3およびソース電極4に
は図に示す位置に、外部端子が接続される端子孔9、1
0がそれぞれ穿設されており、ここから電流が入・出力
される構成となる。なお、ソース電極5はフローティン
グ用であり、メインのスイッチング電流は流れない。
Here, the difference from the conventional semiconductor switch is that the source electrode 4 is formed wider and larger upward from the side as shown in FIG. Is bent at a right angle to the inside direction of "." To form a "U" shape as shown in FIG. The drain electrode 3 and the source electrode 4 have terminal holes 9, 1, to which external terminals are connected, at positions shown in the figure.
0 are respectively formed, from which current is input and output. The source electrode 5 is used for floating, and no main switching current flows.

【0024】本発明による半導体スイッチ電極構造は、
このように構成することにより、以下に述べる作用効果
が生じることになる。先ず、ソース電極4を(本例にお
いて図に示すようなドレイン電極3基板のように)広く
大きく形成することで、電極中に流れる電流が空間的に
分散されることになり、従来の電流が集中して流れる細
い電極の場合と比較してインダクタンスの発生を低減す
ることが可能となる。一方、電極を広く大きく形成する
ことで内部回路全体のサイズが大きくなってしまうた
め、前述した通り断面上で「コ」の字型に形成して設置
することで内部回路全体をコンパクトにできる。しかし
この「コ」の字型に形成することによって同時に、該ソ
ース電極4の上天板部分とドレイン電極3基板が相互に
平行で近接した位置に配置されることになるため、相互
インダクタンスの作用によりお互いのインダクタンス
(磁気)を相殺する(打ち消し合う)といった電磁気的
効果が生じ、これを利用することでインダクタンスのよ
り一層の低減を図ることが可能となる。そしてこの相互
インダクタンスによる効果は、ソース電極4の上天板部
分とドレイン電極3基板の間隔ができるだけ小さく(で
きるだけ狭く)、また流れる電流の方向がお互いに逆向
きである場合に最も高い効果が期待できる。
According to the semiconductor switch electrode structure of the present invention,
With this configuration, the following operation and effect can be obtained. First, by forming the source electrode 4 to be wide and large (like the drain electrode 3 substrate as shown in the figure in this example), the current flowing in the electrode is spatially dispersed, and the conventional current is reduced. It is possible to reduce the occurrence of inductance as compared with the case of a thin electrode flowing in a concentrated manner. On the other hand, since the size of the entire internal circuit increases when the electrodes are formed to be large, the entire internal circuit can be made compact by forming and installing it in a U-shape on the cross section as described above. However, by forming this U-shape, at the same time, the upper top plate portion of the source electrode 4 and the substrate of the drain electrode 3 are arranged at positions parallel and close to each other. Electromagnetic effects such as canceling out (cancelling) each other's inductance (magnetism) occur, and by utilizing this, it is possible to further reduce the inductance. The effect due to the mutual inductance can be expected to be highest when the distance between the upper top plate of the source electrode 4 and the substrate of the drain electrode 3 is as small as possible (as small as possible), and the directions of flowing currents are opposite to each other. .

【0025】ここで図1(b)において、最初に外部か
らの電流がドレイン電極3中の端子孔9に入力され、矢
印Idの示す流路でドレイン電極3から半導体チップ2
へと流れ、一方矢印Isの示す流路でソース電極4から
ソース電極4中の端子孔10へと出力される。したがっ
て矢印Id,Isが示す両電流流路に関しては、お互い
流れる電流がほぼ逆方向に流れていることになり、よっ
て相互インダクタンスによる効果が一層発揮できる構成
となっている。
In FIG. 1B, an external current is first input to the terminal hole 9 in the drain electrode 3, and the semiconductor chip 2 is supplied from the drain electrode 3 through the flow path indicated by the arrow Id.
And is output from the source electrode 4 to the terminal hole 10 in the source electrode 4 through the flow path indicated by the arrow Is. Therefore, the currents flowing through the two current flow paths indicated by the arrows Id and Is are flowing in substantially opposite directions, so that the effect of the mutual inductance can be further exhibited.

【0026】以上によりドレイン電極3−ソース電極4
間の(電磁気的)接続が良くなり、スイッチングロス、
サージ電圧の発生を低減することが可能となる。図2は
本発明の第2実施例の半導体スイッチの電極構造を説明
する図であり、図2(a)は上面図、図2(b)は正面
図となる。またこの図においてもパッケージケースおよ
び内部に充填するゲル、エポキシ樹脂は省略し、内部回
路のみを示してある。
As described above, the drain electrode 3 and the source electrode 4
(Electromagnetic) connection between them is improved, switching loss,
Generation of a surge voltage can be reduced. 2A and 2B are views for explaining the electrode structure of a semiconductor switch according to a second embodiment of the present invention, wherein FIG. 2A is a top view and FIG. 2B is a front view. Also in this figure, the package case and the gel and epoxy resin filling the inside are omitted, and only the internal circuit is shown.

【0027】図2(a)、(b)に示すように、本例の
半導体スイッチ1は、前述の第1実施例の半導体スイッ
チを、正面より見た構成において左右対称の構造に作っ
た2つの半導体スイッチを左右に並べてドレイン電極3
が一体となるよう接続し、中央のゲート電極6とソース
電極5を1つにまとめて兼用とした構成となる。つま
り、、ゲート電極6とソース電極5の配置を除けば、ほ
ぼ左右対称の構成となる。なお、ソース電極5はフロー
ティング用であり、メインのスイッチング電流は流れな
い。
As shown in FIGS. 2A and 2B, the semiconductor switch 1 of the present embodiment is obtained by making the semiconductor switch of the first embodiment into a symmetrical structure when viewed from the front. Three semiconductor switches are arranged side by side and the drain electrode 3
Are connected so as to be integrated, and the central gate electrode 6 and the source electrode 5 are combined into one and shared. That is, except for the arrangement of the gate electrode 6 and the source electrode 5, the configuration is substantially symmetrical. The source electrode 5 is used for floating, and no main switching current flows.

【0028】このように個別に2つ並べるよりも1パッ
ケージ内に2つの回路を対称に並べる構造にすることで
左右対称となる電極間、本例においてはソース電極4と
4’間についても相互インダクタンスの効果が作用し、
半導体スイッチ1全体においてのインダクタンスの一層
の低減を可能とする。
By symmetrically arranging two circuits in one package rather than arranging two individually in this manner, the symmetrical arrangement between the electrodes, that is, between the source electrodes 4 and 4 ′ in this example, is not required. The effect of inductance works,
The inductance of the entire semiconductor switch 1 can be further reduced.

【0029】また、本発明の半導体スイッチの電極構造
において、ボンディングワイヤ8の形状を図に示した半
円形に限定せずに、例えば上辺を長くした台形等に形成
することでより効果的にインダクタンスを相殺する構成
も可能である。
In the electrode structure of the semiconductor switch of the present invention, the shape of the bonding wire 8 is not limited to the semicircular shape shown in FIG. A configuration that cancels out is also possible.

【0030】また前述の相互インダクタンス作用は各電
極の材質の選定によって一層効果的に作用させることも
可能である。尚、上述した半導体スイッチの電極構造
は、上記実施形態例のMOSFET構造に限定されるも
のではなく、他のバイポーラまたはサイリスタにも適用
が可能である。その場合前記主電流入力用電極がそれぞ
れコレクタ電極、アノード電極に、主電流出力用電極が
エミッタ電極、カソード電極に、制御電極がベース電
極、ゲート電極に対応する。
The mutual inductance function described above can be made to work more effectively by selecting the material of each electrode. Note that the electrode structure of the semiconductor switch described above is not limited to the MOSFET structure of the above embodiment, but can be applied to other bipolar or thyristor. In this case, the main current input electrode corresponds to the collector electrode and the anode electrode, the main current output electrode corresponds to the emitter electrode and the cathode electrode, and the control electrode corresponds to the base electrode and the gate electrode.

【0031】[0031]

【発明の効果】以上説明した通り、本発明の半導体スイ
ッチにおいてインダクタンスの発生を低減することが可
能となり、しいては前述したような半導体スイッチの作
動におけるターンオン時のサージ電圧、およびターンオ
フ時のスイッチングロスの低減が可能となる。さらにこ
れにより半導体スイッチ作動中における発熱や電力損失
の低減が可能となるためヒートシンクの小形化、スナバ
レス化、またはディレーティングを小さくできるための
半導体チップ数の削減が実現され、その結果半導体スイ
ッチの信頼性向上と共に製造コストの削減が可能とな
る。
As described above, it is possible to reduce the occurrence of inductance in the semiconductor switch of the present invention, and it is also possible to reduce the surge voltage at the time of turn-on and the switching at the time of turn-off in the operation of the semiconductor switch as described above. Loss can be reduced. Furthermore, this makes it possible to reduce heat generation and power loss during operation of the semiconductor switch, thereby reducing the size of the heat sink, reducing the need for snubbers, and reducing the number of semiconductor chips required to reduce derating. The manufacturing cost can be reduced along with the improvement of the performance.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例の半導体スイッチの電極構
造を説明する図であり、(a)は斜視図、(b)は矢印
A方向から見た正面図となる。
FIGS. 1A and 1B are diagrams illustrating an electrode structure of a semiconductor switch according to a first embodiment of the present invention, wherein FIG. 1A is a perspective view and FIG.

【図2】本発明の第2実施例の半導体スイッチの電極構
造を説明する図であり、(a)は上面図、(b)は正面
図である。
FIGS. 2A and 2B are diagrams illustrating an electrode structure of a semiconductor switch according to a second embodiment of the present invention, wherein FIG. 2A is a top view and FIG.

【図3】従来の半導体スイッチの電極構造の具体的な一
例を示すものである。
FIG. 3 shows a specific example of an electrode structure of a conventional semiconductor switch.

【符号の説明】[Explanation of symbols]

1 半導体スイッチ 2 半導体チップ 3 ドレイン電極 4、4’ ソース電極 5 ソース電極(フローティング用) 6 ゲート電極 7 絶縁用樹脂 8 ボンディングワイヤ 9 ドレイン電極用端子孔 10、10’ ソース電極用端子孔 DESCRIPTION OF SYMBOLS 1 Semiconductor switch 2 Semiconductor chip 3 Drain electrode 4, 4 'source electrode 5 Source electrode (for floating) 6 Gate electrode 7 Insulating resin 8 Bonding wire 9 Drain electrode terminal hole 10, 10' Source electrode terminal hole

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 制御電極に供給される制御信号に従って
主電流入力用電極から半導体チップを介して主電流出力
用電極に電流を供給する半導体スイッチの電極構造にお
いて、電流の集中によるインダクタンスの発生を低減で
きる程度に、前記主電流入力用電極および前記主電流出
力用電極の両方の電極を広く大きく形成したことを特徴
とする半導体スイッチの電極構造。
In an electrode structure of a semiconductor switch for supplying a current from a main current input electrode to a main current output electrode via a semiconductor chip in accordance with a control signal supplied to a control electrode, generation of inductance due to concentration of the current is reduced. An electrode structure for a semiconductor switch, wherein both the main current input electrode and the main current output electrode are formed to be wide and large to the extent that they can be reduced.
【請求項2】 前記主電流入力用電極と前記主電流出力
用電極が平行に近接するよう配置することを特徴とする
請求項1記載の半導体スイッチの電極構造。
2. The electrode structure of a semiconductor switch according to claim 1, wherein said main current input electrode and said main current output electrode are arranged in parallel and close to each other.
【請求項3】 前記主電流出力用電極に流れる電流が、
前記主電流入力用電極に流れる電流と空間的に平行の配
置にあり、かつ逆方向に流れるよう両電極が配置される
ことを特徴とする請求項1または2記載の半導体スイッ
チの電極構造。
3. A current flowing through the main current output electrode,
3. The electrode structure of a semiconductor switch according to claim 1, wherein both electrodes are arranged so as to be spatially parallel to a current flowing through the main current input electrode and to flow in opposite directions.
【請求項4】 前記半導体チップが、前記主電流入力用
電極または前記主電流出力用電極のどちらか一方と兼用
であり広く大きく形成された基板上に接続されることを
特徴とする請求項1ないし3のいずれか記載の半導体ス
イッチの電極構造。
4. The semiconductor chip according to claim 1, wherein said semiconductor chip is used on one of said main current input electrode and said main current output electrode, and is connected to a large substrate which is widely formed. 4. The electrode structure of a semiconductor switch according to any one of items 3 to 3.
【請求項5】 前記半導体スイッチが、一つのパッケー
ジ内に複数個組み込まれ、隣り合う2つの半導体スイッ
チ中にそれぞれ備える主電流入力用電極同士および主電
流出力用電極同士が、該2つの半導体スイッチ間に設定
した境界線を対称中心線として線対称構造となる構成で
あることを特徴とする請求項1ないし3のいずれか記載
の半導体スイッチの電極構造。
5. A plurality of the semiconductor switches are incorporated in one package, and main current input electrodes and main current output electrodes included in two adjacent semiconductor switches are respectively connected to the two semiconductor switches. The electrode structure of a semiconductor switch according to any one of claims 1 to 3, wherein the electrode structure has a line-symmetrical structure with a boundary line set between them as a center line of symmetry.
JP33886497A 1997-12-09 1997-12-09 Electrode structure for semiconductor switch Pending JPH11177021A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33886497A JPH11177021A (en) 1997-12-09 1997-12-09 Electrode structure for semiconductor switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33886497A JPH11177021A (en) 1997-12-09 1997-12-09 Electrode structure for semiconductor switch

Publications (1)

Publication Number Publication Date
JPH11177021A true JPH11177021A (en) 1999-07-02

Family

ID=18322124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33886497A Pending JPH11177021A (en) 1997-12-09 1997-12-09 Electrode structure for semiconductor switch

Country Status (1)

Country Link
JP (1) JPH11177021A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6445068B1 (en) 1999-02-05 2002-09-03 Kabushiki Kaisha Toyoda Jidoshokki Seisakusho Semiconductor module
EP0971412A3 (en) * 1998-07-10 2003-11-26 Kabushiki Kaisha Toyota Jidoshokki Power Semiconductor with Attachable Protection Circuit
JP2006210500A (en) * 2005-01-26 2006-08-10 Nippon Inter Electronics Corp Semiconductor device for electric power
JP2006313821A (en) * 2005-05-09 2006-11-16 Toyota Industries Corp Semiconductor device
CN105140219A (en) * 2015-09-18 2015-12-09 中国工程物理研究院电子工程研究所 Two-way withstand voltage silicon carbide solid-state switch
US11398450B2 (en) 2020-03-06 2022-07-26 Fuji Electric Co., Ltd. Semiconductor module

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0971412A3 (en) * 1998-07-10 2003-11-26 Kabushiki Kaisha Toyota Jidoshokki Power Semiconductor with Attachable Protection Circuit
US6445068B1 (en) 1999-02-05 2002-09-03 Kabushiki Kaisha Toyoda Jidoshokki Seisakusho Semiconductor module
JP2006210500A (en) * 2005-01-26 2006-08-10 Nippon Inter Electronics Corp Semiconductor device for electric power
JP4660214B2 (en) * 2005-01-26 2011-03-30 日本インター株式会社 Power semiconductor device
JP2006313821A (en) * 2005-05-09 2006-11-16 Toyota Industries Corp Semiconductor device
JP4572736B2 (en) * 2005-05-09 2010-11-04 株式会社豊田自動織機 Semiconductor device
CN105140219A (en) * 2015-09-18 2015-12-09 中国工程物理研究院电子工程研究所 Two-way withstand voltage silicon carbide solid-state switch
US11398450B2 (en) 2020-03-06 2022-07-26 Fuji Electric Co., Ltd. Semiconductor module

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