JP2005277014A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005277014A
JP2005277014A JP2004086699A JP2004086699A JP2005277014A JP 2005277014 A JP2005277014 A JP 2005277014A JP 2004086699 A JP2004086699 A JP 2004086699A JP 2004086699 A JP2004086699 A JP 2004086699A JP 2005277014 A JP2005277014 A JP 2005277014A
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support plate
semiconductor element
semiconductor
transistor
fixed
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JP4061551B2 (en
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Akio Iwabuchi
昭夫 岩渕
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13033—TRIAC - Triode for Alternating Current - A bidirectional switching device containing two thyristor structures with common gate contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

<P>PROBLEM TO BE SOLVED: To laminate semiconductor elements and thereby to miniaturize a semiconductor device, and to reduce the electrical resistance, as well as power loss due to a fine lead line so as to cause the semiconductor device to make it operate with a large current. <P>SOLUTION: The semiconductor device comprises a first support board (11), a first semiconductor element (1) secured on the first support board (11), a second support board (12) secured on the first semiconductor element (1), and a second semiconductor element (2) secured on the second support (12). Each of the first support board (11) and the second support board (12) is formed of a conductive material, and has lead terminals (21a, 21b, 21c, 22a, 22b) electrically connected to the first semiconductor element (1) and the second semiconductor element (2). Since the second support board (12) satisfactorily acts as a heat dissipating board for the second semiconductor element (2), and as an electrode terminal for the semiconductor element, wirings can be simplified. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、複数の電力用半導体素子を高さ方向に積層して形成される小型化半導体装置に関する。   The present invention relates to a miniaturized semiconductor device formed by stacking a plurality of power semiconductor elements in the height direction.

図３に示すＨ型ブリッジ（フルブリッジ）回路(10)を単一の半導体装置で構成する場合、Ｈ型ブリッジ回路(10)は、ハイサイド側の第１のトランジスタ(1)及び第３のトランジスタ(3)と、ローサイド側の第２のトランジスタ(2)及び第４のトランジスタ(4)とを備える。第１のトランジスタ(1)のソース端子と第２のトランジスタ(2)のドレイン端子との接続点(A1)と、第３のトランジスタ(3)のソース端子と第４のトランジスタ(4)のドレイン端子との接続点(A2)との間には負荷(6)が接続される。   When the H-type bridge (full bridge) circuit (10) shown in FIG. 3 is configured by a single semiconductor device, the H-type bridge circuit (10) includes a first transistor (1) and a third transistor on the high side. A transistor (3) and a second transistor (2) and a fourth transistor (4) on the low side are provided. The connection point (A1) between the source terminal of the first transistor (1) and the drain terminal of the second transistor (2), the source terminal of the third transistor (3), and the drain of the fourth transistor (4) A load (6) is connected between the connection point (A2) and the terminal.

Ｈ型ブリッジ回路(10)を作動する際に、第１のトランジスタ(1)及び第４のトランジスタ(4)と、第２のトランジスタ(2)及び第３のトランジスタ(3)とを交互にオン・オフ動作させて、スイッチング作動させることにより、接続点(A1)と(A2)との間に交互に逆方向の電流を流して、負荷(6)を作動させることができる。このようにスイッチング動作を行なえば、直流電圧源を使用し、接続点(A1)と(A2)との間に接続された冷陰極蛍光放電管等を点灯させることができる。   When the H-type bridge circuit (10) is operated, the first transistor (1) and the fourth transistor (4), and the second transistor (2) and the third transistor (3) are alternately turned on. By performing the switching operation by turning off the load, the load (6) can be operated by causing a reverse current to flow alternately between the connection points (A1) and (A2). If the switching operation is performed in this manner, a cold cathode fluorescent discharge tube or the like connected between the connection points (A1) and (A2) can be lit using a DC voltage source.

図３に示すＨ型ブリッジ回路(10)を単一の半導体装置に構築するとき、４つのトランジスタ(1〜4)とその制御用ＩＣを支持板（図示せず）に並べて配置するため、半導体装置の平面サイズが増大する欠点がある。特に、リ−ド端子を支持板の一方の側面側にのみ配置した構造の半導体装置では、平面サイズが著しく増大する。下記特許文献１は、非導電性接着剤を介して２つの半導体素子を積層した半導体装置を示す。特許文献１に開示される２つの半導体素子の積層技術を適用して、半導体装置の平面サイズを縮小することができる。しかしながら、冷陰極蛍光放電管の点灯回路等を構成するＨ型ブリッジ回路では、半導体素子に比較的大きな電流を流す必要があり、一般的にパワースイッチング素子が使用される。このようなパワースイッチング素子を使用するＨ型ブリッジ回路では、単に半導体素子を積層しても、動作時に半導体素子の発熱が集中して、良好な放熱特性が得られず、半導体素子の電気的特性が劣化するおそれがあった。これに対し、下記特許文献２は、支持板上に２つの半導体素子をずらして積層し、上段の半導体素子と支持板との間に金属製のスペーサを配置した半導体装置を示す。金属製のスペーサにより半導体装置の動作時に生じる半導体素子の発熱を低減できる。   When the H-type bridge circuit (10) shown in FIG. 3 is constructed in a single semiconductor device, the four transistors (1 to 4) and their control ICs are arranged side by side on a support plate (not shown). There is a disadvantage that the planar size of the device increases. In particular, in a semiconductor device having a structure in which lead terminals are arranged only on one side surface of the support plate, the planar size is remarkably increased. Patent Document 1 below shows a semiconductor device in which two semiconductor elements are stacked with a non-conductive adhesive. By applying the stacking technique of two semiconductor elements disclosed in Patent Document 1, the planar size of the semiconductor device can be reduced. However, in an H-type bridge circuit that constitutes a lighting circuit of a cold cathode fluorescent discharge tube or the like, a relatively large current needs to flow through a semiconductor element, and a power switching element is generally used. In an H-type bridge circuit using such a power switching element, even if semiconductor elements are simply stacked, heat generation of the semiconductor elements is concentrated during operation, and good heat dissipation characteristics cannot be obtained. There was a risk of deterioration. On the other hand, Patent Document 2 below shows a semiconductor device in which two semiconductor elements are stacked on a support plate in a shifted manner, and a metal spacer is disposed between the upper semiconductor element and the support plate. The metal spacer can reduce heat generation of the semiconductor element that occurs during operation of the semiconductor device.

特開昭５５−１１１１５１号公報JP-A-55-1111151 特開２００２−３７３９６８公報JP 2002-373968 A

しかしながら、特許文献２の半導体装置においても上段の半導体素子については十分な放熱効果が得られなかった。また、特許文献２の半導体装置では、外部端子に接続するリード端子を支持板の裏面に別途設け、リード細線により半導体素子の各電極を最下段の支持板に接続して、半導体素子の各電極と外部端子とを電気的に接続するため、リード細線による配線が増加して配線が複雑となり配線設計の自由度が低かった。また、特許文献２の半導体装置によってＨ型ブリッジ回路を構成する場合、積層された２組の半導体素子（スイッチング素子）と制御用ＩＣを必要となるが、制御用ＩＣと半導体素子とを接続するリード細線の配線距離が長くなる問題があった。リ−ド細線の接続距離が増大すると、リ−ド細線の抵抗成分による電力損失の増大及びインダクタンス成分による高周波動作特性の低下を招来する。   However, even in the semiconductor device of Patent Document 2, a sufficient heat dissipation effect was not obtained for the upper semiconductor element. Further, in the semiconductor device of Patent Document 2, a lead terminal connected to the external terminal is separately provided on the back surface of the support plate, each electrode of the semiconductor element is connected to the lowermost support plate by a lead thin wire, and each electrode of the semiconductor element is connected. Since the wires are electrically connected to the external terminals, the number of wires by the thin lead wires is increased, the wires become complicated, and the degree of freedom in wiring design is low. Further, when an H-type bridge circuit is configured by the semiconductor device of Patent Document 2, two sets of stacked semiconductor elements (switching elements) and a control IC are required, but the control IC and the semiconductor element are connected. There was a problem that the wiring distance of the lead fine wire became long. When the connection distance of the lead thin wire increases, an increase in power loss due to the resistance component of the lead thin wire and a decrease in high-frequency operation characteristics due to the inductance component are caused.

そこで、本発明は、複数の半導体素子を小さい面積に積層し且つ良好な放熱特性で作動できる半導体装置を提供することを目的とする。また、本発明は、リード細線による配線を短縮且つ簡素化して、電気抵抗及び電力損失を低減できる半導体装置を提供することを目的とする。   Therefore, an object of the present invention is to provide a semiconductor device in which a plurality of semiconductor elements are stacked in a small area and can operate with good heat dissipation characteristics. Another object of the present invention is to provide a semiconductor device capable of reducing electrical resistance and power loss by shortening and simplifying the wiring of the lead thin wires.

本発明による半導体装置は、導電性の材料により形成された第１の支持板(11)と、第１の支持板(11)上に一方の主面が固着された第１の半導体素子(1)と、導電性の材料により形成され且つ第１の半導体素子(1)の他方の主面に固着された第２の支持板(12)と、第２の支持板(12)上に一方の主面が固着された第２の半導体素子(2)とを備える。第１の支持板(11)及び第２の支持板(12)の各々は、第１の半導体素子(1)及び第２の半導体素子(2)に電気的に接続されたリード端子(21a,21b,21c,22a,22b)を有する。第１の支持板(11)上に第１の半導体素子(1)を固着し、第１の半導体素子(1)の上に第２の支持板(12)を固着し、第２の支持板(12)上に第２の半導体素子(2)を立体状に積層するので、半導体装置の平面サイズを小さくできる。また、第２の支持板(12)が、第２の半導体素子(2)の放熱板として良好に機能するため、放熱特性が向上する。更に、第１の支持板(11)及び第２の支持板(12)の各々は、第１の半導体素子(1)及び第２の半導体素子(2)に電気的に接続されたリード端子(21a,21b,21c,22a,22b)を有するので、配線を簡素化できる。   The semiconductor device according to the present invention includes a first support plate (11) formed of a conductive material, and a first semiconductor element (1) whose one main surface is fixed on the first support plate (11). ), A second support plate (12) formed of a conductive material and fixed to the other main surface of the first semiconductor element (1), and one of the second support plate (12) on the second support plate (12). And a second semiconductor element (2) to which the main surface is fixed. Each of the first support plate (11) and the second support plate (12) is connected to lead terminals (21a, 21a, 21) electrically connected to the first semiconductor element (1) and the second semiconductor element (2). 21b, 21c, 22a, 22b). The first semiconductor element (1) is fixed on the first support plate (11), the second support plate (12) is fixed on the first semiconductor element (1), and the second support plate (12) Since the second semiconductor element (2) is three-dimensionally stacked on the semiconductor device, the planar size of the semiconductor device can be reduced. Further, since the second support plate (12) functions well as a heat radiating plate of the second semiconductor element (2), the heat radiating characteristics are improved. Further, each of the first support plate (11) and the second support plate (12) is connected to a lead terminal (1) electrically connected to the first semiconductor element (1) and the second semiconductor element (2). 21a, 21b, 21c, 22a, 22b), the wiring can be simplified.

第２の支持板(12)は、第２の支持板(12)に連結され且つ第１の半導体素子(1)と第２の半導体素子(2)に電気的に接続されたリード端子(22b)を有するのが望ましい。第１の半導体素子(1)と第２の半導体素子(2)として第１の半導体スイッチング素子(1)及び第２の半導体スイッチング素子(2)を交互にオン・オフ制御すると、第１の半導体素子(1)と第２の半導体素子(2)の発熱を第１の支持板(11)及び第２の支持板(12)を通じて良好に放熱させることができる。第２の半導体素子(2)の他方の主面に第３の支持板(13)を介して制御素子(5)を配置し、第１の半導体素子(1)及び第２の半導体素子(2)に開放領域(31,32)を形成して、制御素子(5)と第１の半導体素子(1)及び第２の半導体素子(2)の開放領域(31,32)とをリード細線(7)により電気的に接続すれば、リード細線(7)の接続距離が短くなり、電力損失の低減、高周波特性の向上が図られる。また、第１の半導体素子(1)と第２の半導体素子(2)とを第２の支持板(12)を介して電気的に接続すれば、第２の支持板(12)が第１の半導体素子(1)と第２の半導体素子(2)との接続導体となり、更に電力損失の低減、高周波特性を向上できる。   The second support plate (12) is connected to the second support plate (12) and is electrically connected to the first semiconductor element (1) and the second semiconductor element (2) (22b ) Is desirable. When the first semiconductor switching element (1) and the second semiconductor switching element (2) are alternately turned on / off as the first semiconductor element (1) and the second semiconductor element (2), the first semiconductor element Heat generated by the element (1) and the second semiconductor element (2) can be radiated well through the first support plate (11) and the second support plate (12). A control element (5) is arranged on the other main surface of the second semiconductor element (2) via a third support plate (13), and the first semiconductor element (1) and the second semiconductor element (2 ) In the open regions (31, 32), and the control element (5) and the open regions (31, 32) of the first semiconductor element (1) and the second semiconductor element (2) are connected to the lead wires ( If the electrical connection is performed according to 7), the connection distance of the lead wire (7) is shortened, and the power loss can be reduced and the high frequency characteristics can be improved. Further, if the first semiconductor element (1) and the second semiconductor element (2) are electrically connected via the second support plate (12), the second support plate (12) becomes the first support plate (12). As a connecting conductor between the semiconductor element (1) and the second semiconductor element (2), power loss can be reduced and high-frequency characteristics can be improved.

また、本発明による半導体装置は、導電性の材料により形成された第１の支持板(11)と、第１の支持板(11)上に各一方の主面が固着された第１の半導体素子(1)及び第３の半導体素子(3)と、導電性の材料により形成され且つ第１の半導体素子(1)の他方の主面に固着された第２の支持板(12)と、導電性の材料により形成され且つ第３の半導体素子(3)の他方の主面に固着された第４の支持板(14)と、第２の支持板(12)上に一方の主面が固着された第２の半導体素子(2)と、第４の支持板(14)上に一方の主面が固着された第４の半導体素子(4)とを備える。Ｈ型ブリッジ回路を構成する第１の半導体素子(1)及び第４の半導体素子(4)と第３の半導体素子(3)及び第２の半導体素子(2)とが交互にスイッチング動作する。このため、Ｈ型ブリッジ回路を放熱特性に優れ且つ小型化した単一の半導体装置で形成できる。第１の半導体素子(1)、第２の半導体素子(2)、第３の半導体素子(3)及び第４の半導体素子(4)に開放領域(31,32,33,34)を設け、制御素子(5)と第１の半導体素子(1)、第２の半導体素子(2)、第３の半導体素子(3)及び第４の半導体素子(4)の開放領域(31,32,33,34)とをリード細線(7)により電気的に接続するのが望ましい。これにより、リード細線(7)の接続距離が短くなり、電力損失が低減し且つ高周波特性が向上したＨ型ブリッジ回路半導体装置が得られる。   The semiconductor device according to the present invention includes a first support plate (11) formed of a conductive material, and a first semiconductor in which one main surface is fixed on the first support plate (11). An element (1) and a third semiconductor element (3); a second support plate (12) formed of a conductive material and fixed to the other main surface of the first semiconductor element (1); A fourth support plate (14) formed of a conductive material and fixed to the other main surface of the third semiconductor element (3), and one main surface on the second support plate (12) A second semiconductor element (2) fixed and a fourth semiconductor element (4) having one main surface fixed on the fourth support plate (14) are provided. The first semiconductor element (1) and the fourth semiconductor element (4), the third semiconductor element (3), and the second semiconductor element (2) constituting the H-type bridge circuit perform switching operations alternately. For this reason, the H-type bridge circuit can be formed with a single semiconductor device having excellent heat dissipation characteristics and a reduced size. Open regions (31, 32, 33, 34) are provided in the first semiconductor element (1), the second semiconductor element (2), the third semiconductor element (3), and the fourth semiconductor element (4), Open regions (31, 32, 33) of the control element (5), the first semiconductor element (1), the second semiconductor element (2), the third semiconductor element (3), and the fourth semiconductor element (4) , 34) is preferably electrically connected to the thin lead wire (7). As a result, the connection distance of the lead wire (7) is shortened, and an H-type bridge circuit semiconductor device with reduced power loss and improved high-frequency characteristics can be obtained.

本発明では、優れた高周波特性と低電力損失とを有する小型の半導体装置を得ることができる。   In the present invention, a small semiconductor device having excellent high-frequency characteristics and low power loss can be obtained.

以下、図３に示すＨ型ブリッジ回路を構成する本発明による半導体装置の実施の形態を図１及び図２について説明する。図１及び図２では、図３に示す部分と同一の箇所には、同一の符号を付する。   A semiconductor device according to an embodiment of the present invention constituting the H-type bridge circuit shown in FIG. 3 will be described below with reference to FIGS. 1 and 2, the same parts as those shown in FIG. 3 are denoted by the same reference numerals.

半導体装置は、図１及び図２に示すように、第１の支持板(11)と、第１の支持板(11)上に固着された第１のトランジスタ(1)と、第１のトランジスタ(1)上に固着された第２の支持板(12)と、第２の支持板(12)上に固着された第２のトランジスタ(2)と、第１のトランジスタ(1)と一定の間隔をもって並行に第１の支持板(11)上に固着された第３のトランジスタと、第３のトランジスタ(3)上に固着された第４の支持板(14)と、第４の支持板(14)上に固着された第４のトランジスタ(4)と、第２のトランジスタ(2)及び第４のトランジスタ(4)上に固着された第３の支持板(13)と、第３の支持板(13)上に固着された制御素子としてのコントロールＩＣ(5)とを備える。本発明による半導体装置を具体的に説明する本実施の形態では、第１の半導体素子、第２の半導体素子、第３の半導体素子及び第４の半導体素子をそれぞれ第１のトランジスタ、第２のトランジスタ、第３のトランジスタ及び第４のトランジスタとして説明するが、これらは、それぞれバイポーラトランジスタ、電界効果トランジスタ(ＭＯＳ、ＩＧＢＴ)、サイリスタ、トライアック等の半導体素子により構成することができる。   As shown in FIGS. 1 and 2, the semiconductor device includes a first support plate (11), a first transistor (1) fixed on the first support plate (11), and a first transistor. (1) The second support plate (12) fixed on the second support plate (12), the second transistor (2) fixed on the second support plate (12), and the first transistor (1) are fixed. A third transistor fixed on the first support plate (11) in parallel with an interval, a fourth support plate (14) fixed on the third transistor (3), and a fourth support plate (14) a fourth transistor (4) fixed on top, a second transistor (2) and a third support plate (13) fixed on the fourth transistor (4); And a control IC (5) as a control element fixed on the support plate (13). In this embodiment mode for specifically describing a semiconductor device according to the present invention, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element are respectively referred to as a first transistor and a second semiconductor element. Although described as a transistor, a third transistor, and a fourth transistor, these can be constituted by semiconductor elements such as a bipolar transistor, a field effect transistor (MOS, IGBT), a thyristor, and a triac, respectively.

各トランジスタ(1,2,3,4)は、各支持板(11,12,13,14)により狭持されて配置される。第１の支持板(11)、第２の支持板(12)、第３の支持板(13)及び第４の支持板(14)は、銅、アルミニウム又はこれらの合金等の比較的放熱性が高い導電性の材料により板状に形成され、夫々リード端子(21a,21b,21c,22a,22b,23a,23b,23c,24a,24b)を有する。第２の支持板(12)及び第４の支持板(14)は、第１の支持板(11)と比較して小さい面積の上面及び下面を有し、第３の支持板(13)は、第２の支持板(12)及び第４の支持板(14)と比較して大きく且つ第１の支持板(11)と比較して小さい面積の上面及び下面を有する。   Each transistor (1, 2, 3, 4) is sandwiched and arranged by each support plate (11, 12, 13, 14). The first support plate (11), the second support plate (12), the third support plate (13), and the fourth support plate (14) are relatively heat radiating, such as copper, aluminum, or alloys thereof. Are formed in a plate shape from a highly conductive material, and have lead terminals (21a, 21b, 21c, 22a, 22b, 23a, 23b, 23c, 24a, 24b), respectively. The second support plate (12) and the fourth support plate (14) have an upper surface and a lower surface having a smaller area than the first support plate (11), and the third support plate (13) The upper and lower surfaces are larger than the second support plate (12) and the fourth support plate (14) and have a smaller area than the first support plate (11).

制御素子(5)は、半導体集積回路により構成され、第１のトランジスタ(1)、第２のトランジスタ(2)、第３のトランジスタ(3)及び第４のトランジスタ(4)の各ベースに制御信号を付与して、各トランジスタをオン・オフ制御する。本実施の形態では、第１のトランジスタ(1)及び第２のトランジスタ(2)と第３のトランジスタ(3)及び第４のトランジスタ(4)とは、Ｈ型ブリッジ回路を構成し、制御素子(5)は、第１のトランジスタ(1)及び第４のトランジスタ(4)と第３のトランジスタ(3)及び第２のトランジスタ(2)とを交互にスイッチング動作させるので、第１のトランジスタ(1)〜第４のトランジスタ(4)の同時発生熱量を抑制することができる。第１のトランジスタ(1)〜第４のトランジスタ(4)は、図３に示すＨ型ブリッジ回路(10)の４つのパワートランジスタを構成する例えばＮｃｈ−ＭＯＳＦＥＴ等のトランジスタである。   The control element (5) is constituted by a semiconductor integrated circuit, and is controlled to each base of the first transistor (1), the second transistor (2), the third transistor (3), and the fourth transistor (4). A signal is applied to control on / off of each transistor. In the present embodiment, the first transistor (1) and the second transistor (2), the third transistor (3) and the fourth transistor (4) constitute an H-type bridge circuit, and the control element (5) causes the first transistor (1) and the fourth transistor (4) and the third transistor (3) and the second transistor (2) to be switched alternately, so that the first transistor ( The amount of heat generated simultaneously in 1) to the fourth transistor (4) can be suppressed. The first transistor (1) to the fourth transistor (4) are transistors such as Nch-MOSFETs that constitute the four power transistors of the H-type bridge circuit (10) shown in FIG.

図２に示すように、第１のトランジスタ(1)は、一方の主面のドレイン端子が第１の支持板(11)上に固着され、他方の主面のソース端子に第２の支持板(12)の下面が固着される。第２のトランジスタ(2)は、一方の主面のドレイン端子が第２の支持板(12)上に固着され、他方の主面のソース端子に第３の支持板(13)の下面が固着される。同様に、第３のトランジスタ(3)は、一方の主面のドレイン端子が第１の支持板(11)上に固着され、他方の主面のソース端子に第４の支持板(14)の下面が固着される。第４のトランジスタ(4)は、一方の主面のドレイン端子が第４の支持板(14)上に固着され、他方の主面のソース端子に第３の支持板(13)の下面が固着される。制御素子(5)は、一方の主面が第３の支持板(13)上に固着されて最上部に配置される。各トランジスタ(1,2,3,4)と支持板(11,12,13,14)とは、半田や導電性ペ−ストから成る導電性接着剤(15)により固着され且つ電気的に接続される。これに対し、制御素子(5)は、絶縁性接着剤(18)により第３の支持板(13)上に機械的に固着され且つ電気的に分離される。なお、第３の支持板(13)は、制御素子(5)のグランド電極とすることができる。   As shown in FIG. 2, the first transistor (1) has a drain terminal on one main surface fixed on the first support plate (11), and a second support plate on the source terminal on the other main surface. The lower surface of (12) is fixed. In the second transistor (2), the drain terminal on one main surface is fixed on the second support plate (12), and the lower surface of the third support plate (13) is fixed on the source terminal on the other main surface. Is done. Similarly, in the third transistor (3), the drain terminal on one main surface is fixed on the first support plate (11), and the source terminal on the other main surface is connected to the fourth support plate (14). The lower surface is fixed. In the fourth transistor (4), the drain terminal on one main surface is fixed on the fourth support plate (14), and the lower surface of the third support plate (13) is fixed on the source terminal on the other main surface. Is done. One main surface of the control element (5) is fixed on the third support plate (13) and arranged at the top. Each transistor (1,2,3,4) and support plate (11,12,13,14) are fixed and electrically connected by a conductive adhesive (15) made of solder or conductive paste. Is done. On the other hand, the control element (5) is mechanically fixed and electrically separated on the third support plate (13) by an insulating adhesive (18). The third support plate (13) can be a ground electrode of the control element (5).

支持板(11,12,13,14)の下面には、下面から突起した接続部(16)が設けられる。接続部(16)により、導電性接着剤(15)が各トランジスタ(1,2,3,4)の主面に必要以上に広がることが防止される。各トランジスタ(1,2,3,4)を立体状に積層するので、支持板(11,12,13,14)に占める各トランジスタ(1,2,3,4)の面積を減少し且つ集積度を向上して半導体装置を小型化できる。Ｈ型ブリッジ回路を構成する本実施の形態の半導体装置では、半導体素子を平面に並べる従来の半導体装置と比較して三分の一程度にパッケージ面積を縮小でき、大幅な小型化が可能である。   A connection portion (16) protruding from the lower surface is provided on the lower surface of the support plate (11, 12, 13, 14). The connecting portion (16) prevents the conductive adhesive (15) from spreading more than necessary on the main surface of each transistor (1, 2, 3, 4). Since each transistor (1,2,3,4) is stacked in three dimensions, the area of each transistor (1,2,3,4) occupying the support plate (11,12,13,14) is reduced and integrated. The degree of improvement can be improved and the semiconductor device can be downsized. In the semiconductor device according to the present embodiment constituting the H-type bridge circuit, the package area can be reduced by about one third as compared with the conventional semiconductor device in which the semiconductor elements are arranged in a plane, and the size can be greatly reduced. .

図１に示すように、第１の支持板(11)は、第１の支持板(11)と一体に且つ第１のトランジスタ(1)に近接して形成された１本のリード端子(21b)と、第１の支持板(11)と離間して且つ第１のトランジスタ(1)と第３のトランジスタ(3)とに夫々近接して形成された２本のリード端子(21a,21c)とを備える。第２の支持板(12)は、第２の支持板(12)と一体に形成された１本のリード端子(22b)と、第２の支持板(12)と離間して形成された１本のリード端子(22a)とを備える。同様に、第４の支持板(14)は、第４の支持板(14)と一体に形成された１本のリード端子(24b)と、第４の支持板(14)と離間して形成された１本のリード端子(24a)とを備える。第３の支持板(13)は、第３の支持板(13)と一体に形成された１本のリード端子(23b)と、第３の支持板(13)と離間して且つ第１のトランジスタ(1)及び第２のトランジスタ(2)と第３のトランジスタ(3)及び第４のトランジスタ(4)とに夫々近接して形成された２本のリード端子(23a,23c)とを備える。各リード端子(21a,21b,21c,22a,22b,23a,23b,23c,24a,24b)は、各支持板(11,12,13,14)から同方向に延伸して形成される。   As shown in FIG. 1, the first support plate (11) is formed of one lead terminal (21b) formed integrally with the first support plate (11) and close to the first transistor (1). ) And two lead terminals (21a, 21c) formed apart from the first support plate (11) and close to the first transistor (1) and the third transistor (3), respectively. With. The second support plate (12) is formed as one lead terminal (22b) formed integrally with the second support plate (12) and spaced apart from the second support plate (12). Lead terminals (22a). Similarly, the fourth support plate (14) is formed so as to be separated from one lead terminal (24b) formed integrally with the fourth support plate (14) and the fourth support plate (14). And a single lead terminal (24a). The third support plate (13) is separated from the one lead terminal (23b) formed integrally with the third support plate (13), the third support plate (13), and the first support plate (13). Two lead terminals (23a, 23c) formed in close proximity to the transistor (1) and the second transistor (2) and the third transistor (3) and the fourth transistor (4), respectively. . Each lead terminal (21a, 21b, 21c, 22a, 22b, 23a, 23b, 23c, 24a, 24b) is formed by extending in the same direction from each support plate (11, 12, 13, 14).

第１のトランジスタ(1)、第２のトランジスタ(2)、第３のトランジスタ(3)及び第４のトランジスタ(4)は、第２の支持板(12)、第３の支持板(13)又は第４の支持板(14)が固着される他方の主面に、支持板(12,13,14)が固着されない開放領域(31,32,33,34)を夫々有し、制御素子(5)と各トランジスタ(1,2,3,4)の開放領域(31,32,33,34)とは、金又はアルミニウム等から成るリード細線(7)によって電気的に接続される。開放領域(31,32,33,34)によりリード細線(7)を各トランジスタ(1,2,3,4)の他方の主面に接続できるので、リード細線(7)の配線が簡素化し、設計自由度が向上する。また、リード細線(7)の長さを短縮できるので、電力損失の低減、高周波特性の向上が図られる。また、第２の支持板(12)及び第４の支持板(14)が、それぞれ第１のトランジスタ(1)と第２のトランジスタ(2)との接続体、第３のトランジスタ(3)と第４のトランジスタ(4)との接続体として機能するので、半導体素子間をリード細線(7)と比較して広い面積で接続可能となり、電流経路のインピーダンス及びインダクタンスを更に良好に低減できる。   The first transistor (1), the second transistor (2), the third transistor (3) and the fourth transistor (4) are composed of a second support plate (12) and a third support plate (13). Alternatively, the other main surface to which the fourth support plate (14) is fixed has open regions (31, 32, 33, 34) to which the support plates (12, 13, 14) are not fixed, and control elements ( 5) and the open region (31, 32, 33, 34) of each transistor (1, 2, 3, 4) are electrically connected by a lead wire (7) made of gold or aluminum. Since the lead wire (7) can be connected to the other main surface of each transistor (1,2,3,4) by the open area (31, 32, 33, 34), the wiring of the lead wire (7) is simplified, Design freedom is improved. In addition, since the length of the lead wire (7) can be shortened, power loss can be reduced and high frequency characteristics can be improved. The second support plate (12) and the fourth support plate (14) are connected to the first transistor (1) and the second transistor (2), respectively, and the third transistor (3) and Since it functions as a connection body with the fourth transistor (4), the semiconductor elements can be connected in a wider area than the lead thin wire (7), and the impedance and inductance of the current path can be further reduced.

図１及び図２に示すように、各素子(1,2,3,4,5)及び支持板(11,12,13,14)並びにリード端子(21a,21b,21c,22a,22b,23a,23b,23c,24a,24b)の一端は、エポキシ樹脂等の比較的高い耐熱性を有する樹脂から成る樹脂封止体(8)により被覆される。図２に示すように、第１の支持板(11)の下面を樹脂封止体(8)により被覆しないが、他の実施の形態では被覆してもよい。更に、各支持板(11,12,13,14)の厚さを夫々異なる厚さに形成してもよい。   As shown in FIGS. 1 and 2, each element (1, 2, 3, 4, 5), support plate (11, 12, 13, 14) and lead terminals (21a, 21b, 21c, 22a, 22b, 23a) , 23b, 23c, 24a, 24b) is covered with a resin sealing body (8) made of a resin having a relatively high heat resistance such as an epoxy resin. As shown in FIG. 2, the lower surface of the first support plate (11) is not covered with the resin sealing body (8), but may be covered in other embodiments. Furthermore, the thickness of each support plate (11, 12, 13, 14) may be formed differently.

本実施の形態では、半導体装置を製造する際に、プレス成形又は打ち抜き成形等の加工法により銅、アルミニウム又はこれらの合金等の材料から成る薄板から形成されたリード端子(21a,21b,21c,22a,22b,23a,23b,23c,24a,24b)及び支持板(11,12,13,14)を含むリードフレームが準備される。周知のダイボンディング法により各支持板(11,12,13,14)の上面に各トランジスタ(1,2,3,4)が例えば導電性接着剤(15)によって接着され、第１のトランジスタ(1)及び第３のトランジスタ(3)が固着された第１の支持板(11)と、第２のトランジスタ(2)が固着された第２の支持板(12)と、第４のトランジスタ(4)が固着された第４の支持板(14)と、制御素子(5)が固着された第３の支持板(13)とが個別に形成される。次に、支持板(11,12,13,14)とトランジスタ(1,2,3,4)との各積層体を例えば導電性接着剤(15)により図１に示すように順次接着して積層する。続いて、周知のワイヤボンディング法により制御素子(5)の主面に設けられた制御端子と、各トランジスタ(1,2,3,4)の開放領域(31,32,33,34)に設けられた制御端子及びリード端子(21a,21b,21c,22a,22b,23a,23b,23c,24a,24b)とをリード細線(7)によって接続する。この後、周知のトランスファモールド法により各支持板(11,12,13,14)及び素子(1,2,3,4,5)を例えばエポキシ樹脂から成る樹脂封止体(8)によって封止し、図１及び図２の半導体装置が得られる。半導体装置全体を樹脂封止体(8)によって被覆するが、リード端子(21a,21b,21c,22a,22b,23a,23b,23c,24a,24b)の他端は樹脂封止体(8)から外部に導出されて外部端子に接続される外部リードとなる。図１に示すリード端子(21a,21b,21c,22a,22b,23a,23b,23c,24a,24b)は、一部を折曲又は湾曲させて同一の高さ位置に形成するのがよい。リード端子(21a,21b,21c,22a,22b,23a,23b,23c,24a,24b)の他端の高さを揃えることにより良好に金型に挟持して樹脂封止体(8)をモールド成型することができる。   In the present embodiment, when manufacturing a semiconductor device, a lead terminal (21a, 21b, 21c, 21c, 21c, 21c, 21c, 21c, 21c, 21c, 21c, 21c, 21c, 21c, 21c, 21c, 21c, 21c, 21c, 21c 22a, 22b, 23a, 23b, 23c, 24a, 24b) and a lead frame including support plates (11, 12, 13, 14) are prepared. Each transistor (1,2,3,4) is bonded to the upper surface of each support plate (11,12,13,14) by, for example, a conductive adhesive (15) by a known die bonding method, and the first transistor ( The first support plate (11) to which the first and third transistors (3) are fixed, the second support plate (12) to which the second transistor (2) is fixed, and the fourth transistor ( A fourth support plate (14) to which 4) is fixed and a third support plate (13) to which the control element (5) is fixed are individually formed. Next, each laminated body of the support plate (11, 12, 13, 14) and the transistor (1, 2, 3, 4) is sequentially bonded with a conductive adhesive (15) as shown in FIG. Laminate. Subsequently, a control terminal provided on the main surface of the control element (5) by a well-known wire bonding method and an open region (31, 32, 33, 34) of each transistor (1, 2, 3, 4) The control terminals and the lead terminals (21a, 21b, 21c, 22a, 22b, 23a, 23b, 23c, 24a, 24b) connected to each other are connected by lead thin wires (7). Thereafter, each support plate (11, 12, 13, 14) and element (1, 2, 3, 4, 5) are sealed with a resin sealing body (8) made of, for example, epoxy resin by a known transfer mold method. Thus, the semiconductor device shown in FIGS. 1 and 2 is obtained. The entire semiconductor device is covered with the resin sealing body (8), but the other end of the lead terminal (21a, 21b, 21c, 22a, 22b, 23a, 23b, 23c, 24a, 24b) is the resin sealing body (8). The lead is led out to the outside and connected to the external terminal. The lead terminals (21a, 21b, 21c, 22a, 22b, 23a, 23b, 23c, 24a, 24b) shown in FIG. 1 are preferably formed at the same height position by bending or bending a part thereof. Mold the resin encapsulant (8) by holding the lead terminals (21a, 21b, 21c, 22a, 22b, 23a, 23b, 23c, 24a, 24b) at the same height and holding them between the molds. Can be molded.

本実施の形態では、図２及び図３に示すように、ハイサイド側の第１のトランジスタ(1)と第３のトランジスタ(3)との上に、ローサイド側の第２のトランジスタ(2)と第４のトランジスタ(4)とが固着され、第２のトランジスタ(2)及び第４のトランジスタ(4)の上に、制御素子(5)が固着される。第２の支持板(12)は、第１のトランジスタ(1)のソース端子と第２のトランジスタ(2)のドレイン端子との接続点(A1)となり、第４の支持板(14)は、第３のトランジスタ(3)のソース端子と第４のトランジスタ(4)のドレイン端子との接続点(A2)となって、第２の支持板(12)のリード端子(22b)と第４の支持板(14)のリード端子(24b)とが負荷(6)に接続される。第１のトランジスタ(1)〜第４のトランジスタ(4)の各ゲート端子は、制御素子(5)に接続され、制御素子(5)からの制御信号を受信する。動作の際に、第１の支持板(11)のリード端子(21b)は、図示しない直流電源の正側端子に接続され、第３の支持板(13)のリード端子(23b)がグランド端子に接続される。第１のトランジスタ(1)と第４のトランジスタ(4)がオンのとき、第２のトランジスタ(2)と第３のトランジスタ(3)とはオフとなり、負荷(6)に一方向の電流(I1)が流れ、その後、第１のトランジスタ(1)と第４のトランジスタ(4)がオフに切り換えられ、第２のトランジスタ(2)と第３のトランジスタ(3)とがオンに切り換えられると、負荷(6)に他方向の電流(I2)が流れて、負荷(6)が交流電流により作動される。第１の半導体素子(1)と第４の半導体素子(4)とを同時にスイッチング動作させ、第３の半導体素子(3)と第２の半導体素子(2)とを同時にスイッチング動作させると共に、第１のトランジスタ(1)及び第４のトランジスタ(4)と第３のトランジスタ(3)及び第２のトランジスタ(2)とを交互にスイッチング動作させることにより、直流電源に接続されたＨ型ブリッジ回路(10)の例えば冷陰極蛍光放電管である負荷(6)を交流電流で駆動できる。その際、半導体装置を動作したときに発生する熱を各支持板(11,12,13,14)を通じて十分に放出して、各素子(1,2,3,4,5)の電気的特性の劣化を防止できる。   In this embodiment, as shown in FIG. 2 and FIG. 3, the second transistor (2) on the low side is placed on the first transistor (1) and the third transistor (3) on the high side. And the fourth transistor (4) are fixed, and the control element (5) is fixed on the second transistor (2) and the fourth transistor (4). The second support plate (12) is a connection point (A1) between the source terminal of the first transistor (1) and the drain terminal of the second transistor (2), and the fourth support plate (14) is It becomes a connection point (A2) between the source terminal of the third transistor (3) and the drain terminal of the fourth transistor (4), and the lead terminal (22b) of the second support plate (12) and the fourth terminal The lead terminal (24b) of the support plate (14) is connected to the load (6). The gate terminals of the first transistor (1) to the fourth transistor (4) are connected to the control element (5) and receive a control signal from the control element (5). In operation, the lead terminal (21b) of the first support plate (11) is connected to the positive terminal of a DC power source (not shown), and the lead terminal (23b) of the third support plate (13) is the ground terminal. Connected to. When the first transistor (1) and the fourth transistor (4) are on, the second transistor (2) and the third transistor (3) are off, and the load (6) has a unidirectional current ( I1) flows, and then the first transistor (1) and the fourth transistor (4) are switched off and the second transistor (2) and the third transistor (3) are switched on. The current (I2) in the other direction flows through the load (6), and the load (6) is operated by the alternating current. The first semiconductor element (1) and the fourth semiconductor element (4) are simultaneously switched, and the third semiconductor element (3) and the second semiconductor element (2) are simultaneously switched. An H-type bridge circuit connected to a DC power source by alternately switching the first transistor (1) and the fourth transistor (4) and the third transistor (3) and the second transistor (2). The load (6) which is a cold cathode fluorescent discharge tube of (10) can be driven with an alternating current. At that time, the heat generated when operating the semiconductor device is sufficiently released through each support plate (11, 12, 13, 14), and the electrical characteristics of each element (1, 2, 3, 4, 5) Can be prevented.

本発明の前記実施の形態は、変更が可能である。例えば、ＭＯＳＦＥＴの代わりに、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）又は一般的なバイポーラトランジスタを使用することができる。また、第１の半導体素子(1)〜第４の半導体素子(4)をトランジスタとして示したが、トランジスタ等のスイッチング素子と他の半導体素子を含む複合素子（ＩＣ）でもよい。   The embodiment of the present invention can be modified. For example, an insulated gate bipolar transistor (IGBT) or a general bipolar transistor can be used instead of the MOSFET. Although the first semiconductor element (1) to the fourth semiconductor element (4) are shown as transistors, a composite element (IC) including a switching element such as a transistor and other semiconductor elements may be used.

冷陰極蛍光放電管の駆動装置等に使用されるマルチチップパワーＩＣ等の半導体装置に良好に適用することが可能である。   The present invention can be favorably applied to a semiconductor device such as a multi-chip power IC used for a cold cathode fluorescent discharge tube driving device or the like.

本発明による半導体装置の一実施の形態を示す平面図The top view which shows one Embodiment of the semiconductor device by this invention 図１のＸ−Ｘ線断面図XX sectional view of FIG. Ｈ型ブリッジ回路を示す回路図Circuit diagram showing H-type bridge circuit

符号の説明Explanation of symbols

(1)・・第１の半導体素子（第１の半導体スイッチング素子、第１のトランジスタ）、 (2)・・第２の半導体素子（第２の半導体スイッチング素子、第２のトランジスタ）、 (3)・・第３の半導体素子（第３の半導体スイッチング素子、第３のトランジスタ）、 (4)・・第４の半導体素子（第４の半導体スイッチング素子、第４のトランジスタ）、 (5)・・制御素子、 (7)・・リード細線、 (11)・・第１の支持板、 (12)・・第２の支持板、 (13)・・第３の支持板、 (14)・・第４の支持板、 (21a,21b,21c,22a,22b,23a,23b,23c,24a,24b)・・リード端子、 (31,32,33,34)・・開放領域、   (1)... First semiconductor element (first semiconductor switching element, first transistor), (2).. Second semiconductor element (second semiconductor switching element, second transistor), (3) ··· Third semiconductor element (third semiconductor switching element, third transistor), (4) · · Fourth semiconductor element (fourth semiconductor switching element, fourth transistor), (5) · .Control element, (7) .. Lead thin wire, (11) .. First support plate, (12) .. Second support plate, (13) .. Third support plate, (14) .. Fourth support plate, (21a, 21b, 21c, 22a, 22b, 23a, 23b, 23c, 24a, 24b) ... lead terminal, (31,32,33,34) ... open region,

Claims (9)

導電性の材料により形成された第１の支持板と、該第１の支持板上に一方の主面が固着された第１の半導体素子と、導電性の材料により形成され且つ前記第１の半導体素子の他方の主面に固着された第２の支持板と、該第２の支持板上に一方の主面が固着された第２の半導体素子とを備え、
前記第１の支持板及び第２の支持板の各々は、前記第１の半導体素子及び第２の半導体素子に電気的に接続されたリード端子を有することを特徴とする半導体装置。 A first support plate made of a conductive material; a first semiconductor element having one main surface fixed on the first support plate; and the first support plate made of a conductive material and the first A second support plate fixed to the other main surface of the semiconductor element; and a second semiconductor element having one main surface fixed to the second support plate;
Each of the first support plate and the second support plate has a lead terminal electrically connected to the first semiconductor element and the second semiconductor element. 前記第２の支持板を介して前記第１の半導体素子と前記第２の半導体素子とが電気的に接続された請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element are electrically connected via the second support plate. 前記第２の支持板は、該第２の支持板に連結され且つ前記第１の半導体素子及び第２の半導体素子に電気的に接続されたリード端子を有する請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the second support plate has a lead terminal connected to the second support plate and electrically connected to the first semiconductor element and the second semiconductor element. 導電性の材料により形成され且つ前記第２の半導体素子の他方の主面に固着された第３の支持板と、該第３の支持板上に固着された制御素子とを備え、
前記第１の半導体素子及び第２の半導体素子は、それぞれ第１の半導体スイッチング素子及び第２の半導体スイッチング素子であり、
前記制御素子は、前記第１の半導体スイッチング素子及び第２の半導体スイッチング素子を交互にオン・オフ制御する請求項１〜３の何れか１項に記載の半導体装置。 A third support plate made of a conductive material and fixed to the other main surface of the second semiconductor element; and a control element fixed on the third support plate,
The first semiconductor element and the second semiconductor element are a first semiconductor switching element and a second semiconductor switching element, respectively.
4. The semiconductor device according to claim 1, wherein the control element alternately controls on / off of the first semiconductor switching element and the second semiconductor switching element. 5. 前記第１の半導体素子及び第２の半導体素子は、前記第２の支持板又は第３の支持板が固着される他方の主面に、前記第２の支持板又は第３の支持板が固着されない開放領域を夫々有し、
前記制御素子と前記第１の半導体素子及び第２の半導体素子の開放領域とは、リード細線により電気的に接続される請求項４に記載の半導体装置。 In the first semiconductor element and the second semiconductor element, the second support plate or the third support plate is fixed to the other main surface to which the second support plate or the third support plate is fixed. Each has an open area that is not
5. The semiconductor device according to claim 4, wherein the control element and the open regions of the first semiconductor element and the second semiconductor element are electrically connected by a thin lead wire. 導電性の材料により形成された第１の支持板と、該第１の支持板上に各一方の主面が固着された第１の半導体素子及び第３の半導体素子と、導電性の材料により形成され且つ前記第１の半導体素子の他方の主面に固着された第２の支持板と、導電性の材料により形成され且つ前記第３の半導体素子の他方の主面に固着された第４の支持板と、前記第２の支持板上に一方の主面が固着された第２の半導体素子と、前記第４の支持板上に一方の主面が固着された第４の半導体素子とを備え、
前記第１の半導体素子及び第２の半導体素子並びに前記第３の半導体素子及び第４の半導体素子は、Ｈ型ブリッジ回路を構成し、
前記第１の半導体素子及び第４の半導体素子と前記第３の半導体素子及び第２の半導体素子とは交互にスイッチング動作を行うことを特徴とする半導体装置。 A first support plate formed of a conductive material, a first semiconductor element and a third semiconductor element each having a main surface fixed on the first support plate, and a conductive material A second support plate formed and fixed to the other main surface of the first semiconductor element; and a fourth support plate formed of a conductive material and fixed to the other main surface of the third semiconductor element. A second semiconductor element having one main surface fixed on the second support plate, and a fourth semiconductor element having one main surface fixed on the fourth support plate; With
The first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element constitute an H-type bridge circuit,
The semiconductor device, wherein the first semiconductor element and the fourth semiconductor element, and the third semiconductor element and the second semiconductor element perform switching operations alternately. 導電性の材料により形成された第１の支持板と、該第１の支持板上に各一方の主面が固着された第１の半導体素子及び第３の半導体素子と、導電性の材料により形成され且つ前記第１の半導体素子の他方の主面に固着された第２の支持板と、導電性の材料により形成され且つ前記第３の半導体素子の他方の主面に固着された第４の支持板と、前記第２の支持板上に一方の主面が固着された第２の半導体素子と、前記第４の支持板上に一方の主面が固着された第４の半導体素子と、導電性の材料により形成され且つ前記第２の半導体素子及び第４の半導体素子の他方の主面に固着された第３の支持板と、該第３の支持板上に固着された制御素子とを備えることを特徴とする半導体装置。   A first support plate formed of a conductive material, a first semiconductor element and a third semiconductor element each having a principal surface fixed on the first support plate, and a conductive material A second support plate formed and fixed to the other main surface of the first semiconductor element; and a fourth support plate formed of a conductive material and fixed to the other main surface of the third semiconductor element. A second semiconductor element having one main surface fixed on the second support plate, and a fourth semiconductor element having one main surface fixed on the fourth support plate; A third support plate made of a conductive material and fixed to the other main surface of the second semiconductor element and the fourth semiconductor element; and a control element fixed on the third support plate A semiconductor device comprising: 前記第２の支持板を介して前記第１の半導体素子と前記第２の半導体素子とが電気的に接続され、前記第４の支持板を介して前記第３の半導体素子と前記第４の半導体素子とが電気的に接続される請求項７に記載の半導体装置。   The first semiconductor element and the second semiconductor element are electrically connected via the second support plate, and the third semiconductor element and the fourth semiconductor element are connected via the fourth support plate. The semiconductor device according to claim 7, wherein the semiconductor device is electrically connected to the semiconductor element. 前記第１の半導体素子、前記第２の半導体素子、前記第３の半導体素子及び前記第４の半導体素子は、前記第２の支持板、第３の支持板又は前記第４の支持板が固着される他方の主面に、前記第２の支持板、第３の支持板又は前記第４の支持板が固着されない開放領域を夫々有し、
前記制御素子と前記第１の半導体素子、第２の半導体素子、前記第３の半導体素子及び前記第４の半導体素子の開放領域とは、リード細線により電気的に接続される請求項７又は８に記載の半導体装置。 The first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element are fixed to the second support plate, the third support plate, or the fourth support plate. Each of the other main surfaces is provided with an open region where the second support plate, the third support plate or the fourth support plate is not fixed,
The control element and the open regions of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element are electrically connected by a thin lead wire. A semiconductor device according to 1.
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