JP2001036001A - Power semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor module which can effectively cool a sealed power element. SOLUTION: In a power semiconductor module 100, rather than a metallic fine wire used conventionally but a net-like metallic fine wire is used for a connecting the line between an emitter electrode 14 and an electrode terminal 22 for an emitter. The net-like metallic fine wire 24 is very much larger in surface area than that of the metallic fine wire. Therefore, the heat radiation efficiency is improved, so it can effectively cool a power semiconductor chip 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor power module used for an electric vehicle.

[0002]

2. Description of the Related Art An inverter for supplying a predetermined AC power to a coil of a motor of an electric vehicle or the like (including a hybrid vehicle) is composed of a power switching element and the like. IGBT and power MOSF as power semiconductors
A power element formed on a semiconductor chip such as an ET is used. The semiconductor chip on which the power elements are formed is sealed in one power module together with a control circuit and the like.

In such a power module,
Since a large current flows through the sealed power element itself,
This power element generates heat and may cause thermal destruction. Conventionally, in order to prevent such thermal destruction, the semiconductor chip has been cooled by attaching a sealed semiconductor chip to a heat sink via an insulating plate and cooling the heat sink.

FIG. 17 shows a conventional power semiconductor module. In the power semiconductor module 600,
IGBT (Insulated Ga) as a power element
The power semiconductor chip 2 on which teBipolar Transistor is formed and the semiconductor chip 40 on which a diode is formed are sealed. Power semiconductor chip 2
The semiconductor chip 40 is fixed to the conductor layer 6 on the insulating substrate 4 such as AlN by solder (not shown) or the like. The conductor layer 6 is patterned so that the emitter current and the like of the power semiconductor chip 2 and the semiconductor chip 40 can be appropriately taken out.

An emitter electrode (not shown) on the power semiconductor chip 2 is electrically connected to the conductor layer 6 by a thin metal wire 80 made of a thin metal wire such as Al or Au. On the other hand, the conductor layer 6 has an emitter electrode terminal 2 for electrically connecting the power semiconductor chip 2 and an external device.
2 are connected to supply an emitter current to an external device. An anode electrode (not shown) of the diode on the semiconductor chip 40 is electrically connected to the emitter electrode terminal 22 via a thin metal wire 84. On the other hand, a gate electrode (not shown) on the power semiconductor chip 2 is electrically connected to a predetermined position of the conductor layer 6 by a thin metal wire 80, similarly to the emitter electrode.

As described above, conventionally, the power semiconductor chip 2
The upper emitter electrode and the emitter electrode terminal 22 were connected by a thin metal wire 82.

[0007]

A power semiconductor module used for a driving inverter of an electric vehicle or the like needs a current of about several hundreds of amperes. When such a large current flows, the heat generated by the resistance of the thin metal wires and the heat generated inside the semiconductor chip cannot be effectively cooled. Then, there has been a problem that the temperature of the semiconductor chip increases and the safe operation area of the semiconductor chip decreases.

Further, due to the thermal expansion of the thin metal wire, an excessive thermal stress is generated at a connection portion between the semiconductor chip and the thin metal wire, so that the bonding surface is apt to be separated.

In order to correct the above-mentioned problems, a method of connecting several tens of thin metal wires to the emitter electrode may be adopted. In this case, there is a problem in that the time spent in the wire bonding process is lengthened and the manufacturing cost is increased.

[0010] In addition, since the thin metal wire has a parasitic inductance, a surge voltage due to a change in a flowing current and electric noise accompanying the change have adversely affected the operation of the inverter and peripheral devices.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a power semiconductor module capable of effectively cooling a sealed power element.

[0012]

SUMMARY OF THE INVENTION The present invention relates to a power semiconductor module having a built-in power semiconductor chip, comprising an electrode terminal for making an electrical connection to the outside, and an electrical connection between the electrode terminal and the power semiconductor chip. And at least a part of the connection line is made of a net-like metal wire.

The power semiconductor chip generates heat according to its operation. The connection line is a conductor that makes an electrical connection,
The heat of the power semiconductor chip is easily transmitted through the connection line. At least a part of the connection line is made of a net-like metal wire in which a large number of thin metal wires are woven. Since the reticulated metal wire has a very large surface area, the reticulated metal wire can effectively radiate heat generated in the power semiconductor chip.

The present invention also relates to a power semiconductor module incorporating a power semiconductor chip, comprising an electrode terminal for making an electrical connection to the outside, and a connection for electrically connecting the electrode terminal to the power semiconductor chip. A conductive layer formed on both sides of an insulating substrate having a through hole and on an inner wall portion of the through hole, wherein at least a part of the electrode terminal is made of a metal plate. It is characterized by consisting of.

The power semiconductor chip is connected to electrode terminals via conductor layers formed on both surfaces of the insulating substrate and on the inner wall of the through hole. Further, a part of the electrode terminal connected to the conductor layer is also a metal plate and has a relatively large area. Therefore, heat generated in the power semiconductor chip can be efficiently dissipated.

Further, since the connection line between the power semiconductor chip and the electrode terminal is a conductor layer formed on both surfaces of the insulating substrate, the distance between the power semiconductor chip and the electrode terminal can be reduced. Therefore, the length of the conductor layer may be shorter than that of the thin metal wire. Therefore, the resistance value of the conductor layer decreases, and the amount of heat generated by the conductor layer itself due to electric current also decreases. Further, the parasitic inductance is reduced, and the surge voltage and the electric noise can be reduced.

Further, since the distance between the power semiconductor chip and the electrode terminals can be reduced, it is possible to reduce the size of the entire power semiconductor module, and to provide a power semiconductor module with a low manufacturing cost. Becomes possible.

It is preferable that the power semiconductor module further includes a heat radiating plate closely attached to one main surface of the power semiconductor chip. The power semiconductor chip can be efficiently cooled from both sides of the side connected to the electrode terminals and the side to which the heat sink is adhered.

Further, the insulating substrate has, on one main surface thereof,
It is preferable to have a control semiconductor chip electrically connected to the power semiconductor chip.

Since the control semiconductor chip is on the insulating substrate, the length of the connection line between the power semiconductor chip and the control semiconductor chip can be reduced, and the electric noise mixed into the connection line can be reduced. Is possible. Therefore, it is possible to prevent the power semiconductor chip from malfunctioning due to electric noise mixed into the connection line between the control semiconductor chip and the power semiconductor chip.

[0021]

Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings. The same members are denoted by the same reference symbols throughout the drawings.

FIGS. 1 and 2 are schematic diagrams of a power semiconductor module according to the present embodiment. FIG. 1 is a schematic sectional view of the power semiconductor module 100, and is a schematic sectional view taken along line BB of FIG. FIG. 2 is a schematic plan view taken along line AA in FIG.

In the power semiconductor module 100, a power semiconductor chip 2 on the surface of which an IGBT is formed as a power element is fixed to a conductor layer 6 on an insulating substrate 4 by soldering or the like. The insulating substrate 4 is attached to the metal substrate 34 via the conductor layer 10. The conductor layer 10 and the power semiconductor chip 2 are electrically insulated by the insulating substrate 4.

Here, IGB is used as a power element.
T, but the power MOSFET (Metal
Oxide Semiconductor Fail
Other power elements such as d-Effect Transistor may be used.

FIG. 3 is a plan view of the power semiconductor chip 2. An IGBT is formed on the power semiconductor chip 2 as a power element, and a gate electrode 1 is formed on the surface of the IGBT.
2 and a plurality of emitter electrodes 14, and a collector electrode (not shown) is provided on almost the entire back surface thereof.

A gate electrode 12 on the power semiconductor chip 2;
In order to supply a voltage to the emitter electrode 14 and the collector electrode (that is, the semiconductor substrate of the power semiconductor chip 2), it is necessary to electrically connect these electrodes to electrode terminals electrically connected to the outside of the chip. . The gate electrode 12 is electrically connected to the gate electrode terminal 18 via the thin metal wire 16 and the conductor layer 17. This gate electrode terminal 1
8 supplies a voltage to the gate electrode 12 on the power semiconductor chip 2.

The voltage supply to the collector electrode on the power semiconductor chip 2, that is, the semiconductor substrate of the power semiconductor chip 2,
The operation is performed from the collector electrode terminal 20 via the conductor layer 6 on the back surface of the power semiconductor chip 2.

Emitter electrode 14 on power semiconductor chip 2
Is supplied from the emitter electrode terminal 22. A fine mesh wire 24 is connected to the emitter electrode 14 with solder or the like. The reticulated metal wire 24 is the metal wire 1
It is composed of a large number of fine metal wires woven into a net shape smaller than 6. Wiring metal terminals 26 are further connected to the net-like metal wires 24 by soldering. The wiring metal terminal 26 is joined to the conductor layer 28 by soldering, and the emitter electrode terminal 22 is further joined to the conductor layer 28. As described above, the emitter electrode 14 is electrically connected to the emitter electrode terminal 22 via the thin net-like metal wire 24, the wiring metal terminal 26, and the conductor layer 28.

The power semiconductor chip 2, the insulating substrate 4, the electrode terminals 18, 20, 22 and the like are enclosed in a package 36 composed of an outer case 32 and a metal substrate 34. At this time, the inside of the package 36 may be filled with silicon gel, epoxy resin, or the like.

In the power semiconductor module 100,
The connection line between the emitter electrode 14 and the emitter electrode terminal 22 is formed of a conventionally used thin metal wire (for example, a thin metal wire 1).
6, the net-like metal fine wires 24 are used. The reticulated metal wire 24 has a very large surface area compared to the metal wire. Therefore, the heat radiation efficiency is improved, and the power semiconductor chip 2 can be effectively cooled.

FIGS. 4, 5 and 6 show schematic views of a power semiconductor module according to another embodiment. FIG.
Is a schematic cross-sectional view of the power semiconductor module 200;
FIG. 6 is a schematic sectional view taken along line EE in FIG. 5. FIG. 5 is a schematic plan view taken along the line CC in FIG. 4, and FIG.
It is sectional drawing in a line.

The power semiconductor module 200 has a power semiconductor chip 2 on which an IGBT is formed as a power element.
And a semiconductor chip 40 on which a diode is formed. FIG. 7 is a plan view of the semiconductor chip 40. A diode is formed on the semiconductor chip 40, and an anode electrode 42 is formed on the front surface, and a cathode electrode (not shown) is formed on the back surface.

Power semiconductor chip 2 and semiconductor chip 40
Is fixed on the conductor layer 6 of an insulating substrate 4 made of AlN or the like having the conductor layer 6 and the conductor layer 10 on both surfaces by solder (not shown) or the like. The collector electrode on the back surface of the power semiconductor chip 2 and the cathode electrode on the back surface of the semiconductor chip 40 are electrically connected by the conductor layer 6.

On the other hand, the gate electrode 12, the emitter electrode 14 on the power semiconductor chip 2 and the anode electrode 42 of the semiconductor chip 40 are respectively provided on the front side of each chip and on an insulating substrate having conductor layers 44 and 46 on both sides. 48 conductive layers 46
Is electrically connected to

FIG. 8 is a schematic view of the insulating substrate 48 shown in FIG. FIG. 8A shows an insulating substrate 48.
FIG. 8B is a plan view of FIG.
FIG. 8A is a plan view of the insulating substrate 48 as viewed from the back surface, and FIG. 8C is an enlarged cross-sectional view taken along line FF of FIG. 8A. On the back surface of the insulating substrate 48, a conductor layer 46 is patterned so that the gate electrode 12, the emitter electrode 14 of the power semiconductor chip 2 and the anode electrode 42 of the semiconductor chip 40 can be connected by solder or the like (FIG. 8 (b)). This patterned conductor layer 46
Is a conductor layer 52 provided on the insulating substrate and formed on the inner wall of the plurality of through holes 50, and is connected to the conductor layer 46 on the front surface.

The conductor electrode 46 has an emitter electrode terminal 2
2 are connected. Part of the emitter electrode terminal 22 is formed from a metal plate. The emitter electrode terminal 22 has a large area.

The insulating substrate 48 may be a translucent substrate, and the positioning when fixing the power semiconductor chip 2 or the semiconductor chip 40 to the conductor layer 46 on the front and back surfaces of the insulating substrate 48, respectively. Alignment mark 54 for
56 etc. are given.

FIG. 9 shows an assembling process of the power semiconductor module 200. Conductor layer 46 of insulating substrate 48
Next, the power semiconductor chip 2 and the semiconductor chip 40 are fixed by soldering by reflow soldering, respectively (FIG. 9A). For this connection, a conductive resin may be used instead of the solder. At this time, the insulating substrate 48 is a translucent substrate, and the positioning of the insulating substrate 48 with the power semiconductor chip 2 and the semiconductor chip 40 is performed by the alignment marks 54 and 56 on the front and back surfaces of the insulating substrate 48. It can be done easily.

Thereafter, the emitter electrode terminal 22 is connected to the conductor layer 44 by soldering or the like. In addition, the power semiconductor chip 2
The back surface of the semiconductor chip 40 is joined to the conductor layer 6 of the insulating substrate 4 by solder or the like (FIG. 9B). After that, by connecting the insulating substrate 4 to the metal substrate 34, it is sealed in the package 36, and the power semiconductor module 200 is completed (FIGS. 4, 5, and 6). At this time, a silicone gel may be inserted into the inside, and finally the module gap may be filled with epoxy resin.

FIG. 10 shows a power semiconductor module 200.
3 shows the maximum temperature of the power semiconductor chip 2 with respect to the rated output. The power semiconductor module 200 was observed to have a maximum temperature drop of about 15 ° C. as compared to the conventional one.

As described above, the power semiconductor module of the present embodiment is connected to the electrode terminals 22, 18 and the like by the conductor layer 46. Therefore, compared to the thin metal wire, the conductor layer 46
May be short. Therefore, the resistance value of the conductor layer decreases, and the amount of heat generated by the conductor layer itself due to electric current also decreases. Further, the parasitic inductance is reduced, and the surge voltage and the electric noise can be reduced.

The electrode terminals 22, 18, and 20 are at least partially formed of a metal plate and have a relatively large area. Therefore, heat generated in the power semiconductor chip 2 can be efficiently radiated.

Further, since the distance between the power semiconductor chip 2 and the emitter electrode terminal 22 can be reduced, the size of the entire power semiconductor module can be reduced, and the power semiconductor module can be manufactured at low cost. Can be provided.

The power semiconductor chip 2 includes an insulating substrate 4
If 8 is an insulating substrate having a certain degree of thermal conductivity, the metal substrate 34 can function as a heat radiating plate and radiate generated heat.

FIGS. 11 and 12 show a power semiconductor module 300 according to another embodiment. FIG. 11 is a cross-sectional view of the power semiconductor module 300 taken along line HH in FIG. FIG. 12 is a plan view of the power semiconductor module 300 in FIG. 11 taken along the line GG. On the insulating substrate 48 of the power semiconductor module 300, a control semiconductor chip 80 having a control circuit for controlling the power semiconductor chip 2 is connected. The control semiconductor chip 80 receives a control signal from the outside of the power semiconductor module 300 and can control the drive current of the power semiconductor chip 2 according to the signal.

FIG. 13 is a plan view of the insulating substrate 48. FIG. 13A is a plan view of the front surface of the insulating substrate 48, and FIG.
8 shows a plan view of the back surface. In this plan view, the insulating substrate 48 is in a state where a bent portion is extended. The control semiconductor chip 80 is fixed to the front surface portion 84 with solder or the like. Control semiconductor chip 80
Is input to the power semiconductor chip 2 through the conductor layer 46 on the insulating substrate 48 to the gate electrode.
As described above, since the power semiconductor module 300 includes the control semiconductor chip 80 on the insulating substrate 48, the distance of the connection line between the control semiconductor chip 80 and the power semiconductor chip 2 is reduced. Therefore, it is possible to greatly reduce the mixing of electromagnetic noise into the connection line.

FIG. 14 shows another power semiconductor module 400. Power semiconductor module 40
In the reference numeral 0, an insulating substrate 60 is further connected on the conductor layer 44 of the insulating substrate 48, and the control semiconductor chips 62, 64 and the like are fixed on the insulating substrate 60. Control semiconductor chip 6
Reference numerals 2 and 64 denote external electrode terminals 61 electrically connected to the outside.
have.

FIG. 15 is a plan view of the insulating substrate 60, FIG. 15A shows a front surface of the insulating substrate 60, and FIG. The back side is shown. The insulating substrate 60 has conductor layers 66 and 68 on both sides.
Having.

The conductor layer 68 is formed on the conductor layer 4 of the insulating substrate 48.
4 is connected by solder or the like. The conductor layer 68 is formed on the insulating substrate 4.
The pattern is formed so that the gate electrode and the emitter electrode of the power semiconductor chip 2 are appropriately and electrically connected to each other via the eight conductor layers 44.

The conductor layer 66 is patterned so that the emitter electrode terminal 22 and the gate electrode terminal 18 are appropriately connected to the power semiconductor chip 2.
Further, a part of the conductor layer 66 includes the control semiconductor chip 6.
There is provided an area 72 to which the second and the second 64 can be fixed. The conductor layers 66 and 68 are electrically connected through the through hole 70.

In the power semiconductor module 400,
Since the control semiconductor chip 80 is provided on the insulating substrate 60, the distance of the connection line between the control semiconductor chip 80 and the power semiconductor chip 2 is reduced. Therefore, it is possible to greatly reduce the mixing of electromagnetic noise into the connection line.

FIG. 16 shows the emitter electrode terminal 2.
2, a power semiconductor module 500 having a water cooling pipe 74 is shown. Thus, by providing the water cooling pipe 74 in a part of the emitter electrode terminal 22, it is possible to further improve the cooling of the power semiconductor chip 2.

[0053]

As described above, according to the present invention, the amount of heat escaping from the electrode terminals for making an electrical connection to the outside and the power semiconductor chip, particularly from the connection line side, increases, so that the power semiconductor chip is effectively cooled. It is possible.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a power semiconductor module according to an embodiment.

FIG. 2 is a schematic plan view of the power semiconductor module of the present embodiment.

FIG. 3 is a plan view of a power semiconductor chip.

FIG. 4 is a schematic sectional view of a power semiconductor module according to another embodiment.

FIG. 5 is a schematic plan view of a power semiconductor module according to another embodiment.

FIG. 6 shows a power semiconductor module according to another embodiment.
3 is a schematic sectional view taken along line DD in FIG.

FIG. 7 is a plan view of a semiconductor chip on which a diode is formed.

FIG. 8 is a schematic diagram of an insulating substrate for connecting a power semiconductor chip and an electrode.

FIG. 9 is a process schematic view showing a method for manufacturing a power semiconductor module.

FIG. 10 is a diagram showing a difference in maximum chip temperature between the power semiconductor module of the present embodiment and a conventional power semiconductor module.

FIG. 11 is a schematic sectional view of a power semiconductor module according to another embodiment.

FIG. 12 is a schematic plan view of a power semiconductor module according to another embodiment.

FIG. 13 is a plan view of an insulating substrate according to another embodiment.

FIG. 14 is a cross-sectional view of a power semiconductor module according to another embodiment.

FIG. 15 is a plan view of an insulating substrate according to another embodiment.

FIG. 16 is a sectional view of a power semiconductor module having a water cooling pipe.

FIG. 17 is a cross-sectional view of a conventional power semiconductor module.

[Explanation of symbols]

2 power semiconductor chips, 18, 20, 22 electrode terminals,
24 Reticulated metal wire, 44, 46 Conductive layer, 48 Insulating substrate, 100, 200, 300, 400 Power semiconductor module.

Claims (4)

[Claims] 1. A power semiconductor module incorporating a power semiconductor chip, comprising: an electrode terminal for making an electrical connection to the outside; and a connection line for electrically connecting the electrode terminal to the power semiconductor chip. A power semiconductor module, wherein at least a part of the connection line is formed of a net-like metal wire. 2. A power semiconductor module incorporating a power semiconductor chip, comprising: an electrode terminal for making an electrical connection to the outside; and a connection line for electrically connecting the electrode terminal to the power semiconductor chip. At least a part of the electrode terminal is made of a metal plate, and at least a part of the connection line is made of a conductor layer formed on both surfaces of an insulating substrate having a through hole and an inner wall portion of the through hole. Characteristic power semiconductor module. 3. The power semiconductor module according to claim 2, further comprising a radiator plate adhered to one main surface of said power semiconductor chip. 4. The power semiconductor module according to claim 2, wherein the insulating substrate has a control semiconductor chip electrically connected to the power semiconductor chip on one main surface thereof. A power semiconductor module, characterized in that: