JP2010093287A - Power semiconductor module - Google Patents

Power semiconductor module Download PDF

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Publication number
JP2010093287A
JP2010093287A JP2009286738A JP2009286738A JP2010093287A JP 2010093287 A JP2010093287 A JP 2010093287A JP 2009286738 A JP2009286738 A JP 2009286738A JP 2009286738 A JP2009286738 A JP 2009286738A JP 2010093287 A JP2010093287 A JP 2010093287A
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power semiconductor
semiconductor module
wiring layer
internal electrode
solder layer
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JP4870204B2 (en
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Kazuhiro Morishita
和博 森下
Isao Umezaki
勲 梅嵜
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a crack in a soldered portion of a power semiconductor module even when a temperature cycle is exerted to the power semiconductor module, and also to prevent growth of the crack even if the crack is generated. <P>SOLUTION: The power semiconductor module includes: an insulating substrate 2 including an insulating board 13 and a wiring layer 12 provided on the main surface of the insulating board; a semiconductor device fixed on the wiring layer; and an internal electrode 9 which has a joint surface substantially parallel to the main surface of the insulating board and whose joint surface is bonded to the wiring layer with the solder layer 10. The internal electrode has a plurality of striped upper projections 21 arranged in approximately parallel on the joint surface covered with the solder layer and the wiring layer has a plurality of striped lower projections arranged in approximately parallel in the region covered with the solder layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明はパワー半導体モジュールに関し、特に、モータ等の電気器機の電力変換装置等に用いられるパワー半導体モジュールに関する。   The present invention relates to a power semiconductor module, and more particularly, to a power semiconductor module used for a power conversion device of an electric device such as a motor.

従来のパワー半導体モジュールでは、絶縁基板の上に設けられた配線層に半導体素子や内部電極が半田層で接合され、更に、半導体素子等がモールド樹脂で封止されていた。   In a conventional power semiconductor module, a semiconductor element and internal electrodes are joined to a wiring layer provided on an insulating substrate with a solder layer, and the semiconductor element and the like are further sealed with a mold resin.

特開昭６０−２２０９３９号公報JP-A-60-220939

電力用のパワー半導体モジュールでは、半導体素子から発熱があり、パワー半導体モジュールの内部に温度サイクルが発生し、電流が流れる部分に大きな熱ストレスが加わる。このため、材質の異なる部品が接合されている部分では、線膨張係数の違いから両者の間に熱応力が発生し、接合部分に亀裂が生じるという問題があった。
特に、パワー半導体モジュールでは、内部電極等の接合には半田が用いられ、半田接合部の割れが、製品寿命を決める一つの要素となっていた。 In a power semiconductor module for electric power, heat is generated from a semiconductor element, a temperature cycle is generated inside the power semiconductor module, and a large thermal stress is applied to a portion where current flows. For this reason, there is a problem that in a portion where parts of different materials are joined, thermal stress is generated between the two due to a difference in linear expansion coefficient, and a crack occurs in the joined portion.
In particular, in power semiconductor modules, solder is used for joining internal electrodes and the like, and cracks in the solder joints have become one of the factors that determine the product life.

そこで、本発明は、温度サイクルが加わった場合の、半田接合部で発生した割れの広がりを防止したパワー半導体モジュールの提供を目的とする。また、半田接合部での割れの発生を防止したパワー半導体モジュールの提供を目的とする。   Accordingly, an object of the present invention is to provide a power semiconductor module that prevents the spread of cracks generated at a solder joint when a temperature cycle is applied. Moreover, it aims at provision of the power semiconductor module which prevented generation | occurrence | production of the crack in a solder joint part.

本発明は、絶縁板と絶縁板の主表面に設けられた配線層とを含む絶縁基板と、配線層上に固定された半導体素子と、絶縁板の主表面に略平行な接合面を有し、接合面が配線層上に半田層で接続された内部電極とを含み、内部電極が、半田層で覆われた接合面に、略平行に配置された複数のストライプ状の上部突起部を有し、かつ配線層が、半田層で覆われた領域に、略平行に配置された複数のストライプ状の下部突起部を有することを特徴とするパワー半導体モジュールに関する。   The present invention has an insulating substrate including an insulating plate and a wiring layer provided on the main surface of the insulating plate, a semiconductor element fixed on the wiring layer, and a bonding surface substantially parallel to the main surface of the insulating plate. And an internal electrode connected with a solder layer on the wiring layer, and the internal electrode has a plurality of stripe-shaped upper protrusions arranged substantially parallel to the joint surface covered with the solder layer. In addition, the present invention relates to a power semiconductor module, wherein the wiring layer has a plurality of stripe-shaped lower protrusions arranged substantially in parallel in a region covered with a solder layer.

以上のように、本発明にかかるパワー半導体モジュールでは、温度サイクルが加わった場合に、半田接合部での割れを防止でき、また割れが発生してもその広がりを防止できるため、パワー半導体モジュールの製品寿命を長くし、信頼性を向上させることができる。   As described above, in the power semiconductor module according to the present invention, when a temperature cycle is applied, it is possible to prevent cracks at the solder joints, and even if cracks occur, the spread thereof can be prevented. Product life can be extended and reliability can be improved.

本発明の実施の形態１にかかるパワー半導体モジュールの断面図である。It is sectional drawing of the power semiconductor module concerning Embodiment 1 of this invention. 発明の実施の形態１にかかるパワー半導体モジュールの部分断面図である。It is a fragmentary sectional view of the power semiconductor module concerning Embodiment 1 of invention. 従来のパワー半導体モジュールの部分断面図である。It is a fragmentary sectional view of the conventional power semiconductor module. 発明の実施の形態１にかかる他のパワー半導体モジュールの部分断面図である。It is a fragmentary sectional view of the other power semiconductor module concerning Embodiment 1 of invention. 発明の実施の形態２にかかるパワー半導体モジュールの一部の斜視図である。It is a one part perspective view of the power semiconductor module concerning Embodiment 2 of invention. 発明の実施の形態２にかかる他のパワー半導体モジュールの一部の斜視図である。It is a one part perspective view of the other power semiconductor module concerning Embodiment 2 of invention. 発明の実施の形態３にかかるパワー半導体モジュールの部分断面図である。It is a fragmentary sectional view of the power semiconductor module concerning Embodiment 3 of invention. 発明の実施の形態４にかかるパワー半導体モジュールの部分断面図である。It is a fragmentary sectional view of the power semiconductor module concerning Embodiment 4 of invention. 発明の実施の形態４にかかる他のパワー半導体モジュールの部分断面図である。It is a fragmentary sectional view of the other power semiconductor module concerning Embodiment 4 of invention.

実施の形態１．
図１は、全体が１００で表される、本発明の実施の形態１にかかるパワー半導体モジュールの断面図である。また、図２は、図１に符合Ａで示す部分を拡大した断面図である。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of a power semiconductor module according to a first embodiment of the present invention, the whole being represented by 100. FIG. 2 is an enlarged cross-sectional view of a portion indicated by reference numeral A in FIG.

パワー半導体モジュール１００は、例えば銅からなるベース板１を含む。ベース板１の上には、両面に金属配線層１２、１４が設けられた絶縁体１３からなる絶縁基板２が接続されている。絶縁体１３は、例えばアルミナからなり、金属配線層１２、１４は例えば銅からなる。   The power semiconductor module 100 includes a base plate 1 made of, for example, copper. An insulating substrate 2 made of an insulator 13 having metal wiring layers 12 and 14 provided on both sides is connected to the base plate 1. The insulator 13 is made of alumina, for example, and the metal wiring layers 12 and 14 are made of copper, for example.

絶縁基板２の上には、例えばＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）やフリーホイールダイオードなどの半導体素子３が半田層１０で接続されている。また、絶縁基板２の上には、同じく半田層１０により内部電極９が接続されている。半田層１０には、例えば、錫と鉛の合金が用いられる。半導体素子３同士の間や、半導体素子３と絶縁基板２に設けられた金属配線層１２との間は、例えばアルミニウムからなるワイヤ４で接続されている。   On the insulating substrate 2, for example, a semiconductor element 3 such as an IGBT (Insulated Gate Bipolar Transistor) or a free wheel diode is connected by a solder layer 10. An internal electrode 9 is connected to the insulating substrate 2 by the solder layer 10. For example, an alloy of tin and lead is used for the solder layer 10. The semiconductor elements 3 and the semiconductor elements 3 and the metal wiring layer 12 provided on the insulating substrate 2 are connected by wires 4 made of, for example, aluminum.

ベース板１はケース６で囲まれ、上部は蓋７で覆われている。ケース６の中にはシリコンゲル５が入れられ、半導体素子３等が封止されている。   The base plate 1 is surrounded by a case 6 and the upper part is covered with a lid 7. A silicon gel 5 is placed in the case 6 to seal the semiconductor element 3 and the like.

パワー半導体モジュール１００では、内部電極９の周りの金属配線層１２に突起部２１が設けられている。より厳密に言えば、内部電極９の接合面と半田層１０を挟んで対向する金属配線層１２の領域を囲むように突起部２１が形成されている。図２の断面では２箇所に見えられる突起部２１は、実際には、内部電極９の周囲を囲むように連続して設けられている。   In the power semiconductor module 100, the protrusion 21 is provided on the metal wiring layer 12 around the internal electrode 9. Strictly speaking, the protrusion 21 is formed so as to surround a region of the metal wiring layer 12 facing the bonding surface of the internal electrode 9 with the solder layer 10 interposed therebetween. The protrusions 21 that can be seen at two places in the cross section of FIG. 2 are actually provided continuously so as to surround the periphery of the internal electrode 9.

図３は、従来のパワー半導体モジュールの、図１のＡに相当する部分の断面図を示す。例えばアルミナからなる絶縁体１３と、例えば銅からなる内部電極９との線膨張係数の違いから、半導体素子３の発熱で温度サイクルが加わった場合、図３に示すように、絶縁基板２の金属配線層１２と半田層１０との境界近傍や、内部電極９と半田層１０との境界近傍に割れ２０が発生する。発生した割れ２０は、金属配線層１２と半田層１０との界面や、内部電極９と半田層１０との界面に沿って、半田層１０の内部に向かって進行する。   FIG. 3 is a sectional view of a portion corresponding to A in FIG. 1 of a conventional power semiconductor module. For example, when a temperature cycle is applied by heat generation of the semiconductor element 3 due to a difference in linear expansion coefficient between the insulator 13 made of alumina and the internal electrode 9 made of copper, for example, as shown in FIG. Cracks 20 occur near the boundary between the wiring layer 12 and the solder layer 10 and near the boundary between the internal electrode 9 and the solder layer 10. The generated crack 20 proceeds toward the inside of the solder layer 10 along the interface between the metal wiring layer 12 and the solder layer 10 and the interface between the internal electrode 9 and the solder layer 10.

本実施の形態１にかかるパワー半導体モジュール１００では、金属配線層１２に突起部２１が設けられているため、絶縁基板２の金属配線層１２と半田層１０との境界近傍で発生し、内部に向かって進行する割れ２０は、突起部２１に到達した時点で、それ以上進行しなくなる。   In the power semiconductor module 100 according to the first embodiment, since the protruding portion 21 is provided on the metal wiring layer 12, it occurs near the boundary between the metal wiring layer 12 and the solder layer 10 of the insulating substrate 2. The crack 20 that progresses toward the projecting portion 21 does not progress any further when it reaches the protrusion 21.

このように、パワー半導体モジュール１００では、温度サイクルが加わった場合に、半田層１０に割れ２０が発生してもその広がりを防止できるため、パワー半導体モジュール１００の製品寿命を長くし、信頼性を向上させることができる。   Thus, in the power semiconductor module 100, when the temperature cycle is applied, even if a crack 20 occurs in the solder layer 10, it can be prevented from spreading, so that the product life of the power semiconductor module 100 is extended and reliability is improved. Can be improved.

また、内部電極９と絶縁基板２との半田層１０による接合面積を小さくでき、パワー半導体モジュールの小型化に寄与することもできる。   Moreover, the joint area by the solder layer 10 between the internal electrode 9 and the insulating substrate 2 can be reduced, which can contribute to miniaturization of the power semiconductor module.

図４は、本実施の形態１にかかる他のパワー半導体モジュールの、Ａに相当する部分の断面図である。図４では、突起部２２が、内部電極９の絶縁基板２に対向する部分の周囲を囲むように設けられている。   FIG. 4 is a cross-sectional view of a portion corresponding to A of another power semiconductor module according to the first embodiment. In FIG. 4, the protrusion 22 is provided so as to surround the periphery of the portion of the internal electrode 9 that faces the insulating substrate 2.

このような突起部２２を設けることにより、内部電極９と半田層１０との境界近傍に発生して内部に向かって進行する割れ２０は、突起部２２に到達した時点で、それ以上進行しなくなる。   By providing such a protrusion 22, the crack 20 that occurs near the boundary between the internal electrode 9 and the solder layer 10 and progresses toward the inside does not progress further when it reaches the protrusion 22. .

なお、パワー半導体モジュールは、突起部２１と突起部２２のいずれか一方だけでも良いが、双方を備えても構わない。   Note that the power semiconductor module may include only one of the protrusion 21 and the protrusion 22, but may include both.

実施の形態２．
図５は、本発明の実施の形態２にかかるパワー半導体モジュールに用いる内部電極９の、絶縁基板２に半田層１０で接続される部分の斜視図である。
本実施の形態２にかかる内部電極９は、板状部１９と縒り線部２３とからなる。絶縁基板２と半田層１０により接合される縒り線部２３は、例えば複数の銅の細線を縒り合わせた構造からなる。銅の細線には、ニッケルメッキ等が施されている。縒り線部２３は、例えば銅からなる板状部１９にろう付けされている。 Embodiment 2. FIG.
FIG. 5 is a perspective view of a portion of the internal electrode 9 used in the power semiconductor module according to the second embodiment of the present invention that is connected to the insulating substrate 2 with the solder layer 10.
The internal electrode 9 according to the second embodiment includes a plate-like portion 19 and a twisted wire portion 23. The twisted wire portion 23 joined by the insulating substrate 2 and the solder layer 10 has a structure in which, for example, a plurality of copper thin wires are wound together. The fine copper wire is nickel-plated or the like. The twisted wire portion 23 is brazed to a plate-like portion 19 made of, for example, copper.

本実施の形態２にかかる内部電極９では、絶縁基板２と半田層１０による接合される部分が、板状部１９に比較して変形しやすい縒り線部２３からなる。このため、温度サイクルが加わった場合に、縒り線部２３が容易に変形して、半田層１０に割れ２０が発生するのを防止できる。   In the internal electrode 9 according to the second embodiment, the portion to be joined by the insulating substrate 2 and the solder layer 10 is composed of a twisted wire portion 23 that is more easily deformed than the plate-like portion 19. For this reason, when the temperature cycle is applied, it is possible to prevent the twisted wire portion 23 from being easily deformed and the crack 20 from being generated in the solder layer 10.

図６は、本発明の実施の形態２にかかる他のパワー半導体モジュールに用いる内部電極９の、絶縁基板２に半田層１０で接続される部分の斜視図である。
かかる内部電極９は、板状部２９と編み線部２４とからなる。絶縁基板２と半田層１０により接合される編み線部２４は、例えば複数の銅の細線をメッシュ状に編んだ構造からなる。銅の細線には、ニッケルメッキ等が施されている。編み線部２４は、例えば銅からなる板状部２９にろう付けされている。 FIG. 6 is a perspective view of a portion of the internal electrode 9 used in another power semiconductor module according to the second embodiment of the present invention that is connected to the insulating substrate 2 with the solder layer 10.
The internal electrode 9 includes a plate-like portion 29 and a knitted wire portion 24. The knitted wire portion 24 joined by the insulating substrate 2 and the solder layer 10 has, for example, a structure in which a plurality of copper fine wires are knitted in a mesh shape. The copper thin wire is nickel-plated or the like. The knitted wire portion 24 is brazed to a plate-like portion 29 made of, for example, copper.

図６に示された内部電極９では、絶縁基板２と半田層１０により接合される部分が、板状部２９に比較して変形しやすい編み線部２４からなる。このため、温度サイクルが加わった場合に、編み線部２４が容易に変形して、半田層１０に割れ２０が発生するのを防止できる。   In the internal electrode 9 shown in FIG. 6, the portion joined by the insulating substrate 2 and the solder layer 10 is composed of a knitted wire portion 24 that is more easily deformed than the plate-like portion 29. For this reason, when the temperature cycle is applied, it is possible to prevent the knitted wire portion 24 from being easily deformed and the crack 20 from being generated in the solder layer 10.

実施の形態３．
図７は、本発明の実施の形態３にかかるパワー半導体モジュールの、図１のＡに相当する部分の断面図である。Ａ以外の部分の構造は、図１と同じである（以下の実施の形態においても同じ）。 Embodiment 3 FIG.
FIG. 7 is a cross-sectional view of a portion corresponding to A in FIG. 1 of the power semiconductor module according to the third embodiment of the present invention. The structure of portions other than A is the same as in FIG. 1 (the same applies to the following embodiments).

本実施の形態３にかかるパワー半導体モジュールでは、内部電極９が、Ｕ字型に曲がったベント部１８を有する。ベント部１８の断面形状は、絶縁基板２の表面に垂直な方向に延びた２つの直線部の間を円弧部でつないだ構造となっている。   In the power semiconductor module according to the third embodiment, the internal electrode 9 has a vent portion 18 bent in a U shape. The cross-sectional shape of the vent portion 18 has a structure in which an arc portion connects two linear portions extending in a direction perpendicular to the surface of the insulating substrate 2.

このようなベント部１８を設けることにより、内部電極９が横方向（絶縁基板２の表面に平行な方向）に弾性を有するようになる。このため、温度サイクルが加わった場合に、ベント部１８が容易に変形して、半田層１０に割れ２０が発生するのを防止できる。特に、横方向の変形により発生する割れ２０の防止に効果的である。   By providing such a vent portion 18, the internal electrode 9 has elasticity in the lateral direction (direction parallel to the surface of the insulating substrate 2). For this reason, it is possible to prevent the bent portion 18 from being easily deformed and causing the crack 20 in the solder layer 10 when a temperature cycle is applied. In particular, it is effective in preventing cracks 20 caused by lateral deformation.

実施の形態４．
図８は、本発明の実施の形態４にかかるパワー半導体モジュールの、図１のＡに相当する部分の断面図である。 Embodiment 4 FIG.
FIG. 8 is a cross-sectional view of a portion corresponding to A in FIG. 1 of the power semiconductor module according to the fourth embodiment of the present invention.

本実施の形態４にかかるパワー半導体モジュールでは、内部電極９と金属配線層１２との、半田層１０を挟んで対向する領域にそれぞれ凸部２５、２６が設けられている。凸部２５と凸部２６は、図８の紙面に垂直な方向に延びた、断面が略矩形のストライプ形状からなる。凸部２５と凸部２６の位置は、図８の紙面に平行な方向に交互に配置されている。   In the power semiconductor module according to the fourth embodiment, convex portions 25 and 26 are provided in regions of the internal electrode 9 and the metal wiring layer 12 facing each other across the solder layer 10. The convex portions 25 and 26 are formed in a stripe shape extending in a direction perpendicular to the paper surface of FIG. 8 and having a substantially rectangular cross section. The positions of the convex portions 25 and the convex portions 26 are alternately arranged in a direction parallel to the paper surface of FIG.

かかる凸部２５、２６を設けることにより、半田層１０に金属配線層１２に沿った割れが発生した場合でも、半田層１０の内部に向かって割れが進行する距離（図８では、金属配線層１２の表面に沿った横方向の距離）が長くなるため、破断に至るまでの時間が長くなる。この結果、パワー半導体モジュールの製品寿命を長くすることができる。   By providing the convex portions 25 and 26, even when the solder layer 10 is cracked along the metal wiring layer 12, the distance at which the crack progresses toward the inside of the solder layer 10 (in FIG. 12), the time to break is increased. As a result, the product life of the power semiconductor module can be extended.

図９は、本実施の形態４にかかる他のパワー半導体モジュールの、図１のＡに相当する部分の断面図である。図９では、内部電極９と金属配線層１２のそれぞれに設けられた凸部２７、２８の断面が、略三角となっている。他は図８の構造と同様である。   FIG. 9 is a cross-sectional view of a portion corresponding to A in FIG. 1 of another power semiconductor module according to the fourth embodiment. In FIG. 9, the cross sections of the protrusions 27 and 28 provided on the internal electrode 9 and the metal wiring layer 12 are substantially triangular. Others are the same as the structure of FIG.

上述のように、かかる凸部２７、２８を設けることにより、半田層１０に金属配線層１２に沿った割れが発生した場合でも、半田層１０の内部に向かって割れが進行する距離が長くなり、破断に至るまでの時間が長くなる。この結果、パワー半導体モジュールの製品寿命を長くすることができる。   As described above, by providing the protrusions 27 and 28, even when a crack along the metal wiring layer 12 occurs in the solder layer 10, the distance that the crack progresses toward the inside of the solder layer 10 becomes long. , The time to break becomes longer. As a result, the product life of the power semiconductor module can be extended.

１ ベース板、２ 絶縁基板、３ 半導体素子、４ ワイヤ、５ シリコンゲル、６ ケース、７ 蓋、９ 内部電極、１０ 半田層、１２、１４ 金属配線層、１３ 絶縁体、１００ パワー半導体モジュール。   DESCRIPTION OF SYMBOLS 1 Base plate, 2 Insulating substrate, 3 Semiconductor element, 4 Wire, 5 Silicon gel, 6 Case, 7 Lid, 9 Internal electrode, 10 Solder layer, 12, 14 Metal wiring layer, 13 Insulator, 100 Power semiconductor module.

Claims (6)

絶縁板と該絶縁板の主表面に設けられた配線層とを含む絶縁基板と、
該配線層上に固定された半導体素子と、
該絶縁板の主表面に略平行な接合面を有し、該接合面が該配線層上に半田層で接続された内部電極とを含み、
該内部電極が、該半田層で覆われた該接合面に、略平行に配置された複数のストライプ状の上部突起部を有し、かつ該配線層が、該半田層で覆われた領域に、略平行に配置された複数のストライプ状の下部突起部を有することを特徴とするパワー半導体モジュール。 An insulating substrate including an insulating plate and a wiring layer provided on the main surface of the insulating plate;
A semiconductor element fixed on the wiring layer;
A bonding surface substantially parallel to the main surface of the insulating plate, the bonding surface including an internal electrode connected by a solder layer on the wiring layer;
The internal electrode has a plurality of stripe-shaped upper protrusions arranged substantially parallel to the joint surface covered with the solder layer, and the wiring layer is in a region covered with the solder layer. A power semiconductor module comprising a plurality of stripe-shaped lower protrusions arranged substantially in parallel. 隣接する２つの上記上部突起部の間に、上記下部突起部が配置されたことを特徴とする請求項１に記載のパワー半導体モジュール。   The power semiconductor module according to claim 1, wherein the lower protrusion is disposed between two adjacent upper protrusions. 上記上部突起部および上記下部突起部の断面形状が、ともに略矩形であることを特徴とする請求項１に記載のパワー半導体モジュール。   2. The power semiconductor module according to claim 1, wherein cross-sectional shapes of the upper protrusion and the lower protrusion are both substantially rectangular. 上記上部突起部および上記下部突起部の断面形状が、ともに略三角形であることを特徴とする請求項１に記載のパワー半導体モジュール。   2. The power semiconductor module according to claim 1, wherein cross-sectional shapes of the upper protrusion and the lower protrusion are both substantially triangular. 絶縁板と該絶縁板の主表面に設けられた配線層とを含む絶縁基板と、
該配線層上に固定された半導体素子と、
該配線層上に半田層で接続された内部電極とを含み、
該内部電極が、Ｕ字型に曲げられたベント部を有し、該ベント部の両端が該半田層で接続されたことを特徴とするパワー半導体モジュール。 An insulating substrate including an insulating plate and a wiring layer provided on the main surface of the insulating plate;
A semiconductor element fixed on the wiring layer;
An internal electrode connected with a solder layer on the wiring layer,
The power semiconductor module, wherein the internal electrode has a bent portion bent in a U-shape, and both ends of the bent portion are connected by the solder layer. 絶縁板と該絶縁板の主表面に設けられた配線層とを含む絶縁基板と、
該配線層上に固定された半導体素子と、
該配線層上に半田層で接続された内部電極とを含み、
該内部電極の端部が、細線を縒りあわせた縒り線部又は細線を編みあわせた編み線部からなり、該縒り線部又は該編み線部に、該半田層が接続されたことを特徴とするパワー半導体モジュール。 An insulating substrate including an insulating plate and a wiring layer provided on the main surface of the insulating plate;
A semiconductor element fixed on the wiring layer;
An internal electrode connected with a solder layer on the wiring layer,
The end of the internal electrode is composed of a twisted wire portion in which fine wires are twisted or a knitted wire portion in which fine wires are knitted, and the solder layer is connected to the twisted wire portion or the knitted wire portion. Power semiconductor module.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017147411A (en) * 2016-02-19 2017-08-24 株式会社村田製作所 module
CN112164689A (en) * 2020-08-25 2021-01-01 江苏长电科技股份有限公司 Air tightness packaging structure for preventing metal cover from shifting
JP2022048877A (en) * 2020-09-15 2022-03-28 株式会社東芝 Semiconductor device

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Publication number Priority date Publication date Assignee Title
JP2001036001A (en) * 1999-07-21 2001-02-09 Toyota Central Res & Dev Lab Inc Power semiconductor module
JP2004200539A (en) * 2002-12-20 2004-07-15 Toshiba Corp Component-connecting terminal and electronic device

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
JP2001036001A (en) * 1999-07-21 2001-02-09 Toyota Central Res & Dev Lab Inc Power semiconductor module
JP2004200539A (en) * 2002-12-20 2004-07-15 Toshiba Corp Component-connecting terminal and electronic device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017147411A (en) * 2016-02-19 2017-08-24 株式会社村田製作所 module
CN112164689A (en) * 2020-08-25 2021-01-01 江苏长电科技股份有限公司 Air tightness packaging structure for preventing metal cover from shifting
JP2022048877A (en) * 2020-09-15 2022-03-28 株式会社東芝 Semiconductor device
JP7438071B2 (en) 2020-09-15 2024-02-26 株式会社東芝 semiconductor equipment

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