JP2017118807A - Power conversion system, power module, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power conversion system, a power module, and a semiconductor device capable of achieving reduction in cost.SOLUTION: A power conversion system comprises: first coupling circuits (HCC1 and HCC2) each of which includes wiring between a controller CTLU and a high-side circuit HSU; and a second coupling circuit (LCC) that includes wiring between the controller CTLU and a low-side circuit LSU. Each first coupling circuit (HCC1, HCC2) comprises a diode DD1, DD2 whose anode is coupled with wiring from the controller CTLU and whose cathode is coupled with wiring from the high-side circuit HSU.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power conversion system, a power module, and a semiconductor device.

  Patent Document 1 discloses a method for estimating the lifetime of a power semiconductor element by providing diodes at two different locations in a power module and detecting temperature gradients at two locations based on the temperature characteristics of each diode. In Patent Document 2, an internal gate resistance is connected between a gate electrode of an IGBT chip and a gate terminal of an IGBT module including the chip, and the temperature characteristic of the internal gate resistance is used to detect the temperature of the IGBT module. The method to do is shown.

JP 2006-114575 A JP 2000-124781 A

  For example, in an inverter that converts a DC voltage into an AC voltage, power is supplied to a load from a connection terminal of a high-side transistor and a low-side transistor. A high-side circuit including a high-side transistor operates on the basis of the voltage at the connection terminal, but the voltage at the connection terminal varies depending on on / off of the high-side transistor and the low-side transistor. For this reason, for example, communication between a controller that operates on the basis of a fixed voltage and a high-side circuit that operates on the basis of a variable voltage is usually performed via an insulating element such as a photocoupler or a digital isolator. However, since such an insulating element is expensive, there is a risk of increasing the cost.

  Embodiments to be described later have been made in view of the above, and other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  A power conversion system according to an embodiment includes a controller that communicates with a high-side circuit and a low-side circuit, a first coupling circuit that includes wiring between the controller and the high-side circuit, and a wiring between the controller and the low-side circuit. Including a second coupling circuit. The high-side circuit includes a high-side switch that is coupled between the first power supply terminal and the load drive terminal and supplies power to the load via the load drive terminal, and a high-side driver that drives the high-side switch. . The low-side circuit includes a low-side switch that is coupled between the reference power supply terminal and the load drive terminal and supplies power to the load via the load drive terminal, and a low-side driver that drives the low-side switch. The first coupling circuit includes a diode having an anode coupled to the wiring from the controller and a cathode coupled to the wiring from the high side circuit.

  According to the embodiment, it is possible to realize cost reduction in the power conversion system.

In the power conversion system by Embodiment 1 of this invention, it is a circuit diagram which shows the schematic structural example of the principal part. FIG. 2 is a waveform diagram illustrating a schematic operation example of a main part in the power conversion system of FIG. 1. (A) And (b) is a supplementary figure of FIG. 2, (a) is a circuit diagram which extracted the communication path | route from a controller to a high side control circuit, (b) is from a high side control circuit. It is the circuit diagram which extracted the communication path | route to a controller. In the power conversion system by Embodiment 2 of this invention, it is a circuit diagram which shows the schematic structural example of the principal part. FIG. 5 is a plan view showing a schematic arrangement configuration example of each of a high-side switch and a low-side switch in FIG. 4. FIG. 5 is a waveform diagram illustrating a schematic operation example of a main part in the power conversion system of FIG. 4. (A) is sectional drawing and a top view which show the structural example of the diode in the temperature detection circuit in FIG. 4, (b) is a figure which shows an example of the proof pressure characteristic in the diode of (a). FIG. 10 is a circuit block diagram showing a schematic configuration example of a semiconductor device according to a third embodiment of the present invention. FIG. 9 is a plan view illustrating a schematic layout configuration example in the semiconductor device of FIG. 8. FIG. 10 is a plan view illustrating a layout configuration example obtained by extending FIG. 9. In the power module by Embodiment 3 of this invention, it is a top view which shows the schematic package structural example. It is the schematic which shows an example of the mounting form of the power module of FIG. In the power conversion system by Embodiment 4 of this invention, it is a circuit diagram which shows the schematic structural example of the principal part. FIG. 14 is a waveform diagram showing a schematic operation example of a main part in the power conversion system of FIG. 13. In the power conversion system used as the comparative example of this invention, it is a circuit diagram which shows the schematic structural example of the principal part. In the power conversion system used as the comparative example of this invention, it is a circuit diagram which shows the schematic structural example of the principal part. In the power conversion system used as the comparative example of this invention, it is a circuit diagram which shows the schematic structural example of the principal part. (A) And (b) is a wave form diagram which shows an example of the problem of the coupling circuit used as a premise in the power conversion system by Embodiment 4 of this invention. In the power conversion system by Embodiment 5 of this invention, it is a circuit diagram which shows the schematic structural example of the principal part. It is the schematic which shows an example of the operation timing of the temperature detection circuit of FIG. FIG. 20 is a schematic diagram illustrating a configuration example of a switch control circuit in FIG. 19.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In the embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (abbreviated as MOS transistor) is used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), but a non-oxide film is not excluded as a gate insulating film. Absent.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<< Schematic configuration of power conversion system >>
FIG. 1 is a circuit diagram showing a schematic configuration example of main parts in a power conversion system according to Embodiment 1 of the present invention. The power conversion system shown in FIG. 1 includes a controller CTLU, a high side circuit HSU, a low side circuit LSU, and coupling circuits HCC1, HCC2, and LCC. The coupling circuits HCC1 and HCC2 include a wiring between the controller CTLU and the high side circuit HSU, and the coupling circuit LCC includes a wiring between the controller CTLU and the low side circuit LSU.

  The high side circuit HSU includes a high side switch HSW and a high side control circuit HCT. The high side switch HSW is coupled between the input power supply terminal PN_VIN to which the input power supply voltage VIN is supplied with the reference power supply voltage GND as a reference and the load drive terminal PN_OUT, and supplies power to the load LD through the load drive terminal PN_OUT. Supply.

  Specifically, the high side switch HSW includes a high side transistor TRh and a free-wheeling diode FDh connected in parallel to the high side transistor TRh. The high side transistor TRh is not particularly limited, but is an IGBT (Insulated Gate Bipolar Transistor) or the like. The high side control circuit HCT includes a high side driver HDV that drives the high side switch HSW (specifically, the high side transistor TRh) to an on state or an off state via a high side switch signal HO. The high-side switch HSW is controlled and protected via this.

  The low side circuit LSU includes a low side switch LSW and a low side control circuit LCT. The low side switch LSW is coupled between the reference power supply terminal PN_GND to which the reference power supply voltage GND is supplied and the load drive terminal PN_OUT, and supplies power to the load LD through the load drive terminal PN_OUT. Specifically, the low-side switch LSW includes a low-side transistor TRl and a free-wheeling diode FDl connected in parallel to the low-side transistor TRl. The low side transistor TRl is not particularly limited but is an IGBT or the like.

  The low-side control circuit LCT includes a low-side driver LDV that drives the low-side switch LSW (specifically, the low-side transistor TRl) to an on state or an off state via a low-side switch signal LO, and via the low-side driver LDV. The low side switch LSW is controlled and protected. Here, as shown in FIG. 1, in some cases, a diode Ddes may be provided between the load drive terminal PN_OUT and the low-side control circuit LCT. The low-side control circuit LCT monitors the emitter-collector voltage of the low-side transistor TRl via the diode Ddes, and when the short-circuit of the load LD is detected based on the monitoring result, the low-side switch LSW is turned off. .

  The controller CTLU controls the high side circuit HSU by communicating with the high side circuit HSU via the coupling circuits HCC1 and HCC2. In the example of FIG. 1, the coupling circuit HCC1 transmits the signal DOh from the transmission circuit TXh of the high side control circuit HCT to the reception circuit RXc of the controller CTLU. On the contrary, the coupling circuit HCC2 transmits the signal DOc from the transmission circuit TXc of the controller CTLU to the reception circuit RXh of the high side control circuit HCT. The controller CTLU controls the low side circuit LSU by communicating with the low side circuit LSU via the coupling circuit LCC.

  In such a configuration, the low side circuit LSU operates with a power supply voltage (for example, 15 V) VCC with reference to the reference power supply voltage GND. In this example, the controller CTLU also operates at the power supply voltage VCC with reference to the reference power supply voltage GND. On the other hand, the high side circuit HSU operates with the boot power supply voltage VB with reference to the floating voltage VS coupled to the load drive terminal PN_OUT. The boot power supply voltage VB is generated by, for example, a bootstrap diode Db and a bootstrap capacitor Cb that are sequentially connected from the power supply voltage VCC toward the load drive terminal PN_OUT.

  For example, in the period [1] when the high side switch HSW is off and the low side switch LSW is on, the floating voltage VS is the reference power supply voltage GND, and the bootstrap diode Db is forward biased. As a result, the bootstrap capacitor Cb is charged with the power supply voltage VCC, and the boot power supply voltage VB becomes equal to the power supply voltage VCC. Strictly speaking, a voltage drop in the forward direction of the diode occurs, but in the present specification, such a voltage drop is ignored unless otherwise specified. Further, the voltage drop due to the on-resistance of each transistor is also ignored.

  On the other hand, in the period [2] in which the high-side switch HSW is on and the low-side switch LSW is off, the floating voltage VS is the input power supply voltage VIN (for example, 1200 V), and the boot power supply voltage VB is the boot in the period [1]. It becomes “VIN + VCC” by the charging voltage of the strap capacitor Cb, and the bootstrap diode Db is reverse-biased. The high side circuit HSU operates at the power supply voltage VCC supplied via the bootstrap diode Db in the period [1], and operates at the charging voltage of the bootstrap capacitor Cb (that is, the power supply voltage VCC) in the period [2]. To do.

《Comparative communication method》
FIG. 15 is a circuit diagram illustrating a schematic configuration example of a main part in a power conversion system as a comparative example of the present invention. As described above, the controller CTLU operates at the power supply voltage VCC with reference to the reference power supply voltage GND, while the high side circuit HSU is “VIN + VCC” with the input power supply voltage VIN as the reference in the period [2]. Operate. For this reason, when communication is performed between the controller CTLU and the high-side circuit HSU, for example, an insulating element as shown in FIG. 15 is required for signal level matching and prevention of element destruction.

  The power conversion system shown in FIG. 15 includes photocouplers CPL1 'and CPL2' that transmit signals by causing a photodiode to emit light and causing a current to flow through the phototransistor, for example, as an insulating element. The photocoupler CPL1 ′ transmits a signal, which is transmitted from the transmission circuit TXh ′ of the high side control circuit HCT, between the boot power supply voltage VB and the floating voltage VS, between the power supply voltage VCC and the reference power supply voltage GND. The signal is converted to a transition signal and transmitted to the receiving circuit RXc ′ of the controller CTLU. On the other hand, the photocoupler CPL2 ′ transmits a signal, which is transmitted from the transmission circuit TXc ′ of the controller CTLU, between the power supply voltage VCC and the reference power supply voltage GND, between the boot power supply voltage VB and the floating voltage VS. The signal is converted to a signal that changes in step (1) and transmitted to the receiving circuit RXh ′ of the high-side control circuit HCT.

  In this example, a photocoupler is used as the insulating element, but a digital isolator or the like that transmits a signal by magnetic coupling of two coils may be used. However, insulating elements such as photocouplers and digital isolators are usually expensive and may increase the cost of the power conversion system. Further, when such expensive parts are required, it may be difficult to increase the communication path between the controller CTLU and the high side circuit HSU, for example.

<< Communication method of the first embodiment >>
Therefore, in the power conversion system according to the first embodiment, as shown in FIG. 1, the coupling circuits HCC1 and HCC2 have their anodes coupled to the wiring from the controller CTLU and the cathodes to the wiring from the high side circuit HSU. Diodes DD1 and DD2 are coupled. Each of the diodes DD1 and DD2 is, for example, a high breakdown voltage diode having a breakdown voltage according to the input power supply voltage VIN (for example, 1200 V).

  Further, in the example of FIG. 1, the coupling circuit HCC1 includes a current source IS1 coupled between the power supply voltage VCC and the anode of the diode DD1 in addition to the diode DD1. The current source IS1 allows a small forward current to flow through the diode DD1. Note that the current source IS1 may be replaced with a high-resistance resistance element or the like. In addition to the diode DD2, the coupling circuit HCC2 includes a pull-down switch DS coupled between the cathode of the diode DD2 and the load drive terminal PN_OUT. The pull-down switch DS is controlled to be turned on / off by, for example, a switch signal Sds from the driver SDV of the high side control circuit HCT.

  FIG. 2 is a waveform diagram showing a schematic operation example of the main part in the power conversion system of FIG. 1. 3A and 3B are supplementary diagrams of FIG. 2, and FIG. 3A is a circuit diagram in which a communication path from the controller to the high-side control circuit is extracted, and FIG. ) Is a circuit diagram in which a communication path from the high-side control circuit to the controller is extracted.

  In FIG. 2, a high side switch signal HO and a low side switch signal LO are signals in which the ‘H’ level and the ‘L’ level transition in a complementary manner. The “L” level voltage of the high side switch signal HO is the floating voltage VS, and the “H” level voltage is a voltage “VS + VCC” obtained by adding the power supply voltage VCC to the floating voltage VS. The 'L' level voltage of the low side switch signal LO is the reference power supply voltage GND, and the 'H' level voltage is the power supply voltage VCC. The high side switch signal HO and the low side switch signal LO are provided with a dead time period so that a period during which both are turned on does not occur.

  At time t1, the floating voltage VS decreases with the transition of the high side switch signal HO to the ‘L’ level (the high side transistor TRh is off). When the floating voltage VS is lower than the reference power supply voltage GND, the current path of the load LD such as a motor is switched to the free wheel diode FDl of the low side switch LSW. After that, when the low side switch signal LO transits to the “H” level (low side transistor TRl is turned on) at time t2 through a dead time period, the floating voltage VS becomes the reference power supply voltage GND.

  Thereafter, at time t3, the floating voltage VS rises with the transition of the low-side switch signal LO to the ‘L’ level (the low-side transistor TRl is turned off). When the floating voltage VS rises above the input power supply voltage VIN, the current path of the load LD is switched to the free wheel diode FDh of the high side switch HSW. After that, when the high side switch signal HO transitions to the ‘H’ level (high side transistor TRh is on) at time t4 after a dead time period, the floating voltage VS becomes the input power supply voltage VIN. Thereafter, at times t5 to t8, operations similar to those at times t1 to t4 are performed.

  With such a transition of the floating voltage VS, as shown in FIGS. 3A and 3B, the reception circuit RXh and the transmission circuit TXh of the high side control circuit HCT operate with reference to the reference power supply voltage GND. The period (time t2 to t3 in FIG. 2) and the period operating from the input power supply voltage VIN (time t4 to t5 in FIG. 2) alternately occur. In the present specification, the former period (time t2 to t3) is referred to as a low side period, and the latter period (time t4 to t5) is referred to as a high side period. Here, it is assumed that signal transmission is performed from the transmission circuit TXc of the controller CTLU to the reception circuit RXh of the high side control circuit HCT.

  First, as an initial state of the low side period (time t2 to t3), the voltage of the reception node Nih of the reception circuit RXh is assumed to be equal to the floating voltage VS (here, the reference power supply voltage GND). In this case, the signal DOc of the “H” level (the level of the power supply voltage VCC) from the transmission circuit TXc of the controller CTLU is transmitted via the forward-biased diode DD2, and the “H” level (the power supply voltage VCC) is received by the reception circuit RXh. ) Level signal DIh. On the other hand, the ‘L’ level (reference power supply voltage GND level) signal DOc from the transmission circuit TXc is also received as the ‘L’ level (reference power supply voltage GND level) signal DIh by the reception circuit RXh.

  Thereafter, when the transition is made to the high side period (time t4 to t5), the voltage of the reception node Nih of the reception circuit RXh follows the transition of the floating voltage VS along with the parasitic capacitance Cp with the floating voltage VS. To do. At this time, when the voltage of the reception node Nih exceeds the voltage of the transmission node Noc of the transmission circuit TXc, the diode DD2 is reverse-biased, and the reception node Nih and the transmission node Noc are insulated. Since the voltage of the transmission node Noc does not exceed the power supply voltage VCC, element destruction in the transmission circuit TXc does not occur.

  As described above, in the first embodiment, signal transmission from the transmission circuit TXc to the reception circuit RXh via the diode DD2 is performed in the low side period (time t2 to t3), and in the high side period (time t4 to t5). Not done. After that, the transition is made again to the low side period (time t6 to t7). Here, if the signal DIh of the reception node Nih is at the “H” level (the level of the power supply voltage VCC) in the immediately preceding low side period (time t2 to t3), the low side period (time t6 to t7). ), The receiving node Nih may still maintain the “H” level. In this case, since the diode DD2 is reverse-biased, it cannot transmit the signal DOc of the “L” level (level of the reference power supply voltage GND) from the transmission circuit TXc.

  Therefore, as shown in FIG. 2, as a pre-processing when signal transmission from the transmission circuit TXc to the reception circuit RXh in the low-side period (time t2 to t3, t6 to t7), the pull-down switch DS is set using the switch signal Sds. Controlled on. In the example of FIG. 2, the high-side control circuit HCT controls the pull-down switch DS to be on during the period from time t1 to t2 and the period from time t5 to t6. As a result, as described above, as the initial state of the low side period (time t2 to t3, t6 to t7), the voltage of the reception node Nih of the reception circuit RXh can be made equal to the floating voltage VS (reference power supply voltage GND). Signal transmission can be performed without any problem. Note that the period during which the pull-down switch DS is controlled to be on is not particularly limited to the example in FIG. 2, and may be any period from time t3 to t6, or from time t6. Short periods of time may be included.

  Next, it is assumed that signal transmission is performed from the transmission circuit TXh of the high side control circuit HCT to the reception circuit RXc of the controller CTLU. In FIG. 3B, the transmission circuit TXh outputs the signal DOh of the “H” level (the level of the power supply voltage VCC) or the “L” level (the level of the reference power supply voltage GND) in the low side period (time t2 to t3). Send. At this time, if the voltage of the reception node Nic of the reception circuit RXc is the reference power supply voltage GND and the signal DOh is at the “H” level, the diode DD1 is reverse-biased so that the signal DOh can be transmitted. Can not.

  Therefore, in FIG. 3B, the reception node Nic is coupled to the power supply voltage VCC via the current source IS1 that flows a minute current. The current source IS1 has a resistance value sufficiently higher than the output resistance of the transmission circuit TXh. As a result, when the signal DOh is at the “H” level, the receiving circuit RXc can receive it as the signal DIc at the “H” level. The 'L' level signal DOh is transmitted to the reception node Nic via the forward biased diode DD1, and the reception circuit RXc can receive the signal as the 'L' level signal DIc. As described above, the current source IS1 may be a high-resistance resistive element or the like.

  Then, the transition is made to the high side period (time t4 to t5). Accordingly, the voltage of the transmission node Noh changes following the change of the floating voltage VS by the same parasitic capacitance Cp as in FIG. 3A or the transmission circuit TXh during the output operation. At this time, when the voltage of the transmission node Noh exceeds the voltage of the reception node Nic (power supply voltage VCC), the diode DD1 is reverse-biased, and the transmission node Noh and the reception node Nic are insulated. Since the voltage of the reception node Nic is set to the power supply voltage VCC, no element destruction occurs in the reception circuit RXc.

  Thereafter, the transition is made again to the low side period (time t6 to t7), and the same operation as in the low side period (time t2 to t3) is performed. Thus, in the first embodiment, signal transmission via the diode DD1 from the transmission circuit TXh to the reception circuit RXc is also performed in the low side period and not in the high side period.

  As described above, in the power conversion system according to the first embodiment, communication between the controller CTLU and the high side circuit HSU is performed using the diodes DD1 and DD2. For this reason, communication of the high side circuit HSU can be performed without using an expensive insulating element as shown in FIG. 15, and a reduction in cost can be realized typically. As a result, the communication path between the controller CTLU and the high side circuit HSU can be easily increased.

  Here, for simplification of explanation, communication of a digital signal that transitions between the “H” level and the “L” level is taken as an example. However, as is apparent from the configuration and operation described above, the communication system of the first embodiment is similarly applied to communication of an analog signal having an arbitrary value between the “H” level and the “L” level. Is possible. Specific examples of analog signal communication will be described later in the second embodiment.

(Embodiment 2)
<< Schematic configuration of power conversion system (application example [1]) >>
FIG. 4 is a circuit diagram showing a schematic configuration example of the main part in the power conversion system according to the second embodiment of the present invention. 4 includes an inverter IVU including three-phase (u-phase, v-phase, w-phase) high-side switches HSWu, HSWv, HSWw and low-side switches LSWu, LSWv, LSWw, and various types of inverters IVU. And a control circuit. The inverter IVU is supplied with an input power supply voltage VIN (for example, 600 V) with reference to the reference power supply voltage GND. The inverter IVU generates a load LD such as a motor by generating three-phase AC voltages (floating voltages) VSu, VSv, VSw at three-phase load drive terminals PN_OUTu, PN_OUTv, PN_OUTw by, for example, PWM (Pulse Width Modulation) control. To supply power.

  Among the various control circuits, there are high-side control circuits HCTu, HCTv, HCTw for controlling and protecting the three-phase high-side switches HSWu, HSWv, HSWw, and three-phase low-side switches LSWu, LSWv, LSWw. -Low side control circuits LCTu, LCTv, LCTw for protection and the like are included. Further, among the various control circuits, there are a controller CTLU, a photocoupler CPL10 serving as an insulating element, a three-phase high-side temperature detection circuit TChu, TChv, TChw, and a three-phase low-side temperature detection circuit TClu, TClv. , TClw.

  The controller CTLU is not particularly limited, but includes a microcontroller (MCU: Micro Control Unit) or the like. The controller CTLU is supplied with a power supply voltage VDD (for example, 5 V) and a reference power supply voltage GND, and includes analog-digital converters ADC1 and ADC2, and a protection circuit PRCc that is mounted by processor program processing or the like. The controller CTLU transmits an on / off signal (for example, a PWM signal) of the high-side switch HSWu (high-side transistor TRhu) from the IO terminal IO1, and on / off of the low-side switch LSWu (low-side transistor TRlu) from the IO terminal IO2. A signal (for example, a PWM signal) is transmitted.

  The low side control circuit LCTu drives the low side transistor TRlu via an internal low side driver (not shown) in response to an on / off signal of the low side switch LSWu from the controller CTLU. Here, the low side control circuit LCTu operates with a power supply voltage VCC of, for example, 15V. Therefore, more specifically, for example, the low-side control circuit LCTu includes a level shift circuit that converts a signal of a power supply voltage VDD (for example, 5V) into a signal of a power supply power supply VCC (for example, 15V). Such voltage level conversion can be realized by, for example, a general level shift circuit including elements having a withstand voltage corresponding to the power supply voltage VCC.

  On the other hand, an insulating element is required to transmit an on / off signal from the controller CTLU to the high-side control circuit HCTi. That is, when the communication method described in Embodiment 1 is used, the communication period is limited, and thus it is not suitable for transmission of on / off signals. Therefore, the photocoupler CPL10 sets the voltage level of the output signal of the controller CTLU (power supply voltage VDD−reference power supply voltage GND level) to the voltage level of the input signal of the high side control circuit HCtu (boot power supply voltage VB−floating voltage VSu). Level). Although illustration is omitted, transmission of on / off signals from the controller CTLU to the v-phase control circuits (HCTv, LCTv) and the w-phase control circuits (HCTw, LCTw) is the same as in the u-phase. Done.

  The high side switch HSWu is formed on the same semiconductor chip as the high side switch HSWu (specifically, for example, the high side transistor TRhu), and includes a temperature detection diode TDhu that detects the temperature of the high side switch HSWu. Similarly, the high side switches HSWv and HSWw also include temperature detection diodes TDhv and TDhw, respectively. The low side switch LSWu is formed on the same semiconductor chip as the low side switch LSWu (specifically, for example, the low side transistor TRlu), and includes a temperature detection diode TDlu that detects the temperature of the low side switch LSWu. Similarly, the low side switches LSWv and LSWw also include temperature detection diodes TDlv and TDlw, respectively.

  FIG. 5 is a plan view showing a schematic arrangement configuration example of each of the high-side switch and the low-side switch in FIG. In FIG. 5, the high side switch HSW is composed of two semiconductor chips CHP1 and CHP2. In the semiconductor chip CHP1, a high side transistor TRh and a temperature detection diode TDh are formed. In the semiconductor chip CHP2, for example, a reflux diode FDh such as FRD (Fast Recovery Diode) is formed.

  In the example of FIG. 5, the high-side transistor TRh is composed of an IGBT, and an emitter electrode EP and a gate electrode GP are formed on the main surface of the semiconductor chip CHP1, and a collector electrode is formed on the back surface (not shown) of the semiconductor chip CHP1. CP is formed. The temperature detection diode TDh is configured by, for example, forming a pn junction diffusion layer or the like in a region close to the IGBT on the main surface side of the semiconductor chip CHP1. On the main surface of the semiconductor chip CHP1, an anode electrode AP coupled to the p-type diffusion layer and a cathode electrode KP coupled to the n-type diffusion layer are formed. Here, the high side switch HSW has been described as an example, but the same applies to the low side switch LSW.

  In FIG. 4, the temperature detection circuit TChu is a circuit corresponding to the coupling circuit HCC1 of FIG. The temperature detection circuit TChu includes two diodes DD1a and DD1b, two current sources IS1a and IS1b, and a differential amplifier circuit AMP1. Diode DD1a has a cathode coupled to the anode of temperature detection diode TDhu, and diode DD1b has a cathode coupled to the cathode of temperature detection diode TDhu. The cathode of the temperature detection diode TDhu is also coupled to the load drive terminal PN_OUTu (floating voltage VSu).

  Current source IS1a is coupled between power supply voltage VDD and the anode of diode DD1a, and allows a forward current to flow through temperature detection diode TDhu via diode DD1a. Current source IS1b is coupled between power supply voltage VDD and the anode of diode DD1b, and allows a forward current to flow through diode DD1b. The differential amplifier circuit AMP1 detects a differential voltage between the anode of the diode DD1a and the anode of the diode DD1b, and transmits the detection result to the analog-digital converter ADC1 of the controller CTLU. Although illustration is omitted, details of the temperature detection circuits TChv and TChw are the same as those of the temperature detection circuit TChu.

  On the other hand, the temperature detection circuit TClu is a circuit corresponding to the coupling circuit LCC of FIG. The temperature detection circuit TClu includes a current source IS2 and a differential amplifier circuit AMP2. Current source IS2 is coupled between power supply voltage VDD and the anode of temperature detection diode TDlu, and allows a forward current to flow through temperature detection diode TDlu. The cathode of temperature detection diode TDlu is coupled to reference power supply terminal PN_GND (reference power supply voltage GND). The differential circuit AMP2 detects the difference voltage between the anode and the cathode of the temperature detection diode TDlu, and transmits the detection result to the analog-digital converter ADC2 of the controller CTLU. Although illustration is omitted, the details of the temperature detection circuits TClv and TClw are the same as those of the temperature detection circuit TClu.

<< Schematic operation of power conversion system (application example [1]) >>
FIG. 6 is a waveform diagram showing a schematic operation example of the main part in the power conversion system of FIG. 4. Here, the operation of the u phase in FIG. 4 will be described as an example, but the same applies to the v phase and the w phase. In the period T1 in FIG. 6, the low-side switch signal LOu serving as the gate input of the low-side transistor TRlu is at the “H” level, and the high-side switch signal HOu serving as the gate input to the high-side transistor TRhu is at the “L” level. It is. This period T1 is the low side period described in the first embodiment. In the period T1, the current from the current source IS1a flows to the temperature detection diode TDhu via the forward biased diode DD1a, and the current from the current source IS1b flows to the forward biased diode DD1b.

  At this time, the temperature detection diode TDhu generates a forward voltage that depends on temperature (specifically, has a negative temperature characteristic), and the anode of the temperature detection diode TDhu has the forward voltage as a reference with respect to the floating voltage VSu. A temperature voltage signal TOHu corresponding to the direction voltage is generated. The current values from the current sources IS1a and IS1b are the same value and are not particularly limited, but are, for example, values smaller than 1 mA. The differential amplifier circuit AMP1 detects the forward voltage of the temperature detection diode TDhu through the diodes DD1a and DD1b during the low side period.

  Specifically, a voltage value obtained by adding the forward voltage of the diode DD1a to the temperature voltage signal TOHu and a forward voltage of the diode DD2a (the same value as the diode DD1a) are added to the floating voltage VSu to the differential amplifier circuit AMP1. Voltage value is input. The differential amplifier circuit AMP1 differentially amplifies the input voltage and transmits a temperature voltage signal TIHu that is an amplification result to the controller CTLU. The controller CTLU converts the temperature voltage signal TIHu into a digital value by the analog-digital converter ADC1, and compares it with a predetermined determination voltage Vjdg using the protection circuit PRCc. In the period T1, since the voltage level of the temperature voltage signal TIHu is higher than the determination voltage Vjdg, the protection circuit PRCc determines that the temperature is normal.

  In the period T2, the low side switch signal LOu is at the ‘L’ level, and the high side switch signal HOu is at the ‘H’ level. This period T2 is the high side period described in the first embodiment. In the period T2, since the diodes DD1a and DD1b are reverse-biased, the temperature detection by the temperature detection diode TDhu is not performed.

  Next, in the period T3, the low side period starts again. In the example of FIG. 6, in the period T3, the temperature detection diode TDhu is in an abnormally high temperature state, and accordingly, the voltage level of the temperature voltage signal TIHu is lower than the determination voltage Vjdg. As a result, the protection circuit PRCc determines that the temperature is abnormal, and performs a protection operation that sets the high-side switch signal HOu that is originally set to the “H” level to the “L” level, for example, via the IO terminal IO1 in the period T4. To do.

  As a result, no current flows through the high side transistor TRhu, and the temperature detection diode TDhu approaches the normal temperature. In the period T5, the controller CTLU performs the operation in the low side period again, and confirms that the temperature detection diode TDhu has returned to the normal temperature. In response to this, the controller CTLU returns to normal operation. Although not particularly limited, the switching frequency fsw of the low side switch signal LOu and the high side switch signal HOu is 10 kHz or the like.

<Structure of high voltage diode>
7A is a cross-sectional view and a plan view showing an example of the structure of the diode in the temperature detection circuit in FIG. 4, and FIG. 7B shows an example of the withstand voltage characteristic of the diode in FIG. 7A. FIG. FIG. 7A shows a plan view of the diode and a cross-sectional view between AA ′ in the plan view. A diode DD shown in FIG. 7A is formed of a parasitic diode of a MOS transistor.

Specifically, in FIG. 7A, a drift layer LDR serving as an n ⁻ type epitaxial layer is formed on a p ⁻ type semiconductor substrate SUB. The drift layer LDR is separated by a p-type diffusion layer DF2 extending from the main surface (in other words, an element formation surface) side so as to be connected to the semiconductor substrate SUB, and a p-type separation layer IDF. On the main surface side of the p-type diffusion layer DF2, a p ⁺ -type diffusion layer DF1 having an impurity concentration higher than that of the p-type is disposed. Further, on the main surface side of the diffusion layer DF2, an n ⁺ type source diffusion layer SO having an impurity concentration higher than that of the n ⁻ type is disposed in a region between the diffusion layer DF1 and the drift layer LDR. Diffusion layer DF1 and source diffusion layer SO are coupled to anode electrode AE made of a contact layer or a metal layer.

  Between the source diffusion layer SO and the drift layer LDR, a gate layer GT made of polysilicon or the like is disposed on the diffusion layer DF2 via a gate insulating film GOX. A region immediately below the gate insulating film GOX between the source diffusion layer SO and the drift layer LDR becomes a channel region. Gate layer GT is coupled to a gate electrode GE made of a contact layer or a metal layer. The gate electrode GE is coupled to the anode electrode AE.

On the main surface side of the drift layer LDR and closer to the isolation layer IDF, an n ⁺ -type drain diffusion layer DR is disposed. The drain diffusion layer DR is coupled to the cathode electrode KE made of a contact layer or a metal layer. An insulating film ISL is formed on the drift layer LDR, and a field plate FP made of polysilicon or the like is disposed on the insulating film ISL. On a semiconductor substrate SUB, the portion located under the drain diffusion layer DR, ^{n +} -type buried layer BDF1 is disposed on the side facing the buried layer BDF1 across the separation layer IDF also, ^{n +} -type A buried layer BDF2 is disposed.

7A shows a structure in which the gate and the source are short-circuited in the MOS transistor having the source diffusion layer SO as the source and the drift layer LDR and the drain diffusion layer DR as the drain. As a result, the MOS transistor is always in an off state, the p ⁺ type diffusion layer DF1 and the p type diffusion layer DF2 are used as anodes, the n ⁻ type drift layer LDR and the n ⁺ type drain diffusion layer DR are used as cathodes. Function as a parasitic diode (or body diode).

  Further, the MOS transistor (parasitic diode) has a high breakdown voltage by including the drift layer LDR. Although not shown, the field plate FP has one end near the anode electrode AE coupled to the anode electrode AE and one end near the cathode electrode KE coupled to the cathode electrode KE. It is one line that connects the anode electrodes AE while being folded back. As a result, the voltage of the field plate FP gradually decreases from the side close to the cathode electrode KE toward the side close to the anode electrode AE. By providing such a voltage gradient, the spread of the depletion layer formed in the drift layer LDR can be made uniform.

  The diode DD shown in FIG. 7A has a breakdown voltage that exceeds the operation guarantee voltage of the inverter IVU (for example, the input power supply voltage VIN such as 600V), as shown in FIG. 7B. As shown in FIG. 7B, the diode DD is particularly limited to the structure example shown in FIG. 7A as long as it has a breakdown voltage exceeding the operation guarantee voltage of the inverter IVU. Instead, general-purpose discrete components can be used.

<< Main effects of the second embodiment >>
16 and 17 are circuit diagrams showing schematic configuration examples of main parts in a power conversion system as a comparative example of the present invention. The power conversion system shown in FIG. 16 differs from the configuration example of FIG. 4 in the circuit system of the high-side temperature detection circuits TChu ′, TChv ′, and TChw ′. For example, the temperature detection circuit TChu ′ includes a photocoupler CPL1 ′, and transmits the temperature voltage signal TOHu from the temperature detection diode TDhu to the controller CTLU via the photocoupler CPL1 ′. When such a method is used, it is necessary to provide an expensive insulating element such as a photocoupler in each of the temperature detection circuits TChu ′, TChv ′, and TChw ′. Therefore, as described in the first embodiment, the cost increases. There is a risk of inviting.

  On the other hand, in the power conversion system shown in FIG. 17, the high side switches HSWu ′, HSWv ′, HSWw ′, the low side switches LSWu ′, LSWv ′, LSWw ′, and the temperature detection circuit TChu are compared with the configuration example of FIG. ", TChv", TChw ", TClu", TClv ", TClw" have different configurations. The temperature detection circuit of each high-side switch and each low-side switch does not include a temperature detection diode, and instead, each temperature detection circuit includes a thermistor.

  For example, the u-phase high-side temperature detection circuit TChu ″ includes the thermistor THhu and transmits a temperature detection signal from the thermistor THhu to the controller CTLU. Similarly, the u-phase low-side temperature detection circuit TClu ″ includes the thermistor THlu. And a temperature detection signal from the thermistor THlu is transmitted to the controller CTLU. The thermistor THhu is composed of parts different from the semiconductor chip (CHP1 in FIG. 5) of the high-side transistor TRhu, and is disposed in the vicinity of the semiconductor chip, for example. Similarly, the thermistor THlu is composed of parts different from the semiconductor chip of the low-side transistor TRlu, and is disposed, for example, close to the semiconductor chip.

  When such a method is used, the thermistor THhu is provided outside the high-side transistor TRhu, and thus can operate with a power supply voltage (for example, the power supply voltage VDD and the reference power supply voltage GND) different from that of the high-side transistor TRhu. It becomes. As a result, an insulating element as in the case of FIG. 16 becomes unnecessary, and the cost can be reduced. However, since the thermistor THhu and the high-side transistor TRh are separate components, the temperature detection result by the thermistor THhu is different from the actual temperature of the high-side transistor TRh, and the responsiveness to a transient temperature change is also low. Become. In such a case, for example, it is necessary to ensure an excessive margin for heat radiation design or the like.

  Therefore, when the method of the second embodiment is used, the problems described with reference to FIGS. 16 and 17 can be solved, and temperature detection can be realized at low cost and with sufficient accuracy. Specifically, the cost reduction can be obtained, for example, because the temperature detection result can be transmitted via an inexpensive diode instead of an expensive insulating element, and an excessive margin in heat dissipation design can be eliminated.

(Embodiment 3)
<< Schematic Configuration and Operation of Driver IC (Integrated Circuit) >>
FIG. 8 is a circuit block diagram showing a schematic configuration example of the semiconductor device according to the third embodiment of the present invention. A driver IC (semiconductor device) DVIC1 shown in FIG. 8 includes, for example, a high-side control circuit (HCtu), a low-side control circuit (LCtu), and a temperature detection circuit (TChu, TClu) for one phase (for example, u phase) in FIG. Is configured to be mounted on one semiconductor chip.

  The driver IC (DVIC1) is composed of one semiconductor chip, and includes a plurality of pads (terminals) PD, a signal processing circuit LGC, a bootstrap circuit BSC, a level shift circuit LSC, and a high side control circuit HCT. The low side control circuit LCT and the temperature detection circuits TCh and TCl are provided. Here, a configuration example including a high-side switch HSW, a low-side switch LSW, a bootstrap capacitor Cb, and a load LD provided outside the driver IC (DVIC1) is shown.

  The high side switch HSW is coupled between the input power supply terminal PN_VIN and the load drive terminal PN_OUT, and the low side switch LSW is coupled between the load drive terminal PN_OUT and the reference power supply terminal PN_GND. The input power supply terminal PN_VIN is supplied with an input power supply voltage VIN of 600 V, for example, using the reference power supply voltage GND of the reference power supply terminal PN_GND as a reference (0 V). The load drive terminal PN_OUT is coupled to the floating voltage VS, and the floating voltage VS changes between the reference power supply voltage GND and the input power supply voltage VIN as described above.

  In the driver IC (DVIC1), the pad PD (VCC) is a power supply terminal to which the power supply voltage VCC is supplied. The power supply voltage VCC is 15 V, for example, with reference to the reference power supply voltage GND. The pad PD (HIN) is a terminal that receives a high-side on / off signal HIN from a controller CTLU (not shown). The pad PD (TIH) is a terminal that transmits the temperature voltage signal TIH from the temperature detection circuit TCh to the controller CTLU. The pad PD (LIN) is a terminal that receives a low-side on / off signal LIN from the controller CTLU. The pad PD (TIL) is a terminal that transmits the temperature voltage signal TIL from the temperature detection circuit TCl to the controller CTLU.

  The pad PD (VB) is a power supply terminal to which the boot power supply voltage VB is supplied. As described in FIG. 1, the boot power supply voltage VB is a voltage obtained by adding the power supply voltage VCC to the floating voltage VS. The pad PD (HO) is a terminal that transmits a high-side switch signal HO to the high-side switch HSW. Pad PD (VS) is a load drive terminal coupled to floating voltage VS. Bootstrap capacitor CB is coupled between pad PD (VB) and pad PD (VS).

  The pad PD (TOH) is a terminal that receives the temperature voltage signal TOH from the temperature detection diode TDh of the high side switch HSW. The pad PD (LO) is a terminal that transmits a low side switch signal LO to the low side switch LSW. The pad PD (GND) is a reference power supply terminal to which a reference power supply voltage GND is supplied. The pad PD (TOL) is a terminal that receives the temperature voltage signal TOL from the temperature detection diode TDl of the low-side switch LSW.

  The signal processing circuit LGC includes a high side input buffer IBFh, a low side input buffer IBF1, a pulse generation circuit PGEN, and a delay circuit DLY. The high side input buffer IBFh converts the high side on / off signal HIN received by the pad PD (HIN) into a signal of the power supply voltage VCC level, and outputs the signal to the pulse generation circuit PGEN. The low-side input buffer IBF1 converts the low-side on / off signal LIN received by the pad PD (LIN) into a signal at the power supply voltage VCC level, and outputs the signal to the delay circuit DLY. Each of the input buffers IBFh and IBFl includes, for example, a Schmitt trigger circuit or the like for removing input noise.

  The pulse generation circuit PGEN and the delay circuit DLY operate at the power supply voltage VCC with reference to the reference power supply voltage GND. The pulse generation circuit PGEN receives the output signal of the high side input buffer IBFh, generates the set signal ST on one of the rising edge and the falling edge, and generates the reset signal RT on the other side. Each of the set signal ST and the reset signal RT is, for example, a one-shot pulse signal. The delay circuit DLY adds a delay corresponding to a dead time period to the output signal of the low-side input buffer IBF1, and outputs a delayed low-side on / off signal LINd.

  The high side control circuit HCT includes a high side driver HDV, an SR latch circuit SRLT, and a high side low voltage detection circuit UVLOh, which operate at the boot power supply voltage VB with reference to the floating voltage VS. The high side driver HDV is composed of a CMOS inverter or the like that receives the output signal (Q) of the SR latch circuit SRLT, and drives the high side transistor TRh by transmitting the high side switch signal HO to the pad PD (HO). To do.

  The SR latch circuit SRLT controls the high side switch signal HO via the high side driver HDV according to the set input (S) and the reset input (R). Specifically, the SR latch circuit SRLT controls the high side switch signal HO to the boot power supply voltage VB level according to the set input (S), and sets the high side switch signal HO to the floating voltage according to the reset input (R). Control to VS level. The high side low voltage detection circuit UVLOh performs a reset input (R) to the SR latch circuit SRLT when the value of the boot power supply voltage VB with respect to the floating voltage VS does not reach a predetermined voltage value. As a result, the high side transistor TRh is fixed off until the value of the boot power supply voltage VB reaches a predetermined voltage value.

  The level shift circuit LSC includes two NMOS transistors (referred to as level shift MOSs) MN1 and MN2 and two resistors R1 and R2. In the level shift MOSs (MN1, MN2), the sources are coupled to the reference power supply voltage GND, and the drains are coupled to the boot power supply voltage VB via resistors R1 and R2, respectively. Thus, since the boot power supply voltage VB is applied between the source and drain of the level shift MOSs (MN1, MN2) with reference to the reference power supply voltage GND, the level shift MOS (MN1, MN2) is a high voltage element. Need to be.

  The level shift MOS (MN2) causes a predetermined pulse current to flow through the resistor R2 in accordance with the set signal ST, thereby changing the voltage level of the set signal ST to a voltage level suitable for the set input (S) of the SR latch circuit SRLT. Convert. Similarly, the level shift MOS (MN1) causes the voltage level of the reset signal RT to match the reset input (R) of the SR latch circuit SRLT by flowing a predetermined pulse current through the resistor R1 according to the reset signal RT. Convert to voltage level. As described above, the level shift circuit LSC is a circuit having a function similar to that of the insulating element described in FIG. 4 (the photocoupler CPL10 in the example of FIG. 4), and a signal based on the reference power supply voltage GND is supplied as a floating voltage. The signal is converted into a signal based on VS.

  The low-side control circuit LCT includes a low-side driver LDV and a protection circuit PRCd including a low-side low voltage detection circuit UVLO1, which operate at the power supply voltage VCC with reference to the reference power supply voltage GND. The low side driver LDV is configured by a CMOS inverter or the like that receives the output signal of the protection circuit PRCd, and drives the low side transistor TRl by transmitting a low side switch signal LO to the pad PD (LO).

  The low side low voltage detection circuit UVLOl controls the low side switch signal LO to the reference power supply voltage GND level via the low side driver LDV when the value of the power supply voltage VCC does not reach a predetermined voltage value. As a result, the low side transistor TRl is fixed off until the value of the power supply voltage VCC reaches a predetermined voltage value. In addition, the low-side low voltage detection circuit UVLOl notifies the pulse generation circuit PGEN when the value of the power supply voltage VCC does not reach a predetermined voltage value. In response to the notification, the pulse generation circuit PGEN stops generating at least the set signal ST. As a result, the high-side transistor TRh is also fixed off until the value of the power supply voltage VCC reaches a predetermined voltage value.

  Note that the protection circuit PRCd represents various types of low-side transistors TRl such as protection by the low-side low-voltage detection circuit UVLOl and protection at the time of load short-circuiting detected through the diode Ddes as described in FIG. Provide protection. The protection circuit PRCd outputs the output signal of the delay circuit DLY to the low side driver LDV in a period in which protection due to such an abnormality is not necessary.

  The bootstrap circuit BSC has a configuration equivalent to the bootstrap diode Db described in FIG. 1, and appropriately charges the bootstrap capacitor Cb so that the charging voltage of the bootstrap capacitor Cb can maintain the power supply voltage VCC. . The temperature detection circuit TCl includes a current source IS2 and a differential amplifier circuit AMP2 as in the case of FIG. The power source voltage VCC is supplied to the current source IS2 and the differential amplifier circuit AMP2. The input node of differential amplifier circuit AMP2 is coupled to pad PD (TOL) and pad PD (GND), respectively, and the output node is coupled to pad PD (TIL).

  Similarly to the case of FIG. 4, the temperature detection circuit TCh also includes diodes DD1a and DD1b, current sources IS1a and IS1b, and a differential amplifier circuit AMP1. The power supply voltage VCC is supplied to the current sources IS1a and IS1b and the differential amplifier circuit AMP1. The cathode of diode DD1a is coupled to pad PD (TOH), and the cathode of diode DD1b is coupled to pad PD (VS). The output node of differential amplifier circuit AMP1 is coupled to pad PD (TIH). Although not shown, for example, a signal at the level of the power supply voltage VCC (for example, 15 V) is converted into a signal at the level of the power supply voltage VDD (for example, 5 V) before the pad PD (TIH) and the pad PD (TIL). A level shift circuit may be provided.

<< Schematic Layout Configuration of Driver IC (Semiconductor Device) >>
FIG. 9 is a plan view showing a schematic layout configuration example in the semiconductor device of FIG. A semiconductor device (driver IC) DVIC1 shown in FIG. 8 is configured by one semiconductor chip, and a termination region AR_TRMBK, a low voltage region AR_LVBK, and a high voltage region AR_HVBK are formed on the semiconductor chip. Termination region AR_TRMBK is a region that has a ring shape and separates and combines a circuit that operates with power supply voltage VCC and a circuit that operates with boot power supply voltage VB.

  In the termination region AR_TRMBK, each circuit shown in the termination unit TRMBK in FIG. 8 is formed. Specifically, in the termination region AR_TRMBK, a region AR_MN1 of the level shift MOS (MN1), a region AR_MN2 of the level shift MOS (MN2), a region AR_DD1a of the diode DD1a, and a region AR_DD1b of the diode DD1b are provided. In the termination region AR_TRMBK, for example, a transistor (or a diode) having a withstand voltage of 300 V or more between the source and drain (or between the anode and the cathode), preferably 600 V or more is formed.

  The low voltage region AR_LVBK is provided outside the termination region AR_TRMBK, and a circuit that operates at the power supply voltage VCC with respect to the reference power supply voltage GND is formed. Specifically, in the low voltage region AR_LVBK, the current sources IS1a and IS1b in the signal processing circuit LGC, the low-side control circuit LCT, the low-side temperature detection circuit TCl, and the high-side temperature detection circuit TCh in FIG. An amplifier circuit AMP1 is formed. The high voltage region AR_HVBK is provided inside the termination region AR_TRMBK, and a circuit that operates with the boot power supply voltage VB with respect to the floating voltage VS is formed. Specifically, in the high voltage region AR_HVBK, as shown in the high voltage circuit unit HVBK in FIG. 1, a high side control circuit HCT and resistors R1 and R2 in the level shift circuit LSC are formed.

As the diodes DD1a and DD1b formed in the regions AR_DD1a and AR_DD1b, respectively, for example, the structure shown in FIG. 7A can be used. In this case, for example, the planar structure of the area AR_DD1a in FIG. 9 and the cross-sectional structure between AA ′ are as shown in FIG. The p-type separation layer IDF shown in the plan view of FIG. 7A is a boundary portion of the area AR_DD1a of FIG. Also, the n ⁺ -type buried layer BDF2 shown in FIG. 7A extends to the entire surface of the high voltage region AR_HVBK in FIG. 9 and serves as a layer to which the boot power supply voltage VB is supplied.

  The level shift MOSs (MN1, MN2) formed in the regions AR_MN1 and AR_MN2, respectively, can use a structure substantially similar to that in the case of FIG. That is, in the diode DD of FIG. 7A, as described above, the parasitic diode of the MOS transistor is used by short-circuiting the gate and source of the MOS transistor, but in the level shift MOS (MN1, MN2), The MOS transistor may be used as a MOS transistor.

  FIG. 10 is a plan view showing an example of a layout configuration obtained by extending FIG. The driver IC (DVIC1) shown in FIG. 9 has a configuration in which each circuit for one phase (for example, u phase) in FIG. 4 is mounted on one semiconductor chip. However, as shown in FIG. The remaining two-phase (v-phase and w-phase) circuits can also be mounted on the same semiconductor chip. The semiconductor device (driver IC) DVIC2 shown in FIG. 10 is composed of one semiconductor chip, and the semiconductor chip includes a termination region AR_TRMBK (u, v, w) for three phases and a low voltage region AR_LVBK (u, v, w) and a high voltage region AR_HVBK (u, v, w) are formed.

<Configuration of power module>
FIG. 11 is a plan view showing a schematic package configuration example in the power module according to the third embodiment of the present invention. The power module PMD shown in FIG. 11 is composed of a single package. For example, a wiring board PCB such as a glass epoxy board, lead frames LF1 to LF4, and a plurality of external leads LF serving as external terminals are epoxy resin or the like. It is the structure sealed with the sealing material PKG.

  A driver IC (semiconductor device) DVIC2 as shown in FIG. 10 is mounted on the wiring board PCB. The plurality of external leads LF include an input power supply terminal PN_VIN, a three-phase load drive terminal PN_OUT (u, v, w), and a reference power supply terminal PN_GND. In addition, the plurality of external leads LF include a power supply terminal PN_VCC, a three-phase high side signal terminal PN_HIN (u, v, w), a low side signal terminal PN_LIN (u, v, w), and three A phase high-side temperature terminal PN_TIH (u, v, w) and a low-side temperature terminal PN_TIL (u, v, w) are included.

  Power supply terminal PN_VCC is coupled to pad PD (VCC) in FIG. The high side signal terminal PN_HIN (u, v, w) is coupled to each pad when the pad PD (HIN) of FIG. 8 is provided for three phases, and the low side signal terminal PN_LIN (u, v, w) is The pad PD (LIN) is coupled to each pad when three phases are provided. The high side temperature terminal PN_TIH (u, v, w) is coupled to each pad when the pad PD (TIH) of FIG. 8 is provided for three phases, and is connected to the high side via the temperature detection circuit (coupling circuit) TCh. This is a terminal for communicating with the switch HSW. Similarly, the low-side temperature terminal PN_TIL (u, v, w) is coupled to each pad when the pad PD (TIL) is provided for three phases, and the low-side switch via the temperature detection circuit (coupling circuit) TCl. It becomes a terminal which communicates with LSW.

  The lead frame LF1 is integrated with the input power supply terminal PN_VIN, and includes three high-side transistors TRhu, TRhv, TRhw and three free-wheeling diodes FDhu, FDhv, FDhw. The lead frame LF2 is integrated with the load drive terminal PN_OUTu, and includes a low side transistor TRlu and a free wheel diode FDlu. The lead frame LF3 is integrated with the load drive terminal PN_OUTv, and includes a low-side transistor TRlv and a free-wheeling diode FDlv. The lead frame LF4 is integrated with the load drive terminal PN_OUTw, and includes a low side transistor TRlw and a free wheel diode FDlw.

  As shown in FIG. 5, each of the three high-side transistors TRhu, TRhv, TRhw and the three low-side transistors TRlu, TRlv, TRlw has a mounting surface (that is, the back surface) on the lead frame as a collector electrode CP. The device has a vertical device structure in which the emitter electrode EP and the gate electrode GP are arranged on the surface. Further, the anode electrode AP and the cathode electrode KP of the temperature detection diode TD are also arranged on the surface. Each of the six free-wheeling diodes FDhu, FDhv, FDhw, FDlu, FDlv, and FDlw has a vertical device structure in which the mounting surface (that is, the back surface) to the lead frame is a cathode electrode and the anode electrode is disposed on the surface. have.

  The emitter electrode EP and the cathode electrode KP arranged in the high side transistor TRhu and the anode electrode of the freewheeling diode FDhu are coupled to the load drive terminal PN_OUTu via the bonding wire BW. Similarly, each electrode (EP, KP) disposed in the high side transistor TRhv and an anode electrode of the free wheel diode FDhv are coupled to the load drive terminal PN_OUTv, and each electrode (EP, KP) disposed in the high side transistor TRhw. ) And the anode electrode of the freewheeling diode FDhw are coupled to the load driving terminal PN_OUTw.

  The emitter electrode EP and the cathode electrode KP arranged in the low side transistor TRlu and the anode electrode of the freewheeling diode FDlu are coupled to the reference power supply terminal PN_GND via the bonding wire BW. Similarly, each electrode (EP, KP) formed in the low side transistor TRlv and an anode electrode of the freewheeling diode FDlv are coupled to the reference power supply terminal PN_GND, and each electrode (EP, KP formed in the low side transistor TRlw). ) And the anode electrode of the freewheeling diode FDlw are coupled to the reference power supply terminal PN_GND.

  Three bonding wires BW respectively coupled to the load drive terminals PN_OUTu, PN_OUTv, and PN_OUTw are coupled to the wiring board PCB, and are coupled to the driver IC (DVIC2) via the three wirings LN on the wiring board PCB. The The three wirings LN are wirings that transmit the floating voltages VSu, VSv, and VSw, respectively. The bonding wire BW coupled to the reference power supply terminal PN_GND is coupled to the wiring board PCB, and is coupled to the driver IC (DVIC2) via the wiring LN on the wiring board PCB. The wiring LN is a wiring that transmits the reference voltage GND.

  The three gate electrodes GP respectively disposed in the high-side transistors TRhu, TRhv, TRhw are coupled to the wiring board PCB via three bonding wires BW, and via three wirings LN on the wiring board PCB. Each is coupled to a driver IC (DVIC2). The three wirings LN are wirings that transmit the high-side switch signals HOu, HOv, and HOw, respectively. The three gate electrodes GP respectively disposed in the low side transistors TRlu, TRlv, TRlw are coupled to the wiring board PCB via three bonding wires BW, and via three wirings LN on the wiring board PCB. Each is coupled to a driver IC (DVIC2). The three wirings LN are wirings that transmit the low-side switch signals LOu, LOv, and LOw, respectively.

  Three anode electrodes AP respectively disposed on the high side transistors TRhu, TRhv, TRhw are coupled to the wiring board PCB via three bonding wires BW, and via three wirings LN on the wiring board PCB. Each is coupled to a driver IC (DVIC2). The three wirings LN are wirings that transmit the temperature voltage signals TOHu, TOHv, and TOHw, respectively. The three anode electrodes AP respectively disposed in the low-side transistors TRlu, TRlv, TRlw are coupled to the wiring board PCB via three bonding wires BW and via three wirings LN on the wiring board PCB. Each is coupled to a driver IC (DVIC2). The three wirings LN are wirings that transmit the temperature voltage signals TOLu, TOLv, and TOLw, respectively.

<< Main effects of the third embodiment >>
FIG. 12 is a schematic diagram illustrating an example of a mounting form of the power module of FIG. As shown in FIG. 12, the power module PMD is mounted on a wiring board BD that is a component of the power conversion system, for example. A heat dissipating component such as a heat sink HSK is mounted on the surface facing the substrate mounting surface via a resin paste RP. Such mounting is performed by, for example, a set manufacturer.

  At this time, for example, when the system as shown in FIG. 16 is used, it is difficult to mount an insulating element such as the photocoupler CPL1 ′ on the power module PMD. It is necessary to separately mount temperature detection circuits TChu ′, TChv ′, and TChw ′ including the circuit board BD. In addition, when the method as shown in FIG. 17 is used, as described above, the accuracy of the temperature detection circuits (TChu ″, TChv ″, TChw ″) is lowered. In order to compensate for the low accuracy, it is necessary to secure an excessive margin (derating), specifically, for example, it is necessary to excessively design characteristics such as the heat sink HSK of FIG.

  On the other hand, when the system of the third embodiment is used, as shown in FIG. 11 and the like, the inverter and each control circuit thereof are mounted on one power module PMD, so that each transistor, circuit, and the like are separated from each other. As compared with the case of mounting on the wiring board BD, the number of components mounted on the wiring board BD can be reduced. In particular, the temperature detection circuits TChu ′, TChv ′, and TChw ′ including the insulating elements as shown in FIG. 16 can be deleted from the mounted components of the wiring board BD. In addition, the level shift circuit LSC in FIG. 8 corresponds to the photocoupler CPL10. Insulating elements can also be eliminated. As a result, it is possible to reduce costs and reduce the size of the power conversion system. Furthermore, the characteristics of the heat sink HSK and the like can be optimized, and from this point, the cost can be reduced and the power conversion system can be downsized.

(Embodiment 4)
<< Schematic configuration of power conversion system (application example [2]) >>
FIG. 13 is a circuit diagram showing a schematic configuration example of the main part in the power conversion system according to the fourth embodiment of the present invention. The power conversion system shown in FIG. 13 has a configuration in which coupling circuits HCC2u, HCC2v, and HCC2w are further added to the configuration example of FIG. The coupling circuits HCC2u, HCC2v, and HCC2w correspond to the coupling circuit HCC2 shown in FIG.

  For example, the coupling circuit HCC2u includes a capacitor C2 and a buffer circuit BF in addition to the same diode DD2 and pull-down switch DS as in FIG. The pull-down switch DS is composed of, for example, an NMOS transistor and is not shown in the figure, but is turned on / off by the high-side control circuit HCTi as in the case of FIG. Capacitor C2 is coupled in parallel with pull-down switch DS between the cathode of diode DD2 and load drive terminal PN_OUTu (floating voltage VSu). The buffer circuit BF is, for example, a voltage follower circuit that operates with the boot power supply voltage VB and the floating voltage VSu, and the input is coupled to the cathode of the diode DD2, and the output is coupled to the high-side control circuit HCTU.

  For example, the controller CTLU includes a digital / analog converter DAC, and transmits the signal VDAC from the digital / analog converter DAC to the anode of the diode DD2. The coupling circuits HCC2v and HCC2w have the same configuration as the coupling circuit HCC2u. When the driver IC as described in the third embodiment is used, the diode DD2 is formed in the termination region AR_TRMBK in FIG. 9, and the pull-down switch DS, the capacitor C2, and the buffer circuit BF are in the high voltage region AR_HVBK in FIG. Formed.

  For example, the high side control circuit HCTu may include a circuit that variably controls the 'H' level voltage of the high side switch signal HOu. When this circuit is used, for example, noise can be reduced by adjusting the slew rate of the high-side switch TRhu. Alternatively, as a protection operation when a temperature abnormality is detected, the high-side switch TRhu is not turned off (ie, the system is stopped) as shown in FIG. By causing the side switch TRhu to perform the operation, the temperature can be returned to the safe region. The coupling circuit HCC2u transmits, for example, an arbitrary voltage signal from the controller CTLU directed to such a circuit.

<< Schematic operation of power conversion system (application example [2]) >>
FIG. 14 is a waveform diagram showing a schematic operation example of the main part in the power conversion system of FIG. 13. Here, the operation of the u phase in FIG. 13 will be described as an example, but the same applies to the v phase and the w phase. In FIG. 14, periods T1, T3, and T5 are the low-side periods described above, and periods T2, T4, and T6 are the high-side periods described above. In the PWM cycle of the periods T1 and T2, the high-side switch signal HOu has a “H” level voltage that is the boot power supply voltage VB.

  At time t3a in the period T3, the controller CTLU transmits a signal VDAC having a predetermined voltage level. On the other hand, the high-side control circuit HCTu controls the pull-down switch DS to be on during the period from time t3a to t3b. Accordingly, the input voltage (and output voltage) of the buffer circuit BF becomes the floating voltage VSu. When the pull-down switch DS is turned off at time t3b, the capacitor C2 is charged with the voltage of the signal VDAC, and the input voltage (and output voltage) of the buffer circuit BF also becomes the voltage of the signal VDAC.

  When the period T3 transitions to the period T4, the input voltage (and output voltage) of the buffer circuit BF becomes a voltage obtained by adding the voltage of the signal VDAC to the floating voltage VSu (that is, the input power supply voltage VIN), and the diode DD2 is reverse-biased. . In the period T4, the signal VDAC from the controller CTLU is not transmitted to the buffer circuit BF, but the voltage of the signal VDAC is maintained by the capacitor C2 and output from the buffer circuit BF. Based on the output voltage of the buffer circuit BF, the high-side control circuit HCTU variably controls the “H” level voltage of the high-side switch signal HOu between the floating voltage VSu and the boot power supply voltage VB.

  Next, the period T4 transitions to the period T5. Similar to the period from time t3a to t3b, the high-side control circuit HCTi controls the pull-down switch DS to be turned on in the period from time t5a to t5b in period T5. Along with this, the capacitor C2 is discharged, and the input voltage (and output voltage) of the buffer circuit BF becomes the floating voltage VSu. When the pull-down switch DS is turned off at time t5b, the capacitor C2 is charged with the voltage of the signal VDAC, and thereafter the same operation is repeated.

<< Main effects of the fourth embodiment >>
As described above, when the power conversion system according to the fourth embodiment is used, communication between the controller CTLU and the high-side control circuits HCTu, HCTv, and HCTw can be performed at a low cost, as in the first embodiment. As a result, it is possible to easily increase the functionality of the power conversion system. Specifically, fine control from the controller CTLU toward the high side can be performed, with the adjustment of the voltage level of the high-side switch signal described above as a representative. At this time, since various controls can be performed mainly by software of the controller CTLU, flexible control can be realized at low cost.

(Embodiment 5)
<Problem of coupling circuit>
18 (a) and 18 (b) are waveform diagrams showing an example of a problem of a coupling circuit that is a precondition in the power conversion system according to the fourth embodiment of the present invention. FIG. 18A shows an actual operation waveform of the temperature detection circuit TChu, taking as an example the case where the temperature detection circuit TChu of FIG. 4 is applied to the coupling circuit HCC1 of FIG. FIG. 18B shows an actual operation waveform of the temperature detection circuit TClu, taking as an example the case where the temperature detection circuit TClu of FIG. 4 is applied to the coupling circuit LCC of FIG.

  As described with reference to FIG. 4, the temperature detection circuit TChu has the temperature voltage signal TOHu and the floating voltage VSu according to the forward voltage of the temperature detection diode TDhu in the low side period (the “H” level period of the low side switch signal LOu). Is detected and amplified to output a temperature voltage signal TIHu. However, in actual operation, as shown in FIG. 18A, the temperature voltage signal TIHu may be distorted. This distortion is caused by fluctuation of the forward voltage of the temperature detection diode TDhu due to noise (that is, switching noise) accompanying switching of the high side switch HSW and the low side switch LSW.

  In the example of FIG. 18 (a), distortion occurs in four places, in which the other two places are added to the rising / falling places of the low-side switch signal LOu. Thus, the distortion of the phase to be detected (here, the u phase) is not limited to the switching noise of each switch (HSWu, LSWu) corresponding to the phase to be detected (u phase), and other phases (v phase and This is also caused by the switching noise of each switch (HSWv, LSWv, HSWw, LSWw) corresponding to w phase. Further, as shown in FIG. 18B, distortion may occur in the same manner with respect to the low-side temperature voltage signal TILu.

  When the distortion as shown in FIG. 18A occurs, it may be difficult for the controller CTLU to detect the temperature with high accuracy. Further, the period during which the temperature can be detected is greatly limited, and in some cases, the period may not be sufficiently obtained. That is, as described above, the period during which the high-side temperature can be detected is limited to the low-side period, but during this low-side period, the period during which the temperature can be correctly detected is further limited by distortion. Depending on the duty, the period itself may not be sufficiently obtained.

<< Schematic configuration of power conversion system (application example [3]) >>
FIG. 19 is a circuit diagram illustrating a schematic configuration example of a main part in the power conversion system according to the fifth embodiment of the present invention. The power conversion system shown in FIG. 19 differs from the power conversion system shown in FIG. 4 in the configuration of the high-side temperature detection circuit TChu2 and the configuration of the controller CTLU2. In FIG. 19, for convenience, the inverter IVU shows the configuration of only the u phase, but actually, it also includes the configurations of the v phase and the w phase as in the case of FIG. 4. Also, FIG. 19 shows the u-phase high-side temperature detection circuit TChu2, but, similarly to the case of FIG. 4, the temperature detection circuit having the same configuration as that of the temperature detection circuit includes the v-phase and w-phase high detection circuits. Also provided on the side.

  The temperature detection circuit TChu2 has a configuration in which switches SW1a and SW1b and low-pass filters LPF1a and LPF1b are added to the temperature detection circuit TChu of FIG. The switch SW1a and the low pass filter LPF1a are serially inserted in series from the diode DD1a side into the wiring between the diode DD1a and the differential amplifier circuit AMP1. The switch SW1b and the low pass filter LPF1b are inserted in series in order from the diode DD1b side into the wiring between the diode DD1b and the differential amplifier circuit AMP1.

  As in the case of FIG. 4, the controller CTLU2 transmits a high-side switch control signal HINu that is an on / off signal for the high-side switch HSWu from the IO terminal IO1u, and an on / off signal for the low-side switch LSWu from the IO terminal IO2u. The low side switch control signal LINu is transmitted. Although omitted in FIG. 19 for the sake of convenience, the controller CTLU2 similarly transmits high-side switch control signals HINv and HINw from the IO terminals IO1v and IO1w for the v phase and the w phase, and the IO terminals IO2v, Low-side switch control signals LINv and LINw are transmitted from IO2w.

  Further, unlike the case of FIG. 4, the controller CTLU2 includes a switch control circuit SWCTL. The switch control circuit SWCTL generates a switch control signal Ssw based on each switch control signal (HINu, HINv, HINw, LINu, LINv, LINw) and transmits it to the switches SW1a and SW1b from the IO terminal IO3. The switches SW1a and SW1b are turned on / off according to the switch control signal Ssw.

  The switches SW1a and SW1b are controlled to be turned off in a predetermined period (for example, several μs) including the timing at which the high-side switches HSWu, HSWv, and HSWw and the low-side switches LSWu, LSWv, and LSWw are turned on / off. It is controlled to turn on in a period excluding a predetermined period. That is, the switches SW1a and SW1b are controlled to be off in a period during which distortion due to switching noise can occur as shown in FIG. The switch control circuit SWCTL can obtain the start timing of this period based on each switch control signal (HINu, HINv, HINw, LINu, LINv, LINw).

  Here, if the switches SW1a and SW1b are controlled to be off, the input of the differential amplifier circuit AMP1 is open, and there is a concern that the input becomes indefinite. Therefore, here, low-pass filters LPF1a and LPF1b are inserted in the wiring between the switches SW1a and SW1b and the differential amplifier circuit AMP1. Since the low-pass filters LPF1a and LPF1b include a capacitor coupled between the wiring and the reference power supply voltage GND, the potential immediately before the switch is turned off (in other words, temperature) can be held for a certain period. Further, since the temperature change in a short period of several μs is extremely small (for example, 0.1 ° C. or less), the difference between the temperature after this period and the temperature at the time of holding can be ignored.

  The low-pass filters LPF1a and LPF1b reduce the noise generated in the temperature voltage signal TOHu during the on-period of the switches SW1a and SW1b in addition to the role of holding the temperature information during the off-period of the switches SW1a and SW1b. In addition, it plays a role of reducing noise caused by turning on and off the switches SW1a and SW1b. Further, the system of FIG. 19 can be applied not only to the temperature detection circuit TChu2 but also to the coupling circuit HCC1 of FIG. In this case, similarly, it is beneficial to insert a switch (referred to as SW1) in the wiring between the diode DD1 and the controller CTLU. It is also beneficial to insert a low-pass filter (referred to as LPF1) in the wiring between the switch (SW1) and the controller CTLU.

<< Operation of temperature detection circuit (application example [3]) >>
FIG. 20 is a schematic diagram showing an example of operation timing of the temperature detection circuit of FIG. Here, u-phase and v-phase low-side switch control signals LINu and LINv are shown as an example, but the same operation is performed for other switch control signals (LINw, HINu, HINv, and HINw). In the example of FIG. 20, the rising / falling edges of the low-side switch control signals LINu and LINv are generated four times in total, and accordingly, the 'L' period of the switch control signal Ssw is generated four times. The four periods are the off periods Toff1 to Toff4 of the switches SW1a and SW1b.

  In the off periods Toff1 to Toff4, the low-side switches LSWu and LSWv are switched, and the u-phase and v-phase floating voltages VSu and VSv transition. In response to this transition, switching noise is superimposed on the temperature voltage signal TOHu, but the switches SW1a and SW1b are off, so the temperature voltage signal TIHu is not affected. Note that the off periods Toff1 to Toff4 may have a length that includes a period in which the u-phase, v-phase, and w-phase floating voltages VSu, VSv, and VSw transition, and are usually the same length (for example, 3 μs). Can be determined.

<Configuration of switch control circuit>
FIG. 21 is a schematic diagram illustrating a configuration example of the switch control circuit of FIG. For example, when the controller CTLU2 is a microcontroller (MCU) or the like, a switch control circuit SWCTL equivalent to, for example, FIG. 21 is constructed by a program process by a CPU (Central Processing Unit). The switch control circuit SWCTL in FIG. 21 includes six pairs (here, only three of them are exemplified) of a rising detection circuit RDET and a falling detection circuit FDET, an OR operation circuit OR, a timer circuit TMR, and an SR latch. Circuit SRLT2.

  The rise detection circuit RDET and the fall detection circuit FDET are provided for each of the u-phase, v-phase, and w-phase switch control signals (LINu, HINu, LINv, HINv, LINw, HINw). For example, the rising edge detection circuit RDET corresponding to the low side switch control signal LINu generates the rising edge detection signal RDlu when the “H” transition of the low side switch control signal LINu occurs. Further, the falling detection circuit FDET corresponding to the low side switch control signal LINu generates the falling detection signal FDlu when the “L” transition of the low side switch control signal LINu occurs.

  Similarly, the rise detection circuits RDET corresponding to the other switch control signals (HINu, LINv, HINv, LINw, HINw) respectively detect the rise detection signals RDhu, RDlv, RDhv, RDlw, and RDhw are generated. The fall detection circuits FDET corresponding to the other switch control signals (HINu, LINv, HINv, LINw, HINw) respectively fall according to the 'L' transition of the corresponding switch control signal FDhu, FDlv, FDhv. , FDlw, FDhw are generated.

  The OR operation circuit OR outputs a timer start signal TST according to the OR operation result of each detection signal (RDlu, FDlu, RDhu, FDhu,..., RDhw, FDhw). The timer circuit TMR starts counting for a predetermined period (for example, several μs) corresponding to each of the off periods Toff1 to Toff4 of FIG. 20 according to the timer start signal TST, and outputs a time-up signal TUP when the count expires To do. At this time, if the timer circuit TMR receives the timer start signal TST during counting, the timer circuit TMR starts counting again. The SR latch circuit SRLT2 changes the switch control signal Ssw to the 'L' level according to the timer start signal TST, and changes to the 'H' level according to the time-up signal TUP.

  As described above, by using the power conversion system of the fifth embodiment, in addition to the various effects described in the second embodiment, the influence of switching noise can be effectively eliminated with a small circuit overhead. As a result, high accuracy in temperature detection can be realized. In addition, the low-pass filter capacitor can ensure a sufficient period for temperature detection.

  The configurations of the switches SW1a and SW1b and the low-pass filters LPF1a and LPF1b described above are also effective for low-side communication. Since the low side is not floating, insulation with a high voltage diode is unnecessary, but as shown in FIG. 18B, noise due to the switching element is superimposed in the same way as the high side in terms of noise. Therefore, as shown in FIG. 19, the influence of switching noise can be effectively eliminated by providing a noise filter NFLT including a switch and a low-pass filter on the low side.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  For example, in the second and fourth embodiments, as an application example of the method of FIG. 1, high-side temperature detection and adjustment of the voltage level of the high-side switch signal are performed. Similarly, for example, high-side overvoltage detection and overcurrent detection, and various high-side controls corresponding thereto can be performed. In the second embodiment and the fourth embodiment, an inverter having a three-phase bridge configuration is taken as an example. However, as the number of switches increases, a more beneficial effect can be obtained.

AMP1, AMP2 Differential amplifier circuit AR_HVBK High voltage region AR_LVBK Low voltage region AR_TRMBK Termination region BW Bonding wire CPL10 Photocoupler CTLU controller DD1, DD1a, DD1b, DD2 Diode DS Pull-down switch DVIC1, DVIC2 Driver IC (semiconductor device)
HCC1, HCC2, LCC coupling circuit HCT High side control circuit HDV High side driver HSU High side circuit HSW High side switch IS1, IS1a, IS1b, IS2 Current source LCT Low side control circuit LD Load LDV Low side driver LF Lead (External terminal)
LSC Level shift circuit LSU Low side circuit LSW Low side switch PCB PCB Wiring board PD Pad (terminal)
PKG Sealing material PMD Power module PN_GND Reference power supply terminal PN_OUT Load drive terminal PN_VIN Input power supply terminal TChu, TChv, TChw, TClu, TClv, TClw Temperature detection circuit TDhu, TDhv, TDhw, TDluh, TDlv, TDlvh Transistor TRl Low side transistor VB Boot power supply voltage VCC Power supply voltage VIN Input power supply voltage VS Floating voltage

Claims (20)

A high-side circuit and a low-side circuit;
A controller in communication with the high side circuit and the low side circuit;
A first coupling circuit including wiring between the controller and the high side circuit;
A second coupling circuit including wiring between the controller and the low side circuit;
A power conversion system comprising:
The high side circuit is:
A high-side switch coupled between a first power supply terminal to which a first power supply voltage is supplied with reference to a reference power supply voltage and a load drive terminal and supplying power to the load via the load drive terminal;
A high side driver for driving the high side switch;
With
The low side circuit is:
A low-side switch coupled between a reference power supply terminal to which the reference power supply voltage is supplied and the load drive terminal, and supplies power to the load via the load drive terminal;
A low side driver for driving the low side switch;
With
The first coupling circuit includes a diode having an anode coupled to the wiring from the controller and a cathode coupled to the wiring from the high side circuit.
Power conversion system. The power conversion system according to claim 1, wherein
The high side circuit includes a first temperature detection diode formed on the same semiconductor chip as the high side switch, detecting a temperature of the high side switch, and having a cathode coupled to the load driving terminal.
The first coupling circuit includes:
A first diode having a cathode coupled to an anode of the first temperature sensing diode;
A second diode having a cathode coupled to the cathode of the first temperature sensing diode;
A first current source that is supplied with a second power supply voltage lower than the first power supply voltage and flows a forward current to the first temperature detection diode via the first diode;
A second current source that is supplied with the second power supply voltage and causes a forward current to flow through the second diode;
A first differential amplifier circuit that detects a differential voltage between the anode of the first diode and the anode of the second diode and transmits the detection result to the controller;
Having
Power conversion system. The power conversion system according to claim 2, wherein
In the first differential amplifier circuit, the first temperature detection diode is connected in the order of the first diode and the second diode in a period in which the high-side switch is off and the low-side switch is on. Detect direction voltage,
Power conversion system. The power conversion system according to claim 3, wherein
The low side circuit includes a second temperature detection diode formed on the same semiconductor chip as the low side switch, detecting a temperature of the low side switch, and having a cathode coupled to the reference power supply terminal,
The second coupling circuit is:
A third current source for passing a forward current through the second temperature detection diode;
A second differential amplifier circuit for detecting a difference voltage between an anode and a cathode of the second temperature detection diode and transmitting the detection result to the controller;
Having
Power conversion system. The power conversion system according to claim 1, wherein
The diode transmits a signal from the controller to the high-side circuit in a period in which the high-side switch is off and the low-side switch is on.
Power conversion system. The power conversion system according to claim 5, wherein
The first coupling circuit includes a pull-down switch coupled between a cathode of the diode and the load driving terminal.
Power conversion system. The power conversion system according to claim 5, wherein
The power conversion system further includes an insulating element that converts the voltage level of the output signal of the controller into the voltage level of the input signal of the high-side circuit,
The insulating element transmits an on / off signal of the high-side switch transmitted from the controller to the high-side circuit.
Power conversion system. The power conversion system according to claim 1, wherein
The diode transmits a signal from the high-side circuit to the controller in a period in which the high-side switch is off and the low-side switch is on.
Power conversion system. The power conversion system according to claim 8, wherein
The first coupling circuit includes a current source that is supplied with a second power supply voltage lower than the first power supply voltage and flows a forward current to the diode.
Power conversion system. A first power supply terminal to which the first power supply voltage is supplied with reference to the reference power supply voltage;
A reference power supply terminal to which the reference power supply voltage is supplied;
A load drive terminal;
A high-side circuit and a low-side circuit;
A first terminal for transmitting or receiving a signal to or from the high side circuit;
A second terminal for transmitting or receiving a signal to or from the low side circuit;
A first coupling circuit including a wiring between the first terminal and the high side circuit;
A second coupling circuit including wiring between the second terminal and the low side circuit;
A power module composed of one package,
The high side circuit is:
A high side transistor coupled between the first power supply terminal and the load drive terminal and supplying power to the load via the load drive terminal;
A high side driver for driving the high side transistor;
With
The low side circuit is:
A low-side transistor coupled between the reference power supply terminal and the load drive terminal and supplying power to the load via the load drive terminal;
A low side driver for driving the low side transistor;
With
The first coupling circuit includes a diode having an anode coupled to the wiring from the first terminal and a cathode coupled to the wiring from the high-side circuit.
Power module. The power module according to claim 10, wherein
The high side transistor is formed in a first semiconductor chip,
The low side transistor is formed in a second semiconductor chip,
The high side driver, the low side driver and the diode are formed in a third semiconductor chip.
Power module. The power module according to claim 11, wherein
The first semiconductor chip is formed with a first temperature detection diode that detects a temperature of the high-side transistor and has a cathode coupled to the load drive terminal.
The third semiconductor chip includes
A first diode having a cathode coupled to an anode of the first temperature sensing diode;
A second diode having a cathode coupled to the cathode of the first temperature sensing diode;
A first current source for causing a forward current to flow to the first temperature detection diode via the first diode;
A second current source for passing a forward current through the second diode;
A first differential amplifier for detecting a differential voltage between the anode of the first diode and the anode of the second diode and transmitting the detection result to the first terminal;
Is formed,
Power module. The power module according to claim 12, wherein
The second semiconductor chip is formed with a second temperature detection diode that detects the temperature of the low-side transistor and has a cathode coupled to the reference power supply terminal.
The third semiconductor chip includes
A third current source for passing a forward current through the second temperature detection diode;
A second differential amplifier circuit that detects a difference voltage between an anode and a cathode of the second temperature detection diode and transmits the detection result to the second terminal;
Is formed,
Power module. The power module according to claim 11, wherein
The diode transmits a signal received at the first terminal to the high side circuit in a period in which the high side transistor is off and the low side transistor is on.
Power module. The power module according to claim 14, wherein
A pull-down transistor coupled between the cathode of the diode and the load drive terminal is formed in the third semiconductor chip.
Power module. A semiconductor device composed of one semiconductor chip,
A load drive terminal coupled to the floating voltage;
A reference power supply terminal to which a reference power supply voltage is supplied;
A first temperature detection terminal coupled to a first temperature detection diode provided outside the semiconductor device;
A termination area with a ring shape;
A first region provided inside the termination region and formed with a circuit that operates with a first power supply voltage with reference to the floating voltage;
A second region provided outside the termination region and formed with a circuit that operates at a second power supply voltage with reference to the reference power supply voltage;
A high-side driver for driving a high-side transistor formed in the first region and provided outside the semiconductor device;
A low-side driver for driving a low-side transistor formed in the second region and provided outside the semiconductor device;
A first diode formed in the termination region and having a cathode coupled to the first temperature detection terminal;
A first current source formed in the second region and coupled to an anode of the first diode;
Having
Semiconductor device. The semiconductor device according to claim 16, further comprising:
A second diode formed in the termination region and having a cathode coupled to the load drive terminal;
A second current source formed in the second region and coupled to an anode of the second diode;
A first differential amplifier circuit formed in the second region for detecting a differential voltage between an anode of the first diode and an anode of the second diode;
Having
Semiconductor device. 18. The semiconductor device according to claim 17, further comprising:
A second temperature detection terminal coupled to a second temperature detection diode provided outside the semiconductor device;
A second current source formed in the second region and coupled to the second temperature sensing terminal;
A second differential amplifier circuit for detecting a differential voltage between the second temperature detection terminal and the reference power supply terminal;
Having
Semiconductor device. The semiconductor device according to claim 16, further comprising:
A level shift circuit including a transistor formed in the termination region, converting a signal based on the reference power supply voltage into a signal based on the floating voltage and outputting the signal to the high-side driver;
Semiconductor device. The semiconductor device according to claim 19, wherein
The first diode is composed of a parasitic diode of a transistor.
Semiconductor device.

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