JP2019017112A - Power circuit - Google Patents

Abstract

To provide a power circuit that suppresses malfunction and parasitic oscillation and has high-speed switching performance, and to provide a power module provided with the power circuit.SOLUTION: A power circuit 1 includes: a main substrate 10; a first electrode pattern 12provided on the main substrate and connected to a positive-side power terminal P; a second electrode pattern 12provided on the main substrate and connected to a negative-side power terminal N; a third electrode pattern 12provided on the main substrate and connected to an output terminal O; a first MISFET Q1 having a first drain disposed on the first electrode pattern; a second MISFET Q4 having a second drain disposed on the third electrode pattern; and a first control circuit (gate diode D) connected between a first gate G1 and a first source S1 of the first MISFET, and controlling a path of current flowing from the first source to the first gate.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power circuit, and more particularly, to a power circuit having high-speed switching performance that suppresses malfunction and parasitic oscillation.

  In a half-bridge circuit, when a switching element of one arm is turned on from a dead time state, there is a phenomenon in which the gate of the other switching element is erroneously turned on due to a drain voltage change (for example, patent document) 1). This is a problem that may occur in, for example, a three-phase inverter for driving a motor or a DC / DC converter for synchronous rectification.

  On the other hand, many research institutions are currently conducting research and development of silicon carbide (SiC) devices. The characteristics of the SiC power device include low on-resistance, high-speed switching, and high-temperature operation that are superior to conventional Si power devices.

JP-A-5-226994

  Furthermore, when the short-circuit current due to erroneous gate turn-on converges, if the energy accumulated in the negative direction in the gate-source capacitance resonates, re-turn-on (oscillation) is induced, and the gate surge voltage and drain surge at that time are induced. The voltage not only can destroy the switching element, but also becomes a noise source.

  When a bridge is formed by a discrete device, a portion where the signal wiring and the power wiring are shared is in the source wiring, and the gate signal is suppressed by the electromotive force of the source wiring, so that extremely high-speed operation is limited.

  On the other hand, a switching element that operates at high speed in a power module in which gate signal wiring and source signal wiring become long by separating signal wiring and power wiring using source sense wiring and connecting semiconductor chips in parallel to allow large capacity Is not affected by gate drive due to electromotive force of the source wiring, and in particular, oscillation caused by this erroneous ON and erroneous ON is a problem and is an important issue to be avoided.

  An object of the present invention is to provide a power circuit having high-speed switching performance while suppressing malfunction and parasitic oscillation.

  According to an aspect of the present invention for achieving the above object, a main substrate, a first MISFET disposed on the main substrate, a second MISFET disposed on the main substrate, and a first of the first MISFET. A first control circuit that is connected between the gate and the first source and controls a path of a current that is conducted from the first source toward the first gate; and is disposed on the main substrate and connected to the first gate And a first signal substrate on which the first source sense signal wiring pattern connected to the first source is mounted, and the first control circuit includes: A third MISFET connected between the first gate signal wiring pattern and the first source sense signal wiring pattern; and the power circuit includes a source of the third MISFET. Scan and is connected between the source sense of the first MISFET, power circuit comprising a first gate capacitor of the gate negative bias applied is provided.

  According to the present invention, it is possible to provide a power circuit having high-speed switching performance by suppressing malfunction and parasitic oscillation.

It is a power circuit which concerns on 1st Embodiment, Comprising: The typical circuit block diagram of a half-bridge circuit. FIG. 2 is a schematic cross-sectional structure diagram of a SiC DISMISFET, which is an example of a semiconductor device applicable to the power circuit according to the first embodiment. It is an example of the semiconductor device applicable to the power circuit which concerns on 1st Embodiment, Comprising: The typical cross-section figure of SiC TMISFET. It is a comparison between a Si device and a SiC device, and (a) a schematic diagram of the p body region 28 and the n ⁻ drift layer 26 of the Si MISFET, (b) a schematic diagram of the p body region and the n drift layer of the SiC MISFET, (c) FIG. 4 is a comparative diagram of electric field intensity distributions corresponding to FIG. 4 (a) and FIG. 4 (b). Explanatory drawing of the parasitic effect of the semiconductor device applicable to the power circuit which concerns on 1st Embodiment, (b) Explanatory drawing of the vibration waveform of drain-source voltage _Vds . (A) Explanatory diagram of parasitic effect between gate and source of SiC MISFET applicable to power circuit according to first embodiment, (b) Explanatory diagram of distributed constant circuit between gate and source, (c) Gate -Equivalent circuit diagram of distributed constant circuit between sources. The circuit diagram explaining an oscillation phenomenon in the power circuit concerning a 1st embodiment. In the configuration of FIG. 7, waveform examples of the gate-source sense voltages V _gs , H · V _gs , L after applying the gate drive voltage, and waveform examples of the drain-source voltages V _ds , H · V _ds , L , And waveform examples of drain currents I _d , H · I _d , and L. 1 is a schematic circuit configuration diagram of a three-phase motor driving three-phase AC inverter to which the power circuit according to the first embodiment can be applied. FIG. In the power circuit according to the first embodiment, (a) a circuit diagram for explaining an oscillation trigger in an oscillation phenomenon, and (b) a circuit diagram for explaining an energy supply source during oscillation. In the power circuit according to the first embodiment, (a) a circuit diagram for explaining an operation simulation when a gate diode as a control circuit is not connected, (b) a gate-source sense voltage in FIG. Waveform example of V _gs , H · V _gs , L, waveform example of drain-source voltage V _ds , H · V _ds , L, and waveform example of drain currents I _d , H · I _d , L. FIG. 3 is a circuit diagram for explaining an operation simulation when a gate diode as a control circuit is connected in the power circuit according to the first embodiment. (A) In FIG. 12, examples of waveforms of gate-source sense voltages V _gs , H · V _gs , L, drain-source voltages V _ds , H · V _ds , L, and drain currents I _d , Waveform example of H · I _d , L, (b) Gate-source sense voltage V _gs , H waveform example when connecting gate diode as control circuit (solid line) and gate Waveform example of source sense voltage V _gs , H (broken line). In the power circuit according to the first embodiment, (a) a circuit diagram for explaining an operation simulation when the gate and source of the first MISFET Q1 on the return side (high side) are short-circuited by the active mirror clamping transistor Q _M1 ; (B) In FIG. 14A, waveform examples of gate-source sense voltages V _gs , H · V _gs , L, drain-source voltages V _ds , H · V _ds , L waveform examples, and drain current Waveform example of I _d , H · I _d , L. The power module which concerns on 1st Embodiment, Comprising: In the two-in-one module (module with a built-in half bridge), the typical plane pattern block diagram before forming the resin layer. The power module which concerns on 1st Embodiment, Comprising: In the module with a built-in half bridge, the typical bird's-eye view block diagram after forming the resin layer. The power module which concerns on 1st Embodiment, Comprising: The half bridge built-in module WHEREIN: The typical bird's-eye view block diagram before forming a resin layer after forming an upper surface board electrode. FIG. 9 is a schematic planar pattern configuration diagram showing a power module according to the first modification of the first embodiment, before forming the resin layer in the half-bridge built-in module. It is a power module which concerns on the modification 1 of 1st Embodiment, Comprising: The typical bird's-eye view block diagram of the module with a built-in half bridge. It is a power circuit which concerns on 2nd Embodiment, Comprising: The typical circuit block diagram of a half-bridge circuit. (A) Operation | movement circuit explanatory drawing of the active mirror clamp applied as a control circuit in the power circuit which concerns on 2nd Embodiment, (b) Operation | movement waveform explanatory drawing of Fig.21 (a). It is a power circuit which concerns on the modification of 2nd Embodiment, Comprising: The typical circuit block diagram of a half-bridge circuit. FIG. 10 is an explanatory diagram of an operation circuit of an active mirror clamp applied as a control circuit in a power circuit according to a modification of the second embodiment. It is a power circuit which concerns on 3rd Embodiment, Comprising: The typical circuit block diagram of a half-bridge circuit. It is a power module which concerns on 3rd Embodiment, Comprising: The top view before forming a resin layer in the module with a built-in half bridge. It is a power module which concerns on the modification 1 of 3rd Embodiment, Comprising: The top view before forming a resin layer in a half-bridge built-in module. FIG. 27 is a schematic circuit configuration diagram of a half-bridge circuit corresponding to FIG. 26, which is a power circuit according to Modification 1 of the third embodiment. It is a power module which concerns on the modification 2 of 3rd Embodiment, Comprising: The top view before forming a resin layer in a half-bridge built-in module. It is a power circuit which concerns on the modification 2 of 3rd Embodiment, Comprising: The typical circuit block diagram of the half-bridge circuit corresponding to FIG. It is a board | substrate structure applied to the power module which concerns on the 1st-3rd embodiment, Comprising: The typical cross-section figure of the signal board | substrate arrange | positioned on a ceramic substrate and a ceramic substrate. It is a board | substrate structure applied to the power module which concerns on the 1st-3rd embodiment, Comprising: The typical cross-section figure of the signal board | substrate which is arrange | positioned on a ceramic substrate and a ceramic substrate, and has a shield layer inside. A substrate structure applied to the power modules according to the first to third embodiments, which is a schematic diagram of a ceramic substrate and a signal substrate that is disposed on the ceramic substrate via a shield metal plate and has a shield layer inside. FIG. (A) It is a power circuit which concerns on 4th Embodiment, Comprising: The circuit block diagram comprised by the discrete device, (b) The plane block diagram of the power module corresponding to Fig.33 (a). (A) It is a power module which concerns on the modification of 4th Embodiment, Comprising: The typical bird's-eye view block diagram comprised by the hybrid device, (b) The model of the structure part which mounted the diode on the semiconductor device (SiC TMISFET) FIG.

  Next, embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the material, shape, structure, The layout is not specified as follows. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[First embodiment]
(Power circuit)
A schematic circuit configuration of the half-bridge circuit, which is the power circuit 1 according to the first embodiment, is expressed as shown in FIG. FIG. 15 shows a schematic planar pattern configuration before the resin layer 120 is formed in the power module 2 in which the power circuit 1 according to the first embodiment is mounted and the two-in-one module (half-bridge built-in module). Represented as shown. The power circuit 1 according to the first embodiment is not limited to the half bridge circuit, and can be applied to a full bridge circuit, a three-phase bridge circuit, or the like.

As shown in FIGS. 1 and 15, the power circuit 1 according to the first embodiment includes a plurality of insulated gate field effect transistors (MISFETs) and electrode patterns 12 ₁ and 12. a circuit in which the drain D1 · D4 of the 1MISFETQ1 · second 2MISFETQ4 is electrically connected on the main substrate 10 having an _n · 12 _4, the gate G1 · G4, source sense SS1 · SS4, external extraction gate terminal GT1 A source sense terminal SST1 and power terminals P and N are provided at the same time, and at least a first control circuit that controls a current path that conducts from the first source S1 of the first MISFET Q1 toward the first gate G1 is provided.

More specifically, the power circuit 1 according to the first embodiment is disposed on the main board 10 and the main board 10 and connected to the positive power terminal P as shown in FIGS. 1 and 15. first and electrode patterns 12 _1, disposed on the main substrate 10, and the second electrode patterns 12 _n that are connected to the negative power terminal n, arranged on the main substrate 10, the first connected to the output terminal O 3 and the electrode pattern 12 _4, and the 1MISFETQ1 the first drain D1 is placed on the first electrode pattern 12 ₁ on, and the 2MISFETQ4 second drain D4 is disposed on the third electrode pattern 12 _4, of the 1MISFETQ1 A first control circuit that is connected between the first gate G1 and the first source S1 and that controls a path of current that is conducted from the first source S1 toward the first gate G1.

  Further, a second control circuit may be provided that is connected between the second gate G4 and the second source S4 of the second MISFET Q4 and controls a current path that conducts from the second source S4 toward the second gate G4. .

Here, the first control circuit includes a first gate diode D _G1 having a cathode connected to the first gate G1 and an anode connected to the first source S1.

The second control circuit includes a second gate diode D _G4 having a cathode connected to the second gate G4 and an anode connected to the second source S4.

Further, in the power circuit 1 according to the first embodiment, as shown in FIGS. 1 and 15, part of the electrode patterns 12 ₁ , 12 ₄ is a signal substrate 14 ₁ , 14 different from the main substrate 10. ₄ , the signal boards 14 ₁ , 14 ₄ may be placed on the main board 10, and the control circuit may be placed on the signal boards 14 ₁ , 14 ₄ . By adopting such a configuration, the control circuit is not easily affected by instantaneous heat generation of the transistor, and malfunction can be avoided.

More specifically, as shown in FIG. 15, the power circuit 1 according to the first embodiment is disposed on the main substrate 10 and is connected to the first gate G1. The first gate signal wiring pattern GL1. , and the first may be provided with a first signal substrate 14 ₁ for mounting the source sensing signal wiring pattern SL1 connected to the first source S1.

Further, as shown in FIG. 15, the second gate signal wiring pattern GL4 disposed on the main substrate 10 and connected to the second gate G4, and the second source sensing signal wiring connected to the second source S4. it may be provided with a second signal substrate 14 ₄ for mounting a pattern SL4.

Here, as shown in FIG. 15, the first control circuit includes a first gate diode D _G1 connected between the first gate signal wiring pattern GL1 and the first source sense signal wiring pattern SL1. May be. It is desirable that these patterns have parallel or face-to-face arrangements to suppress parasitic inductance.

Further, as shown in FIG. 15, the second control circuit includes a second gate diode D _G4 connected between the second gate signal wiring pattern GL4 and the second source sense signal wiring pattern SL4. Also good.

In addition, the forward voltage when the first gate diode D _G1 is conductive is parasitic on the wiring from the first MISFET to the first gate diode so as to be lower than the negative absolute maximum rating of the gate-source voltage of the first MISFET. The circuit constant should be set in consideration of inductance. Similarly, the forward voltage when the second gate diode D _G4 is conductive is lower than the absolute maximum rating on the negative side of the gate-source voltage of the second MISFET, so that the wiring from the second MISFET to the second gate diode is reduced. The circuit constant should be set in consideration of the parasitic inductance.

In the power circuit 1 according to the first embodiment, the forward voltage drop of the first gate diode D _G1 only, a voltage is applied to the gate negative direction between the gate and source of the second MISFET.
For this reason, dielectric breakdown can be prevented by designing the ON characteristics of the first gate diode _DG1 .

As the first gate diode D _G1, zener diode or a Schottky barrier diode (SBD: Schottky Barrier Diode) can be applied to. Similarly, the second gate diode D _G4, is applicable Zener diode or SBD.

When the Zener diode is applied as the first gate diode D _G1 , the forward voltage is high, and thus the voltage applied in the negative direction of the gate is slightly high. However, when the Schottky barrier diode is applied, the forward voltage is low. As a result, the voltage applied in the negative direction of the gate is lowered, and this is easy to cope with.

That is, the forward voltage when the first gate diode D _G1 is conductive needs to be lower than the gate breakdown voltage of the gate-source voltage of the first MISFET. The negative absolute maximum rating value of the gate-source voltage of the first MISFET is, for example, about -6V.

In the power circuit 1 and the power module 2 on which the power circuit 1 is mounted according to the first embodiment, the gate G1 and source sense SS1 wiring pattern on which the first MISFET is mounted (arranged inside the signal terminals GT1 and SST1 connected to the outside) It is important that the gate diode D _G1 (the anode A on the source sense SS1 side and the cathode K on the gate G1 side) for suppressing the oscillation of the gate-source voltage is connected. By connecting in this way the gate diode D _G1, suppresses vibration and oscillation of the gate-source voltage when the voltage applied to the negative direction capacitance between the gate and source, it is possible to obtain a stable operation And since it can be comprised with a simple circuit, it can reduce in size.

In the implementation example of Figure 15, the gate diode D _{G1-D G2,} are examples which is arranged on the main substrate 10 on the signal substrate 14 _1, 14 ₄ disposed on is shown.

As shown in FIG. 1, between the signal terminals GT1 and SST1 extracted externally and the gate G1 and the source sense SS1 of the first MISFET Q1, parasitic inductances L _GP1 and L accompanying the routing of the signal terminals GT1 and SST1 and the electrode wirings are provided. _SP1 exists. Since such an inductance component exists in the gate closed circuit of the first MISFET Q1, an operation delay in the gate drive of the first MISFET Q1 and an increase in gate-source sense voltage fluctuation when the drain-source voltage changes are caused.

The gate diode D _G1 is arranged between the gate G1 and the source sense SS1 wiring. In order to suppress the parasitic effect due to such an inductance component, the gate pad electrode of the first MISFET Q1 from the cathode K / anode A of the diode D _G1 is used. The shorter the distance to the GP / source pad electrode SP, the higher the effect. Here, the gate pad electrode GP and the source pad electrode SP of the first MISFET Q1 are formed on the surface of the first MISFET Q1. Therefore, the gate diode D _G1 may be formed in the same chip as the first MISFET Q1, or the anode A of the gate diode D _G1 chip may be directly soldered on the source pad electrode SP of the first MISFET Q1.

Further, the gate diodes D _G1 may be arranged together for each first MISFET Q1 arranged in parallel, but it is more effective to individually connect each of the plurality of first MISFETs Q1.

It is important that the gate diode D _G1 is arranged inside the externally extracted signal terminals GT1 and SST1 having the parasitic inductances L _GP1 and L _SP1 , and the closer to the first MISFET Q1, the more effective. Alternatively, the effect can be expected even if they are connected so as to bridge the tip of the terminal.

However, when the gate diode D _G1 is directly connected to the chip of the first MISFET Q1, the temperature becomes high. Therefore, the gate diode D _G1 may be composed of a wide band gap semiconductor such as SiC or GaN having a high temperature characteristic. desirable.

A zener diode can be applied as the gate diode D _G1 in terms of arrangement, but since the forward characteristics are utilized, SBD having good characteristics is more effective.

  On the other hand, when a Zener diode is applied, it is expected that the positive gate voltage clamping function is maintained.

The above description is the same for the gate diode _DG2 .

  As described above, according to the power circuit 1 according to the first embodiment, it is possible to obtain a half bridge circuit that is small and suppresses oscillation. Note that the present invention is not limited to the half bridge circuit, and the same applies to a full bridge circuit or a three-phase bridge circuit.

  In addition, one of the first MISFET Q1 and the second MISFET Q2 can be configured by a SiC MISFET.

Since SiC has a high dielectric breakdown electric field, it is possible to realize a low on-resistance R _on by increasing the concentration of the thin film / drift layer. However, the depletion layer expansion width to the drift layer is limited, and the feedback capacitance C _Since the gate-source capacitance is C _gs and the gate-drain capacitance is C _gd because the _rss is difficult to decrease, the ratio of C _gs : C _gd is small, and the gate erroneous ON due to the drain voltage change dV _ds / dt Movement is easy to happen.

  By applying the power circuit 1 according to the first embodiment, parasitic oscillation can be suppressed and high-speed switching performance can be ensured.

In addition, one of the first MISFET Q1 and the second MISFET Q2 may be formed of a SiC trench (T: Trench) MISFET. In SiC TMISFET, it is difficult to set a large C _gs : C _gd ratio. For example, in a region where the drain voltage is 100 V or less, the capacitance ratio C _gd / C _gs is about 1/2 to 1/20. For example, the SiC TMISFET basically does not include a JFET in the current path, so that the feedback capacitance C _rss is less likely to decrease. However, by applying the power circuit 1 according to the first embodiment, parasitic oscillation is suppressed. Fast switching performance can be ensured.

  According to the power module 2 including the power circuit 1 according to the first embodiment, a module in which the control circuit is integrated can be configured. For this reason, variation in the distance between the control circuit and the MISFET can be suppressed, and the influence of the parasitic inductance can be controlled.

(Configuration example of semiconductor device)
-SiC DMISFET-
2 is an example of a semiconductor device 100 applicable to the power circuit 1 according to the first embodiment, and a schematic cross-sectional structure of a SiC DI (Double Implanted) MISFET is represented as shown in FIG.

As shown in FIG. 2, the SiC DISMISFET applicable to the power circuit 1 according to the first embodiment includes a semiconductor substrate 26 made of an n ⁻ high resistance layer, and a p body formed on the surface side of the semiconductor substrate 26. A region 28, an n ⁺ source region 30 formed on the surface of the p body region 28, a gate insulating film 32 disposed on the surface of the semiconductor substrate 26 between the p body regions 28, and a gate insulating film 32. Gate electrode 38, source electrode 34 connected to source region 30 and p body region 28, n ⁺ drain region 24 disposed on the back surface opposite to the surface of semiconductor substrate 26, and n ⁺ drain region 24 And a drain electrode 36 connected to the.

In FIG. 2, the semiconductor device 100 includes a p body region 28 and an n ⁺ source region 30 formed on the surface of the p body region 28 by double ion implantation (DI). 30 and source electrode 34 connected to p body region 28. The gate pad electrode GP (not shown) is connected to the gate electrode 38 disposed on the gate insulating film 32. Further, as shown in FIG. 2, the source pad electrode SP and the gate pad electrode GP (not shown) are disposed on a passivation interlayer insulating film 44 that covers the surface of the semiconductor device 100.

As shown in FIG. 2, in the SiC DISMISFET, a depletion layer as shown by a broken line is formed in a semiconductor substrate 26 made of an n ⁻ high resistance layer sandwiched between p body regions 28. A channel resistance R _{JFET due} to the JFET) effect is formed. A body diode BD is formed between the p body region 28 and the semiconductor substrate 26 as shown in FIG.

―SiC TMISFET―
It is an example of the semiconductor device 100 applicable to the power circuit 1 which concerns on 1st Embodiment, Comprising: The typical cross-section of SiC TMISFET is represented as shown in FIG.

As shown in FIG. 3, the SiC TMISFET applicable to the power circuit 1 according to the first embodiment includes an n-layer semiconductor substrate 26N, and a p body region 28 formed on the surface side of the semiconductor substrate 26N. The n ⁺ source region 30 formed on the surface of the p body region 28 and the trench penetrating the p body region 28 and reaching the semiconductor substrate 26N are interposed via the gate insulating layer 32 and the interlayer insulating films 44U and 44B. Trench gate electrode 38TG formed in this manner, source electrode 34 connected to source region 30 and p body region 28, n + drain region 24 disposed on the back surface opposite to the surface of semiconductor substrate 26N, n ⁺ And a drain pad electrode 36 connected to the drain region 24.

  In FIG. 3, in the semiconductor device 100, a trench gate electrode 38TG formed through the gate insulating layer 32 and the interlayer insulating films 44U and 44B is formed in the trench formed through the p body region 28 to the semiconductor substrate 26N. The source pad electrode SP is connected to the source electrode 34 connected to the source region 30 and the p body region 28. The gate pad electrode GP (not shown) is connected to the gate electrode 38 disposed on the gate insulating film 32. Further, as shown in FIG. 3, the source pad electrode SP and the gate pad electrode GP (not shown) are disposed on the passivation interlayer insulating film 44 </ b> U that covers the surface of the semiconductor device 100.

In the SiC TMISFET, the channel resistance R _JFET associated with the junction FET (JFET) effect like the SiC DIMISFET is not formed. A body diode BD is formed between the p body region 28 / semiconductor substrate 26 / n + drain region 24 as in FIG.

  In addition, a GaN-based FET or the like can be applied to the semiconductor device 100 (Q1 and Q4) applicable to the power circuit 1 according to the first embodiment instead of the SiC-based MISFET.

  Either a SiC-based power device or a GaN-based power device can be applied to the semiconductor device 100 (Q1 and Q4) applicable to the power circuit 1 according to the first embodiment.

  Furthermore, the semiconductor device 100 (Q1 · Q4) applicable to the power circuit 1 according to the first embodiment can use a semiconductor having a band gap energy of 1.1 eV to 8 eV, for example.

(Electric field distribution)
Since SiC devices have a high breakdown field (for example, about 3 MV / cm, about 3 times that of Si), the drift layer is made thinner and the impurity density is set higher than that of Si. Can withstand pressure. FIG. 4A is a comparison between the Si device and the SiC device, and a schematic diagram of the p body region 28 and the n ⁻ drift layer 26 of the Si MISFET is represented as shown in FIG. 4A, and the p body region 28 and n of the SiC MISFET A schematic diagram of the drift layer 26N is expressed as shown in FIG. Moreover, the electric field strength distribution corresponding to FIG. 4A and FIG. 4B is schematically represented as shown in FIG.

As shown in FIG. 4C, the peak electric field strength E _p2 of the Si MISFET is a position at a distance X1 measured from the junction interface of the p body region 28 / n ⁻ drift layer 26, that is, the surface of the p body region 28. can get. Similarly, the peak electric field intensity E _p1 of the SiC MISFET is obtained at the position of the distance X1 measured from the junction interface of the p body region 28 / n drift layer 26N, that is, the surface of the p body region 28. Due to the difference in the breakdown electric field, the peak electric field intensity E _p1 of the SiC MISFET can be set higher than the peak electric field intensity E _p2 of the Si MISFET.

The spread width of the depletion layer of the Si MISFET is in the range of distances X1 to X3 measured from the surface of the p body region 28, whereas the spread width of the depletion layer of the SiC MISFET is the surface of the p body region 28. It is the range of distance X1-X2 measured from. For this reason, the required thickness of the n ⁻ drift layer is small, and the resistance value of the n ⁻ drift layer can be reduced and the on-resistance R _on can be reduced due to the merits of both the impurity density and the film thickness. Can be reduced (smaller chip). Further, since the MISFET structure which is a unipolar device can be used, a breakdown voltage comparable to that of a Si IGBT can be realized, so that a high breakdown voltage and high-speed switching can be realized, and a reduction in switching loss can be expected.

  On the other hand, increasing the concentration and thinning of the drift layers 26 and 26N (X2 <X3) has a demerit that it is difficult to reduce the output capacitance and the feedback capacitance by limiting the depletion layer expansion width.

Furthermore, this disadvantage is particularly noticeable in SiC TMISFETs that do not have a junction FET (JFET: Junction FET) structure in the current path, and the trade-off is the reduction of on-resistance R _on and the ease of erroneous turn-on. It is turned off, and the high-speed response of the SiC MISFET is hindered.

  According to the power circuit 1 according to the first embodiment, in a circuit in which at least one SiC-based MISFET is electrically connected, at least one of the transistors cannot be controlled by a switching operation other than intended. It is possible to prevent the phenomenon of oscillation that repeats on / off.

  According to the first embodiment, in particular, in a circuit in which at least one or more SiC-based MISFETs are electrically connected, parasitic oscillation is suppressed, and a power circuit and a power circuit having a high-speed switching performance are mounted. Modules can be provided.

(Gate false ON and drain surge voltage)
An explanatory diagram of the parasitic effect of the semiconductor device Q applicable to the power circuit 1 according to the first embodiment is expressed as shown in FIG. 5A, and an explanation of the oscillation waveform of the drain-source voltage V _ds. The figure is represented as shown in FIG.

In FIG. 5A, C _gs represents a gate-source capacitance, C _ds represents a drain-source capacitance, C _gd represents a gate-drain capacitance, and I _d represents a drain current. The gate-drain capacitance C _gd is equal to the feedback capacitance C _rss of the semiconductor device Q. L _GP and L _SP represent the parasitic inductance associated with the gate terminal G and the source terminal S. As shown in FIG. 5A, in a short circuit state between the gate and the source, the inductance component existing in the closed circuit between the gate and the source is L _GP + L _SP .

When the drain voltage V _ds changes in this gate-source short-circuit state, the parasitic gate resistance and the inductance component L _GP + L _SP of the semiconductor device Q exist in the short-circuit wiring, so the gate-source instantaneously in the transient response. If a partial pressure is generated in the capacitance C _gs and it exceeds the gate threshold, an erroneous ON (false ignition) occurs.

A phenomenon in which the gate is erroneously turned on (false ignition) due to the drain voltage change dV _ds / dt is likely to occur when a switching element having a small C _gs : C _gd ratio is switched at high speed.

The drain surge voltage ΔV when the drain current is converged, represented by -L (dI _d / dt), becomes a vibration waveform as shown in FIG. 5 (b), when the drain surge voltage ΔV is too MISFET Can be a source of noise. Here, L represents the combined parasitic inductance of the main circuit portion (half bridge and power supply circuit (entire portion composed of a power supply and a capacitor)).

  An explanatory diagram of the parasitic effect between the gate and the source of the SiC MISFET Q1 applicable to the power circuit 1 according to the first embodiment is expressed as shown in FIG. 6A, and is a distributed constant circuit between the gate and the source. The explanatory diagram is expressed as shown in FIG. 6B, and the equivalent circuit diagram of the gate-source distributed constant circuit is expressed as shown in FIG. 6C.

Between the gate and source of the SiC MISFET Q1 applicable to the power circuit 1 according to the first embodiment, as an inductance component, a parasitic inductance L _GP1 between the gate terminal GT1 and the gate G1, a source sense terminal SST1, and a source sense SS1. There is a parasitic inductance L _SP1 between them, and there are parasitic capacitances C _GP and C _GP as capacitance components. Specifically, as shown in FIG. 6B, these inductance component / capacitance component can be expressed by a distributed constant circuit including a distributed gate inductance l _gp , a distributed source inductance l _sp and a distributed gate capacitance C _gp. . That is, the distributed constant circuit shown in FIG. 6B corresponds to the gate-source equivalent circuit shown in FIG. An equivalent circuit of such a distributed constant circuit is arranged between the gate and source of the SiC MISFET Q1, as shown in FIG.

(Oscillation phenomenon)
In the power circuit 1 according to the first embodiment using the SiC MISFET, a circuit diagram for explaining the oscillation phenomenon occurring is expressed as shown in FIG.

  In the configuration of FIG. 7, the problem of oscillation occurring in the inductive load switching evaluation of the half-bridge built-in module using the SiC TMISFET is described.

As shown in FIG. 7, in the half bridge circuit configuration of the first MISFET Q1 and the second MISFET Q4, the power supply voltage E, the electric field capacitor _CE, and the collective snubber capacitor C1 are connected between the positive power terminal P and the negative power terminal N. ing. Here, a load inductance L1 is connected between the drain and source of the first MISFET Q1 on the reflux side (high side), the gate and source of the first MISFET Q1 are short-circuited at the signal terminal portion, and the first MISFET Q1 is turned off. In the state, a gate drive voltage was applied from the gate driver 50 between the gate and source of the second MISFET Q4 on the drive side (low side).

  Here, the power supply voltage E = 100V, the load inductance L1 = 500 μH, the gate drive voltage = 18V / 0V, and the external gate resistance is 0Ω.

Under the above conditions, waveform examples of gate-source sense voltages V _gs , H · V _gs , L after applying gate drive voltage, waveform examples of drain-source voltages V _ds , H · V _ds , L, A waveform example of the drain currents I _d , H · I _d , and L is expressed as shown in FIG. In FIG. 8, gate-source sense voltages V _gs , H · V _gs , L are 20 V / div, drain-source voltages V _ds , H · V _ds , L are 100 V / div, drain current I _d , H · I _d and L are 50 A / div.

Here, V _gs , H represents the gate-source sense voltage of the high-side first MISFET Q1, and V _gs , L represents the gate-source sense voltage of the low-side second MISFET Q4. V _ds , H represents the drain-source voltage of the high-side first MISFET Q1, and V _ds , L represents the drain-source voltage of the low-side second MISFET Q4. I _d , H represents the drain current (source → drain direction) of the first MISFET Q1 on the high side, and I _d , L represents the drain current (drain → source direction) of the second MISFET Q4 on the low side.

As shown in FIG. 8, when the low-side second MISFET Q4 is turned on, a phenomenon (oscillation) in which the gate of the high-side first MISFET Q1 that should be kept off repeatedly turns on / off unintentionally occurs. This phenomenon shows different waveforms depending on the parasitic inductance and parasitic capacitance of each part in the circuit, but the whole phenomenon occurring due to the same cause is targeted regardless of the shape of each waveform. Further, the drain-source voltage V _ds , H of the first MISFET Q1 on the high side is applied with a surge voltage that is 2 to 4 times the power supply voltage E = 100V, and the power supply voltage E has a larger value. In this case, the device is easily destroyed.

Further, I _d , H represents the drain current (source → drain direction) of the first MISFET Q1 on the high side, and I _d , L represents the drain current (drain → source direction) of the second MISFET Q4 on the low side. As shown in FIG. 5, an arm short-circuit current between the first MISFET Q1 on the high side and the second MISFET Q4 on the low side is observed.

―Target power circuit―
The power module including the power circuit 1 according to the first embodiment can be applied to a module for a power supply circuit in which a bridge structure such as a half bridge circuit, a full bridge circuit, or a three-phase bridge circuit is incorporated. In the full bridge circuit, a two-phase inverter can be configured, in the three-phase bridge circuit, a three-phase AC inverter can be configured, and the same configuration can be achieved by using a plurality of half-bridge circuits.

  A schematic circuit configuration of a three-phase AC inverter to which the power circuit 1 according to the first embodiment using an SiC MISFET can be applied is expressed as shown in FIG.

  As shown in FIG. 9, the three-phase AC inverter includes a gate driver 50, a power module unit 52 connected to the gate driver 50, and a three-phase AC motor 54. The power module unit 52 is connected to U-phase, V-phase, and W-phase inverters corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor 54. Here, the gate driver 50 is connected to the SiC MISFETs Q1 and Q4, the SiC MISFETs Q2 and Q5, and the Q3 and Q6.

  In the power module unit 52, inverter-configured SiC MISFETs Q1 and Q4, Q2 and Q5, and Q3 and Q6 are connected between a positive power terminal P and a negative power terminal N to which the power supply voltage E is connected. Further, diodes (not shown) are connected in antiparallel between the sources and drains of the SiC MISFETs Q1 to Q6.

  In the configuration of FIG. 9, the problem of oscillation occurring in the power module for a three-phase AC inverter using SiC MISFET is described.

  Also in the configuration of FIG. 9, the same oscillation problem as the phenomenon described in FIGS. That is, also in the configuration of FIG. 9, when the switching element of one arm is turned on during the dead time in the state where the switching elements of the first MISFET Q1 on the high side of the half bridge and the second MISFET Q4 on the low side are connected, FIG. -Oscillation problems similar to those described in 8 can occur. Such an operation mode includes a corresponding operation mode even during continuous operation. In addition, the higher the switching speed, the more likely it is.

  It can be generated not only by a three-phase inverter but also by a converter using synchronous rectification.

In a half-bridge circuit, a full-bridge circuit, or a three-phase bridge circuit, etc., when a converter or inverter is operated, when the switching element of one arm is turned on from the dead time state, the gate caused by the drain voltage change dV _ds / dt The phenomenon of erroneous turn-on (false spot) is likely to occur when switching a switching element having a small ratio between the gate-source capacitance C _gs and the gate-drain capacitance C _gd at high speed.

-Oscillation trigger and energy source-
In the power circuit according to the first embodiment using the SiC MISFET, the circuit diagram for explaining the oscillation trigger in the oscillation phenomenon is expressed as shown in FIG. 10A and describes the energy supply source during the oscillation. The circuit diagram to be expressed is expressed as shown in FIG.

In the power circuit 1 according to the first embodiment, as shown in FIG. 10A, the oscillation trigger in the oscillation phenomenon is an abrupt drain of the first MISFET Q1 on the high side accompanying the ON operation of the second MISFET Q4 on the low side. This occurs when the threshold voltage of the first MISFET Q1 is exceeded due to an increase in the gate-source sense voltage V _gs , H due to the source-to-source voltage change dV _ds , H / dt, and the positive power terminal P / negative power A current that short-circuits between terminals N flows.

Although between the high side of the 1MISFETQ1 gate source are short-circuited, the parasitic gate resistance and parasitic inductance L _G is present, the voltage between the first 1MISFETQ1 drain source is applied, also between the gate and the source moment Thus, the drain-source voltage change dV _ds , H / dt is divided and applied. That is, when the drain-source voltage suddenly changes (increases) in the first MISFET Q1, the gate-source sense voltage V _gs , H is also increased.

In the power circuit 1 according to the first embodiment, the energy supply source during oscillation is as shown in FIG. 10B when the short-circuit current converges due to resonance of the gate-source sense voltage V _gs , H. A part of the energy stored as the drain voltage surge is generated by flowing into the gate-source capacitance C _gs through ringing in the closed loop LP1. That is, the injection current I _i flows into the gate-source capacitance C _gs , a negative voltage is applied between the gate and source of the first MISFET Q1, and the voltage oscillates in the closed loops LP1 and LP2, thereby turning on again. The energy during oscillation is supplied every time the short circuit converges. An example of the ringing waveform of the drain-source voltage V _ds, H of the first MISFET Q1 is as shown in FIG.

The device and module characteristics that are likely to be erroneously turned on are that the gate threshold is low, the parasitic gate resistance and the parasitic inductance of the gate-source short-circuit closed loop LP2 are large, the gate-source capacitance C _gs and the gate-drain capacitance C _gd . The ratio is small.

  On the other hand, the device and module characteristics in which oscillation tends to continue are that the parasitic inductance of the short-circuited closed loop LP2 between the gate and source is large, and the parasitic inductance of the closed loop LP1 that supplies a short-circuit current when erroneously turned on.

The SiC MISFET essentially has a small ratio between the gate-source capacitance C _gs and the gate-drain capacitance C _gd . In particular, SiC TMISFET does not have a junction FET (JFET) in the current path, and since the on-resistance R _on is low, the gate-source sense voltage for allowing the same drain current to flow is lower, resulting in a combination of false on and oscillation energy supply. The phenomenon tends to appear remarkably.

  The effect of suppressing malfunction and parasitic oscillation in the power circuit 1 according to the first embodiment is basically assumed after an erroneous ON due to a drain voltage change has occurred.

In the power circuit 1 according to the first embodiment, connecting the gate diode D _G1 between the first gate G1 · first source sense SS1 of the 1MISFETQ1. Turns on the gate diode D _G1 when the voltage in the negative direction is applied to the gate of the 1MISFETQ1, to form a low-impedance current path to the gate G1 · source sense SS1 between short lines, the signal terminals having a large parasitic inductance The discharge is performed from the source sense SS1 to the gate G1 through a path that does not include GT1 and SST1. As a result, the negative charge to the gate-source capacitance C _gs and the oscillation of the gate voltage are suppressed so that the erroneous turn-on does not occur.

In the power circuit 1 according to the first embodiment, the gate diode D _G1, in order to operate the passive to the movement of the gate voltage, there is no time delay through the IC in case of applying the IC control. Therefore, it is possible to respond to a phenomenon that occurs in an extremely short time. Furthermore, since it is not necessary to increase the number of new control terminals, the function can be obtained without impairing the merit of downsizing the entire module.

  The above measures lead to taking advantage of the SiC power module equipped with a unipolar switching element as a technique for suppressing gate oscillation without impairing high-speed switching performance.

(Explanation of simulation effect)
In the power circuit 1 according to the first embodiment, a circuit diagram for explaining an operation simulation when a gate diode as a control circuit is not connected is expressed as shown in FIG.

As shown in FIG. 11A, in the half bridge configuration of the first MISFET Q1 and the second MISFET Q4, a power supply voltage E, an electric field capacitor C _E, and a snubber capacitor C1 are connected between the positive power terminal P and the negative power terminal N. Has been. A parasitic inductance L _E is connected to the power supply voltage E, a parasitic inductance L _CE is connected to the electric field capacitor C _E , and a parasitic inductance L _C1 is connected to the snubber capacitor C1. Here, a load inductance L1 is connected between the drain and source of the first MISFET Q1 on the high side, the gate and source of the first MISFET Q1 are short-circuited at the signal terminal portion, and in a state where the first MISFET Q1 is turned off, A gate drive voltage was applied from the gate driver 50 between the gate and source of the second MISFET Q4 on the side.

  Here, the power supply voltage E = 100V, the load inductance L1 = 500 μH, the gate drive voltage = 18V / 0V, and the external gate resistance is 0Ω.

Under the above conditions, waveform examples of gate-source sense voltages V _gs , H · V _gs , L after applying gate drive voltage, waveform examples of drain-source voltages V _ds , H · V _ds , L, A waveform example of the drain currents I _d , H · I _d , and L is expressed as shown in FIG. In FIG. 11B, gate-source sense voltages V _gs , H · V _gs , L are 20 V / div, drain-source voltages V _ds , H · V _ds , L are 50 V / div, drain current. I _d , H · I _d , and L are 25 A / div.

As shown in FIG. 11B, when the low-side second MISFET Q4 is turned on, a phenomenon occurs in which the gate of the high-side first MISFET Q1 that should be kept off repeatedly turns on / off unintentionally. Further, the drain-source voltage V _ds , H of the first MISFET Q1 on the high side is applied with a voltage more than twice the power supply voltage E = 100V, and when the power supply voltage E is a larger value, It easily leads to device destruction.

Further, I _d , H represents the drain current (source → drain direction) of the first MISFET Q1 on the high side, and I _d , L represents the drain current (drain → source direction) of the second MISFET Q4 on the low side. As shown in (b), a short-circuit current between the arms of the first MISFET Q1 on the high side and the second MISFET Q4 on the low side flows.

In the power circuit according to the first embodiment using SiC TMISFET, circuit diagram illustrating the operation simulation of the case where a gate connected diode D _G1 of the control circuit is expressed as shown in FIG. 12. 12, the gate diode D _G1 of the control circuit is connected between the high-side first 1MISFETQ1 gate source. Other configurations are the same as those in FIG.

In FIG. 12, examples of waveforms of gate-source sense voltages V _gs , H · V _gs , L after applying a gate drive voltage, waveform examples of drain-source voltages V _ds , H · V _ds , L, and A waveform example of the drain currents I _d , H · I _d , L is expressed as shown in FIG. In FIG. 13A, gate-source sense voltages V _gs , H · V _gs , L are 20 V / div, drain-source voltages V _ds , H · V _ds , L are 50 V / div, drain current. I _d , H · I _d , and L are 25 A / div.

As shown in FIG. 13A, when the low-side second MISFET Q4 is turned on, the phenomenon of repeating on / off at the gate of the high-side first MISFET Q1 that should be kept off is suppressed. Further, the occurrence of a surge voltage in the drain-source voltage V _ds , H of the high-side first MISFET Q1 is also suppressed.

  Further, as shown in FIG. 13A, the conduction of the short-circuit current between the arms of the first MISFET Q1 on the high side and the second MISFET Q4 on the low side is suppressed.

If a gate connected diode D _G1 as the control circuit when not connected gate-source sense voltage V _gs (Figure 12), waveform example H (solid line) gate diode D _G1 (FIG. 11 (a)) A waveform example (broken line) of the gate-source sense voltage V _gs , H is expressed as shown in FIG.

A waveform example (broken line) of the gate-source sense voltage V _gs , H in the case where the gate diode _DG1 is not connected (FIG. 11A) is shown in FIG. 12B as the low-side second MISFET Q4. on-time, a phenomenon that first 1MISFETQ1 gate of off continuity to be high side repeats unintentional on / off is occurring, the gate-source sense voltage when connecting the gate diode D _G1 (FIG. 12) In the waveform example (solid line) of V _gs , H, the phenomenon of repeating ON / OFF at the gate of the first MISFET Q1 on the high side that should be kept off is suppressed. In particular, the waveform example (solid line) of the gate-source sense voltage V _gs , H is clamped at about −0.5V. This value reflects the value of the forward voltage of the gate diode _DG1 .

Further, in the power circuit 1, a circuit diagram for explaining an operation simulation when the gate and the source of the first MISFET Q1 on the high side are short-circuited by the active mirror clamping transistor Q _M1 is expressed as shown in FIG. In FIG. 13A, waveform examples of gate-source sense voltages V _gs , H · V _gs , L, drain-source voltages V _ds , H · V _ds , L, and drain current I _d , H · I _d , L waveform examples are expressed as shown in FIG. In FIG. 14B, the gate-source sense voltages V _gs , H · V _gs , L are 20 V / div., And the drain-source voltages V _ds , H · V _ds , L are 50 V / div. The drain currents I _d , H · I _d , and L are 25 A / div. Even when the gate and source of the high-side first MISFET Q1 are short-circuited by the active mirror clamping transistor Q _M1 , the phenomenon of repeated on / off at the gate of the high-side first MISFET Q1 to be kept off is suppressed. In particular, since the gate-source sense is already short-circuited with a low inductance when the drain-source voltage V _ds , H of the high-side first MISFET Q1 suddenly changes due to the ON operation of the low-side second MISFET Q2, the high-side The increase in the gate-source sense voltage V _gs , H of the first MISFET Q1 and the short circuit time are suppressed. Further, the generation of a surge voltage in the drain-source voltage V _ds , H of the high-side first MISFET Q1, the reverse voltage surge to the gate-source sense voltage, and the high-side first MISFET Q1 and the low-side second MISFET Q4 arm. Short-circuiting is also suppressed. An example in which the active mirror clamping transistor Q _M1 is applied will be described in detail in the power circuit 1 according to the second embodiment shown in FIG.

  As described above, according to the first embodiment, during the operation of the power circuit constituted by the MISFET, a power circuit that suppresses erroneous ON or erroneous ON to parasitic oscillation and is miniaturized and has high-speed switching performance. In addition, a power module equipped with a power circuit can be provided.

(Power module)
In the power module 2 mounted with the power circuit 1 according to the first embodiment, in the half-bridge built-in module, a schematic planar pattern configuration before forming the resin layer 120 is expressed as shown in FIG. A schematic bird's-eye view configuration after forming the resin layer 120 is expressed as shown in FIG. The power module 2 according to the first embodiment has a configuration of a half-bridge built-in module. That is, two MISFETs Q1 and Q4 are built in one module.

  The circuit configuration of the power module 2 shown in FIG. 15 corresponds to the power circuit 1 shown in FIG. FIG. 15 shows an example in which MISFETs Q1 and Q4 are arranged in parallel in four chips.

  As shown in FIGS. 15 and 16, the power module 2 according to the first embodiment includes a positive power terminal P and a negative side arranged on the first side of the ceramic substrate 10 covered with the resin layer 120. A power terminal N, a gate terminal GT1 and a source sense terminal SST1 disposed on a second side adjacent to the first side, an output terminal O disposed on a third side opposite to the first side, A gate terminal GT4 and a source sense terminal SST4 are provided on a fourth side opposite to the second side. Here, the gate terminal GT1 and the source sense terminal SST1 are connected to the gate signal wiring pattern GL1 and the source signal wiring pattern SL1 of the MISFET Q1, and the gate terminal GT4 and the source sense terminal SST4 are connected to the gate signal wiring pattern GL4 of the MISFET Q4. Connected to the source signal wiring pattern SL4.

As shown in FIG. 15, the gate wire GW1-GW 4 toward the MISFET Q1-Q4 to the signal substrate 14 ₁ - 14 ₄ arranged gate signal wiring pattern on GL1-GL4 and source sense signal wiring pattern SL1-SL4 The source sense wires SSW1 and SSW4 are connected. Further, gate terminals GT1 and GT4 and SST1 and SST4 for external extraction are connected to the gate signal wiring patterns GL1 and GL4 and the source sense signal wiring patterns SL1 and SL4 by soldering or the like.

As shown in FIG. 15, a gate diode _DG1 is connected to the gate signal wiring pattern GL1 and the source sense signal wiring pattern SL1 by soldering or the like so as to straddle the signal wiring pattern. Similarly, a gate diode _DG4 is connected to the gate signal wiring pattern GL4 and the source sense signal wiring pattern SL4 by soldering or the like so as to straddle the signal wiring pattern. Therefore, when the gate diodes D _G1 and D _G4 operate, the current flowing from the source senses SS1 and SS4 toward the gates G1 and G4 is not included in the module including the gate terminals GT1 and GT4 for external extraction and SST1 and SST4. Only through the low inductance path. As shown in FIG. 1 and FIG. 15, the gate diodes D _G1 and D _G4 work effectively because they are connected on the wiring not including the main circuit wiring. The signal boards 14 ₁ and 14 ₄ are connected to the main board 10 by soldering or the like.

As shown in FIG. 15, the power module 2 according to the first embodiment may include a snubber capacitor C _B that is electrically connected between the positive side power terminal P · negative power terminal N.

Further, in the power module 2 according to the first embodiment, a schematic bird's-eye view configuration after forming the upper surface plate electrodes 22 ₁ and 22 ₄ and before forming the resin layer 120 is expressed as shown in FIG. The sources S1 and S4 of the MISFETs Q1 and Q4 arranged in parallel in the four chips are connected in common by the upper surface plate electrodes 22 ₁ and 22 ₄ . In FIG. 17, the gate wires GW1 and GW4 and the source sense wires SSW1 and SSW4 are not shown.

In the power module 2 according to the first embodiment, variation in the distance between the control circuit (gate diodes D _G1 and D _G4 ) and the MISFETs Q1 and Q4 can be suppressed, and the influence of the parasitic inductance can be controlled.

  Although not shown in FIGS. 1 and 15 to 19, diodes may be connected in antiparallel between D1 and S1 and between D4 and S4 of MISFETs Q1 and Q4.

In the example shown in FIGS. 15 to 19, the sources S1 and S4 of the MISFETs Q1 and Q4 arranged in parallel in four chips are connected in common by the upper surface plate electrodes 22 ₁ and 22 ₄ . source each other instead of _1, 22 ₄ may be conductive wire.

  The positive side power terminal P, the negative side power terminal N, the gate terminals GT1 and GT4 for external extraction, and the SST1 and SST4 can be formed of Cu, for example.

The main substrate 10 and the signal substrates 14 ₁ and 14 ₄ can be formed of ceramic substrates. The ceramic substrate may be made of, for example, Al ₂ O ₃ , AlN, SiN, AlSiC, or at least a surface of insulating SiC.

The main wiring conductor (electrode pattern) 12 · 12 ₀ · 12 ₁ · 12 ₄ · 12 _n can be formed of, for example, Cu, Al or the like.

The electrode pillars 20 ₁ and 20 ₄ and the upper surface plate electrodes 22 ₁ and 22 ₄ that connect the sources S1 and S4 of the MISFETs Q1 and Q4 and the upper surface plate electrodes 22 ₁ and 22 ₄ are formed of, for example, CuMo, Cu, or the like. Also good. When materials of the same size having the same value of the coefficient of thermal expansion (CTE) are compared, the generated stress is larger in a material having a larger Young's modulus value. For this reason, a member with a small value of generated stress can be achieved by selecting a material having a smaller value of Young's modulus × CTE. CuMo has such advantages. Moreover, although CuMo is inferior to Cu, its electrical resistivity is relatively low. Further, the separation distance along the surface between the upper surface plate electrodes 22 ₁ and 22 ₄ is called a creepage distance. The value of the creepage distance is, for example, about 2 mm.

  The gate wires GW1 and GW4 and the source sense wires SSW1 and SSW4 can be formed of, for example, Al or AlCu.

  As the MISFETs Q1 and Q4, SiC power devices such as SiC DIMISFET and SiC TMISFET, or GaN power devices such as GaN high electron mobility transistors (HEMT) can be applied. In some cases, power devices such as Si-based MISFETs and IGBTs are also applicable.

As the gate diodes D _G1 and D _G4 , Si-based SBDs and Zener diodes, and SBDs and Zener diodes using wide-gap semiconductors such as SiC-based or GaN-based are applicable.

  As the snubber capacitor connected between the positive power terminal P and the negative power terminal N, a ceramic capacitor or the like can be applied.

  Moreover, as the resin layer 120, transfer mold resin, thermosetting resin, etc. applicable to a SiC type semiconductor device can be used. Further, a silicone resin such as silicon gel may be applied partially or entirely by using a case type power module.

(Modification)
In the power module 2 according to the modification of the first embodiment, a schematic planar pattern configuration before the resin layer 120 is formed is represented as shown in FIG. 18, and a schematic bird's-eye configuration after the resin layer 120 is formed. Is expressed as shown in FIG. In the power module 2 according to the modification of the first embodiment, bonding wires BW _S1 and BW _S4 are used instead of the upper surface plate electrodes 22 ₁ and 22 ₄ . That is, as shown in FIG. 18, between the source pad electrode SP1 and the electrode patterns 12 ₄ MISFETQ1 is connected via a bonding wire BW _S1, the source pad electrode SP4 and the electrode patterns 12 _n of MISFETQ4 (EP) is It is connected via a bonding wire BW _S1. The bonding wires BW _S1 and BW _S4 can be formed of, for example, Al or AlCu.

The distance between the signal substrates 14 ₁ and 14 ₄ and the MISFETs Q1 and Q4 is, for example, about 2 mm apart. This is because the bonding wires BW _S1 and BW _S4 are set short.

The power module 2 according to the modification of the first embodiment includes snubber capacitors C _B and C _B connected between the positive power terminal P and the negative power terminal N, as shown in FIG. May be.
The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

[Second Embodiment]
(Power circuit and power module)
In the power circuit 1 according to the second embodiment, a schematic circuit configuration of the half bridge circuit is represented as shown in FIG. The power circuit 1 according to the second embodiment is not limited to the half bridge circuit, and can be applied to a full bridge circuit, a three-phase bridge circuit, or the like.

  Further, in the power module 2 on which the power circuit 1 according to the second embodiment is mounted, the schematic planar pattern configuration before forming the resin layer 120 in the half-bridge built-in module is expressed in the same manner as in FIG. The

  In addition, the power module 2 according to the second embodiment can have the same configuration as that of the configuration example (FIGS. 15 to 19) of the power module 2 according to the first embodiment and its modification. .

In the power circuit 1 according to the second embodiment and the power module 2 equipped with the power circuit 1, as shown in FIG. 20, an active mirror is used instead of the gate diodes D _G1 and D _G4 in the first embodiment. Clamping transistors Q _M1 and Q _M4 are used.

  Further, in the power circuit 1 according to the second embodiment, an operation circuit explanatory diagram of an active mirror clamp applied as a control circuit is expressed as shown in FIG. 21A, and the operation of FIG. The waveform explanatory diagram is expressed as shown in FIG.

As shown in FIG. 21 (a), the active mirror clamping transistor Q _M1 is connected in parallel between the gate and source of the first MISFET Q1, and is complementary to the first MISFET Q1 by providing a dead time in an off state. Basically execute. That is, as shown in FIG. 21 (b), when the gate-source voltage V _gs of the active mirror clamp transistor Q _M1 'is at a high level, equal to the drain-source voltage of the active mirror clamp transistor Q _M1 When the gate-source voltage V _gs of the first MISFET Q1 becomes a low level and the gate drive signal is input while the gate-source voltage V _gs ′ of the active mirror clamping transistor Q _M1 is at the low level, the active mirror The gate-source voltage V _gs of the first MISFET Q1, which is equal to the drain-source voltage of the clamping transistor Q _M1 , becomes a high level.

In FIG. 21A, a gate resistance R _g1 · R _g2 , a pnp bipolar transistor Q _p · npn bipolar transistor Q _n and a capacitor C _i schematically represent a gate driver circuit of the first MISFET Q1. By inputting a signal to the gate terminal G _p of the pnp bipolar transistor Q _p · npn-type bipolar transistor Q _n of the inverter arrangement, it is possible to make the first 1MISFETQ1 ON / OFF drive. It may be applied to CMOS (Complementary Metal Oxide Semiconductor) FET instead of the pnp bipolar transistor Q _p · npn-type bipolar transistor Q _n.

In the power module 1 according to the second embodiment and the power module 2 equipped with the power circuit 1, an active mirror clamp that operates complementarily to the gate-source sense voltages V _gs and V _gs of the first MISFET Q1 and the second MISFET Q4 A circuit (active mirror clamping transistors Q _M1 and Q _M4 ) is provided in the module, and the corresponding active mirror clamping transistors Q _{M1 and} Q _M4 are operated during the gate-off periods of the first MISFET Q1 and the second MISFET Q4. Thus, the same effect as that of the gate diodes D _G1 and D _G4 in the first embodiment can be obtained when a negative voltage is applied to the gate-source capacitance.

The gate signal wiring pattern of the active mirror clamp transistors Q _M1 ... Q _M4 and the mirror clamp gate terminals MGT1 and MGT4 are newly required, but the diode response time is omitted as compared with the gate diodes D _G1 and D _G4. Since the effect of reducing the impedance of the short-circuit wiring can be obtained, it is possible to suppress erroneous ON due to the drain voltage change.

Further, the active mirror clamp transistor Q _M1 · · Q _M4, by disposing on the signal substrate 14 _1, 14 _4, it is possible to avoid the influence of the instantaneous heating of the semiconductor chip.

In the power circuit 1, the operation simulation when the gate and the source of the high-side first MISFET Q1 are short-circuited by the active mirror clamping transistor Q _M1 is as described in FIGS. 14 (a) and 14 (b). . When the gate and source of the high-side first MISFET Q1 are short-circuited by the active mirror clamping transistor Q _M1 , the phenomenon of repeatedly turning on / off the gate of the high-side first MISFET Q1 that should be kept off is suppressed. Particularly, when the drain-source voltage V _ds , H of the high-side first MISFET Q1 is suddenly changed due to the ON operation of the low-side second MISFET Q2, the gate-source sense is already short-circuited with a low parasitic inductance. The increase of the gate-source sense voltage V _gs , H and the short-circuit time of the first MISFET Q1 are suppressed. Further, the occurrence of a surge voltage in the drain-source voltage V _ds , H of the high-side first MISFET Q1 and the short circuit between the arms of the high-side first MISFET Q1 and the low-side second MISFET Q4 are also suppressed.

As shown in FIGS. 20 and 15, the power circuit 1 according to the second embodiment includes a plurality of MISFETs, and the first MISFET Q1 and the second MISFET Q4 on the main substrate 10 having the electrode patterns 12 ₁ , 12 _n, and 12 ₄ . The drains D1 and D4 are electrically connected to each other, and have gates G1 and G4, source senses SS1 and SS4, externally extracted signal terminals GT1 and SST1, and power terminals P and N, and at least the first MISFET Q1. A first control circuit is provided for controlling a path of a current conducted from the first source S1 toward the first gate G1.

More specifically, the power circuit 1 according to the second embodiment is arranged on the main board 10 and the main board 10 and connected to the positive power terminal P as shown in FIGS. 20 and 15. first and electrode patterns 12 _1, disposed on the main substrate 10, and the second electrode patterns 12 _n that are connected to the negative power terminal n, arranged on the main substrate 10, the first connected to the output terminal O 3 and the electrode pattern 12 _4, and the 1MISFETQ1 the first drain D1 is placed on the first electrode pattern 12 ₁ on, and the 2MISFETQ4 second drain D4 is disposed on the third electrode pattern 12 _4, of the 1MISFETQ1 A first control circuit which is connected between the first gate G1 and the first source S1 and which controls a path of a current conducted from the first source S1 toward the first gate G1.

  Further, a second control circuit may be provided that is connected between the second gate G4 and the second source S4 of the second MISFET Q4 and controls a current path that conducts from the second source S4 toward the second gate G4. .

Here, the first control circuit includes a third MISFET Q _M1 for mirror clamping in which the third drain is connected to the first gate and the third source is connected to the first source.

Further, the second control circuit includes a fourth MISFET Q _M4 for mirror clamping in which the fourth drain is connected to the second gate and the fourth source is connected to the second source.

Further, in the power circuit 1 according to the second embodiment, as shown in FIGS. 20 and 15, a part of the electrode patterns 12 ₁ , 12 _n, and 12 ₄ has a signal board 14 different from the main board 10. is disposed on _1, 14 _4, signal substrate 14 ₁ - 14 ₄ is disposed on the main board 10, the control circuit may be arranged on a signal substrate 14 _1, 14 _4. By adopting such a configuration, the control circuit is not easily affected by instantaneous heat generation of the transistor, and malfunction can be avoided.

More specifically, the power circuit 1 according to the second embodiment is arranged on the main substrate 10 and is connected to the first gate G1, similarly to FIG. 15, and the first gate signal wiring pattern GL1, A first signal mounting a first source sense signal wiring pattern SL1 connected to the first source S1 and an active mirror clamp gate signal wiring pattern MGL1 (not shown) connected to the active mirror clamp gate MG1. it may be provided with a substrate 14 _1.

Similarly to FIG. 15, the second gate signal wiring pattern GL4 disposed on the main substrate 10 and connected to the second gate G4, and the second source sensing signal wiring pattern connected to the second source S4. SL4, and the gate signal wiring pattern for the active mirror clamp connected to an active mirror clamping gate MG4 MGL4 (not shown) may be provided with a second signal substrate 14 ₄ for mounting.

Here, the first control circuit may include a third MISFET Q _M1 for active mirror clamping connected between the first gate signal wiring pattern and the first source sense signal wiring pattern.

The second control circuit may include a fourth MISFET Q _M4 for active mirror clamp connected between the second gate signal wiring pattern and the second source sense signal wiring pattern.

For an active mirror clamp circuit, the gate MG1-MG4 the MISFET Q _{M1-Q M4} for active mirror clamp also be formed on the signal substrate 14 _1, 14 ₄ can be formed compactly. In this case, three lines, that is, the gate signal of the MISFET Q ₁ · Q ₄ wiring pattern GL1 · GL4, active mirror clamp gate signal wiring pattern of the source sense signal wiring pattern _{SL1 · SL4, MISFETQ M1 · Q} M4 MGL1 · It is desirable that the MGL4 is arranged in parallel on the main substrate 10 plane and the active mirror clamp gate signal wiring patterns MGL1 and MGL4 of the MISFETs Q _M1 and Q _M4 are sandwiched between other wirings.

In the power module 1 according to the second embodiment and the power module 2 in which the power circuit 1 is mounted, the gate G1 and source sense SS1 wiring pattern in which the first MISFET is mounted (inside the signal terminals GT1 and SST1 connected to the outside) It is important to connect a third MISFET Q _M1 for active mirror clamping (a source on the source sense SS1 side and a drain on the gate G1 side) for suppressing the oscillation of the gate-source voltage. By connecting the third MISFET Q _{M1 in} this way, even when an erroneous ON occurs, the oscillation of the current flowing in the negative direction into the gate-source capacitance and the gate-source voltage is suppressed, and stable operation is performed. Can be obtained. Moreover, since it can be configured with a simple circuit, it can be miniaturized. Unlike a diode, it can be operated at all times, so that it can be operated instantaneously, and a gate-source voltage change or erroneous ON due to a change in drain-source voltage can also be suppressed.

As shown in FIG. 20, there are parasitic inductances L _GP1 and L _SP1 due to the routing of the signal terminals and electrode wirings between the externally extracted signal terminals GT1 and SST1 and the gate G1 and source sense SS1 of the first MISFET Q1. To do. Such an inductance component is present in the gate closed circuit of the first MISFET Q1, and therefore causes an operation delay in the gate drive of the first MISFET Q1.

The third MISFET Q _M1 is arranged between the gate G1 and the source sense SS1 wiring. In order to suppress the parasitic effect due to such an inductance component, the drain pad and the source of the third MISFET Q _M1 to the gate pad electrode GP and source of the first MISFET Q1. The shorter the distance to the sense pad electrode SSP, the higher the effect. Here, the gate pad electrode GP and the source sense pad electrode SSP of the first MISFET Q1 are formed on the surface of the first MISFET Q1. For this reason, the third MISFET Q _M1 may be formed in the same chip as the first MISFET Q1, or the source of the third MISFET Q _M1 may be directly soldered on the source pad electrode SP of the first MISFET Q1.

The third MISFETs Q _M1 may be arranged together for each of the first MISFETs Q1 arranged in parallel, but it is more effective that they are individually connected to each of the plurality of first MISFETs Q1.

It is important that the third MISFET Q _M1 is arranged inside the externally extracted signal terminals GT1 and SST1 having the parasitic inductances L _GP1 and L _SP1 , and the closer to the first MISFET Q1, the more effective.

However, when the third MISFET Q _M1 is directly connected to the chip of the first MISFET Q1, the temperature becomes high. Therefore, the third MISFET Q _M1 is preferably composed of a wide band gap semiconductor such as SiC or GaN having good high temperature characteristics. The above description is the same for the fourth MISFET Q _M4 for mirror clamp.

  As described above, according to the power circuit 1 according to the second embodiment, it is possible to obtain a half bridge circuit that is small and suppresses oscillation. Note that the present invention is not limited to the half bridge circuit, and the same applies to a full bridge circuit or a three-phase bridge circuit.

In addition, one of the first MISFET Q1 and the second MISFET Q2 can be configured by a SiC MISFET. Since SiC has a high breakdown electric field, it is possible to realize a low on-resistance R _on by increasing the concentration of the drift layer. However, the depletion layer expansion width to the drift layer is limited, and the feedback capacitance C _rss is reduced. Since the C _gs : C _gd ratio is poor because it is difficult to lower, and the gate erroneous ON operation due to the drain voltage change dV _ds / dt is likely to occur, by applying the power circuit 1 according to the first embodiment, Malfunctions and parasitic oscillations can be suppressed and high-speed switching performance can be ensured.

  According to the power module 2 including the power circuit 1 according to the second embodiment, a module in which the control circuit is integrated can be configured. For this reason, variation in the distance between the control circuit and the MISFET can be suppressed, and the influence of the parasitic inductance can be controlled.

(Modification)
FIG. 22 shows a schematic circuit configuration of the power circuit 1 according to the modification of the second embodiment, which is a half bridge circuit.

  Further, in the power circuit 1 according to the modification of the second embodiment, an operation circuit explanatory diagram of an active mirror clamp applied as a control circuit is expressed as shown in FIG.

In FIG. 22, the first gate for applying a negative gate bias is connected between the sources MS1 and MS4 of the third MISFET Q _M1 and fourth MISFET Q _M4 for active mirror clamping and the source senses SS1 and SS4 of the first MISFET Q1 and second MISFET Q4, respectively. A capacitor C _G1 and a second gate capacitor C _G4 are provided inside the power module. The active mirror clamp includes a first active mirror clamp source terminal MST1 and a second active mirror clamp source terminal MST4 that are electrically connected to the sources MS1 and MS4 of the third MISFET Q _M1 and the fourth MISFET Q _M4 for active mirror clamp, respectively.

Furthermore, as shown in FIG. 23, the collector side and the negative gate bias of the pnp transistor _{Q p} to the active mirror clamp signal terminal MST1 by connecting the (-V _g) Input, MISFET Q1 of including gate capacitor C _G The parasitic inductance of the gate-source sense closed loop LP3 is reduced. As a result, the signal terminal is further increased by one, but when the MISFET Q1 is in the OFF state, the active mirror clamp circuit can be utilized with low parasitic inductance while applying the gate voltage to the negative bias (−V _g ) side. This makes it possible to more effectively suppress erroneous ON operation and oscillation caused by a sudden change in the drain-source voltage.

  As described above, according to the second embodiment, during the operation of the power circuit configured by the MISFET, a power circuit that suppresses erroneous ON and erroneous induction from parasitic ON to parasitic oscillation, and is small and has high-speed switching performance. In addition, a power module equipped with a power circuit can be provided.

[Third embodiment]
(Power circuit and power module)
In the power circuit 1 according to the third embodiment, a schematic circuit configuration of a half bridge circuit is represented as shown in FIG.

  Further, in the power module 2 on which the power circuit 1 according to the third embodiment is mounted, a top view before the resin layer is formed is expressed as shown in FIG.

In the power circuit 1 according to the third embodiment, it is connected between the positive power terminal P and the negative power terminal N in order to reduce the drain voltage surge by suppressing the parasitic inductance of the short circuit current path. A snubber capacitor _CPN is provided. Although not shown, the other configuration is the same as that of the power circuit 1 according to the first to second embodiments including the control circuit.

The snubber capacitor C _PN, since the parasitic inductance of the short circuit current path is reduced, not only to suppress the drain voltage surges, reduces short-circuit time when mis-on occurs, can reduce the supply energy for oscillation continuation It is. That is, in the power circuit 1 according to the third embodiment, by incorporating a connected snubber capacitor C _PN between the positive power terminal P · negative power terminal N, it is possible oscillation suppression. The technique to incorporate a connected snubber capacitor C _PN between the positive power terminal P · negative power terminal N are equally applicable in the power circuit 1 according to the first to the second embodiment Similarly, oscillation can be suppressed.

The snubber capacitor C _PN built in the power module 2 has a size limit depending on the size of the module. If the capacitance value is small, the positive power is generated by the voltage drop at the time of ringing or short-circuit occurrence and charging from the power source to the snubber capacitor C _PN . Since the voltage between the terminal P and the negative power terminal N and the drain current vibrate and become a source of breakdown and noise, it is necessary to design the capacitance value and select the target power supply circuit. Oscillation can be more effectively suppressed by combining this method and the power circuits according to the first to third embodiments. Since the short-circuit time when an erroneous ON occurs also affects the parasitic inductance of the gate-source short circuit path, the parasitic inductance of the gate-source short circuit path may also be adjusted.

In particular, in the power module 2 equipped with the power circuit 1 according to the third embodiment, the positive power terminal P and the negative power terminal are connected from the short circuit path in order to further reduce the parasitic inductance related to the short circuit and the ringing. The device layout has been devised to exclude N. That is, as shown in FIG. 25, the extension plate 25 _{4 includes} an extension electrode 25 ₄ that extends the upper surface plate electrode 22 ₄ in the direction of the positive power terminal P, and a columnar connection electrode 18 ₁ that is disposed on the electrode pattern 12 _{1. 4-pillar} connection electrode 18 may be connected in parallel a plurality of snubber capacitors C _PN1 · C _PN2 · C _PN3 between _1. Incidentally, columnar connecting electrode ₁₈₁ can be formed in a metal column such as Cu, or may be formed as an extension of the positive power terminal P. As the snubber capacitors _CPN1 , _CPN2 , _CPN3 , ceramic capacitors can be applied.

In the power module 2 according to the third embodiment, as shown in FIG. 25, a plurality of snubber capacitors C _PN1 , C _PN2, and C _PN3 are provided directly across the extension electrode 25 ₄ and the columnar connection electrode 18 _1. By connecting them in parallel, it is possible to reduce the parasitic inductance related to short circuit and ringing. Also, by setting the top surface of the top plate lower than the top surfaces of the positive power terminal P and the negative power terminal N, a margin for arranging a plurality of snubber capacitors C _PN1 , C _PN2, and C _PN3 in parallel Can take.

(Modification 1)
FIG. 26 is a top view of the power module 2 according to the first modification of the third embodiment before forming the resin layer in the half-bridge built-in module.

  A schematic circuit configuration of the half-bridge circuit corresponding to FIG. 26, which is the power circuit 1 according to the first modification of the third embodiment, is expressed as shown in FIG.

In the power circuit 1 according to the first modification of the third embodiment, in order to reduce the drain voltage surge by suppressing the parasitic inductance of the short-circuit current path, the positive power terminal P and the negative power terminal N Snubber capacitors C _PN1 , C _PN2, and C _PN3 are connected in series.
Other configurations are the same as those of the power circuit 1 according to the third embodiment.

  In FIGS. 26 and 27, power terminal inductances LP1 and LS1 are schematically shown as parasitic inductances associated with the positive power terminal P and the negative power terminal N. Also in the power circuit 1 according to the first modification of the third embodiment, the operation excluding the power terminal inductances LP1 and LS1 as parasitic inductances associated with the positive power terminal P and the negative power terminal N is performed. Can do.

The snubber capacitors C _PN1 , C _PN2 and C _PN3 can reduce the supply energy for continuing oscillation. That is, in the power circuit 1 according to the first modification of the third embodiment, the snubber capacitors C _PN1 , C _PN2, and C _PN3 connected in series between the positive power terminal P and the negative power terminal N are incorporated. Thus, oscillation can be suppressed.

In particular, in the power module 2 equipped with the power circuit 1 according to the first modification of the third embodiment, in order to further reduce the parasitic inductance related to the short circuit and the ringing, the positive power terminal P · The module layout is devised to exclude the negative power terminal N. That is, as shown in FIG. 26, adjacent patterns TP1 and TP4 arranged adjacent to the electrode patterns 12 ₁ , 12 ₄ and 12 _n are provided, and the snubber capacitor C _PN1 is connected between the electrode pattern 12 ₁ and the adjacent pattern TP1, connect the snubber capacitor C _PN2 between adjacent patterns TP1 · TP4, connecting the snubber capacitor C _PN3 between adjacent pattern TP4 · electrode patterns 12 _n. As the snubber capacitors _CPN1 , _CPN2 , _CPN3 , ceramic capacitors can be applied.

In the power module 2 according to the first modification of the third embodiment, the snubber capacitors C _PN1 , C _PN2, and C _PN3 connected in series between the positive power terminal P and the negative power terminal N straddle between the patterns. It is possible to reduce the parasitic inductance involved. By connecting the snubber capacitors C _PN1 , C _PN2, and C _PN3 in series, the breakdown voltage of the snubber capacitors connected in series can be improved. Here, a numerical example of the snubber capacitors C _PN1 , C _PN2 , C _PN3 is, for example, about 10 nF / withstand voltage 600V, and a desired number of snubber capacitors are connected to each other while securing the withstand voltage Function can be obtained. Each snubber capacitor and the mounting pattern at this time are arranged in parallel with a part of the closed loop circuit formed by the half bridge and the snubber capacitor, so that the parasitic inductance in the closed loop is reduced, so that the effect is obtained. Strengthened. C _PN1 , C _PN2, and C _PN3 may be formed by connecting a plurality of snubber capacitors in parallel, or resistors for balancing the voltages applied to the respective capacitors may be inserted. The capacitance value may be designed to adjust the resonance frequency of the closed loop.

(Modification 2)
In the power module 2 according to the second modification of the third embodiment, the top view before the resin layer is formed in the half-bridge built-in module is represented as shown in FIG.

  A schematic circuit configuration of the half-bridge circuit corresponding to FIG. 28 in the power circuit 1 according to the second modification of the third embodiment is expressed as shown in FIG.

In the power circuit 1 according to the second modification of the third embodiment, in order to reduce the drain voltage surge by suppressing the parasitic inductance of the short-circuit current path, the positive power terminal P and the negative power terminal N An RCD snubber circuit (R _S1 · C _S1 · D _S1 and R _S4 · C _S4 · D _S4 ) is provided between them. Other configurations are the same as those of the power circuit 1 according to the third embodiment.

The RCD snubber circuit (R _S1 · C _S1 · D _S1 and R _S4 · C _S4 · D _S4 ) can reduce the supply energy for continuing oscillation. That is, also in the power circuit 1 according to the second modification of the third embodiment, the RCD snubber circuits (R _S1 · C _S1 · D _S1 and R _S4 · C are connected between the positive power terminal P and the negative power terminal N. Oscillation can be suppressed by incorporating _S4 · D _S4 ).

In particular, in the power module 2 equipped with the power circuit 1 according to the second modification of the third embodiment, in order to further reduce the parasitic inductance related to the short circuit and the ringing, the positive power terminal P · The module layout is devised to exclude the negative power terminal N. That is, as shown in FIG. 28, resistance patterns R _S1 and R _S4 are provided adjacent to the electrode patterns 12 ₁ , 12 ₄ and 12 _n , and the snubber capacitor C _S1 is interposed between the electrode patterns 12 ₁ and R _S1 . Connect the snubber capacitor C _S4 between the electrode pattern 12 ₄ and the resistance pattern R _S4 , connect the snubber diode D _S1 between the resistance pattern R _S1 and the electrode pattern 12 _4, and connect the snubber diode D _S4 to the resistance pattern R _{S4. -It} is connected between the electrode patterns _12n . Further, while the electrode pattern 12 _n · resistance pattern R _S1 is connected by bonding wires BW _R1, the resistance pattern R _S4 · electrode patterns 12 ₁ between are connected by bonding wires BW _R4. As the snubber capacitors C _S1 and C _S4 , ceramic capacitors can be applied. As the snubber diodes D _S1 and D _S4 , SBD using a wide-gap semiconductor such as Si-based SBD, SiC-based, or GaN-based can be applied.

In the power module 2 according to the second modification of the third embodiment, the RCD snubber circuit (R _S1 · C _S1 · D _S1 and R _S4 · C _S4 · It is possible to reduce the parasitic inductance involved by connecting each element across the pattern D _S4 ) or by wire connection.

(Substrate structure)
It is a board | substrate structure applied to the power module 2 which concerns on the 1st-3rd embodiment, Comprising: The typical cross-section of the signal board | substrate 14 arrange | positioned on the main board | substrate (ceramic board | substrate) 10 and the ceramic board | substrate 10 is , As shown in FIG. The signal substrate 14 can also be formed of a ceramic substrate. In this figure, a solder layer or the like for connecting the ceramic substrate 10 and the signal substrate 14 is omitted.

  The ceramic substrate 10 includes a copper plate layer 10a and a copper plate layer 10b on the front and back surfaces. The signal board 14 also includes a copper plate layer 14a and a copper plate layer 14b on the front and back surfaces. Here, the thickness of the signal board 14 is about 0.8 mm, for example, and the thickness of the copper plate layer 14a and the copper plate layer 14b is about 0.4 mm, for example, and the control circuit is spatially separated from the MISFET. It may be designed to a value that can be separated to reduce the influence of radiation noise. The copper plate layer 10b has a function as a heat spreader.

In the power module 2 according to the first to third embodiments, a shield that shields radiation noise may be provided inside the first signal board 14 ₁ or between the main board 10 and the first signal board 14 _1. . Similarly, a shield for shielding radiation noise may be provided inside the second signal board 14 ₄ or between the main board 10 and the second signal board 14 ₄ .

  A substrate structure applied to the power module 2 according to the first to third embodiments, which is disposed on a main substrate (ceramic substrate) 10 and a ceramic substrate 10 and has a shield layer 14BR inside. A schematic cross-sectional structure of 14 is expressed as shown in FIG. In this figure, a solder layer or the like for connecting the ceramic substrate 10 and the signal substrate 14 is omitted.

  It is a board | substrate structure applied to the power module 2 which concerns on the 1st-3rd embodiment, Comprising: It arrange | positions through the shield metal plate 15 on the ceramic board | substrate 10 and the ceramic board | substrate 10, and it has shield layer 14BR inside A schematic cross-sectional structure of the signal board 14 is shown as shown in FIG. In this figure, a solder layer or the like for connecting the ceramic substrate 10 and the signal substrate 14 is omitted.

In the power module 2 according to the first embodiment, the gate diode D _{G1-D G4,} by disposing on the signal substrate 14 _1, 14 _4, only to avoid the influence of the instantaneous heating of the semiconductor chip In addition, by providing the shield layer 14BR inside the signal boards 14 ₁ and 14 ₄ , it is possible to prevent malfunction of the control circuit due to the influence of radiation noise. Further, the same effect can be obtained provided with a shield metal plate 15 for shielding the radiation noise between the main board 10 of the second signal substrate 14 _4.

Similarly, in the power module 2 according to the second embodiment, the active mirror clamp transistor Q _{M1-Q M4,} by disposing on the signal substrate 14 _1, 14 _4, the semiconductor chip of instantaneous heating In addition to avoiding the influence, by providing the shield layer 14BR inside the signal boards 14 ₁ and 14 ₄ , it is possible to prevent a malfunction of the active mirror clamp gate control circuit in particular due to the influence of radiation noise. Further, the same effect can be obtained provided with a shield metal plate 15 for shielding the radiation noise between the main board 10 of the second signal substrate 14 _4. Further, the radiation noise resistance of the gate signal wiring patterns GL1 and GL4 and the source sense signal wiring patterns SL1 and SL4 is more than the effect of separating the distances.

[Fourth embodiment]
FIG. 33A shows a circuit configuration example of a power circuit according to the fourth embodiment, which is configured by a discrete device, and is a plan configuration of the power module 3 corresponding to FIG. An example is represented as shown in FIG.

In the power module 3 according to the fourth embodiment, as shown in FIG. 33 (b), the MISFET Q 1 whose drain is connected to the metal die 140 is housed in a package 150. The gate diode D _G1 is arranged in the package 150 so that the anode is connected to the source sense terminal SST1. The source pad electrode SP and the gate pad electrode GP of the MISFET Q1 are arranged on the surface side as shown in FIG.

  In the power module 3 according to the fourth embodiment, the gate G1 of the MISFET Q1 corresponds to the gate pad electrode GP, and the source sense SS1 of the MISFET Q1 corresponds to the source pad electrode SP commonly connected to the source S. Yes.

Further, in the package 150, while the source pad electrode SP · source sense terminal SST1 is connected via a bonding wire BW _S1, the gate pad electrode GP · gate terminal GT1 between is connected via a bonding wire BW _G1, source during cathode K · gate terminal GT1 gate diode D _G1 disposed on sense terminal SST1 is connected via a bonding wire BW _GS. The metal die 140 to which the drain of the MISFET Q1 is connected extends as it is to form a diode terminal DT.

Also in the power module 3 according to the fourth embodiment, the package 150, by placing in close proximity to the gate diode D _G1 to MISFET Q1, reducing the parasitic inductance involved in the gate terminal GT1 and source sense terminal SST1 Is possible.

In the power module 3 according to the fourth embodiment, when a current is conducted between the drain and the source, an inductance component between the source pad electrode SP and the source terminal ST1 is generated, and a voltage applied between the gate and the source. As a result, the switch response becomes slow, and the drain voltage change dV _ds / dt becomes small. As a result, the voltage division due to the feedback capacitance is suppressed, and the rise of the gate voltage is suppressed, so that it is difficult for the source line to be erroneously turned on by the electromotive force of the source wiring. _G1 can suppress oscillation.

  According to the fourth embodiment, it is possible to provide a power circuit and a power module in which induction from erroneous ON to parasitic oscillation is suppressed.

(Modification)
In the power module 3 according to the modified example of the fourth embodiment, a schematic bird's-eye view configuration configured by a hybrid device is represented as shown in FIG. 34 (a). In FIG. A schematic cross-sectional structure of the structure portion on which the diode is mounted is expressed as shown in FIG. The circuit configuration is expressed in the same manner as in FIG. The detailed structure of the MISFET Q1 is omitted in FIG. 34, but the structure of the SiC-based MISFET shown in FIGS. 2 and 3 is applicable.

In the power module 3 according to the modification of the fourth embodiment, as shown in FIGS. 34 (a) and 34 (b), the source pad electrode SP and the gate pad electrode GP are as shown in FIG. As shown in FIG. 5, the gate diode D _G1 is arranged with the anode connected to the source pad electrode SP of the MISFET Q1, and the cathode K of the gate diode D _G1 is connected to the MISFET Q1 via the bonding wire BW _GK. It is connected to the gate pad electrode GP.

  In the power module 3 according to the modification of the fourth embodiment, the gate G1 of the MISFET Q1 corresponds to the gate pad electrode GP, and the source sense SS1 of the MISFET Q1 is connected to the source pad electrode SP commonly connected to the source S. It corresponds.

Further, the power module 3 according to the modification of the fourth embodiment is omitted in the drawing, but is housed in the package 150 as in the fourth embodiment, and the source pad electrode SP / source sense is accommodated. during terminal SST1 it is connected via a bonding wire BW _S1, between the gate pad electrode GP · gate terminal GT1 is connected via a bonding wire BW _G1. The metal die 140 to which the drain of the MISFET Q1 is connected extends as it is to form a diode terminal DT.

Also in the power module 3 according to a modification of the fourth embodiment, the package 150, by placing in close proximity to the gate diode D _G1 to MISFET Q1, parasitic inductances involved in the gate terminal GT1 and source sense terminal SST1 Can be reduced. This control circuit may be built in another area in the same chip as MISFETQ1.

  According to the modified example of the fourth embodiment, it is possible to provide a power circuit and a power module in which induction from erroneous ON to parasitic oscillation is suppressed.

  The power circuits and power modules according to the first to fourth embodiments include HEV / EVs using SiC power modules, converters for in-wheel motors, inverters (power factor improvement for boosting from battery (PFC: Power (Factor Correction) circuit and three-phase inverter for motor drive), converters for power conditioners of solar cell systems, converters and inverters for industrial equipment, etc. In particular, the power circuits and power modules according to the first to fourth embodiments can be effectively applied to converters and inverters that require high-frequency operation and miniaturization in order to miniaturize passive elements.

  As described above, according to the present invention, it is possible to provide a power circuit with high-speed switching performance by suppressing malfunction and parasitic oscillation.

[Other embodiments]
As described above, the first to fourth embodiments have been described. However, it should be understood that the description and drawings constituting a part of this disclosure are exemplary and limit the present invention. Absent. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art. In addition, the power circuit and power that have prepared the pattern only with a metal plate or metal frame without using the main substrate, and maintained the positional relationship between the patterns, which is the role of the main substrate, such as resin sealing and insulating sheet, and insulation retention The same effect can be obtained by the same measures for modules.

  As described above, the present invention includes various embodiments not described herein.

  The power circuit of the present invention can be used for all power devices such as an SiC power module intelligent power module, and in particular, HEV / EV, converters for in-wheel motors, inverters (PFC circuits for boosting from batteries and motor driving) It can be applied to a wide range of application fields, such as three-phase inverters, step-up converters for power conditioners of solar cell systems, converters for industrial equipment, and inverters.

DESCRIPTION OF SYMBOLS 1 ... Power circuit 2, 3 ... Power module 10 ... Ceramic substrate (main substrate)
12, 12 ₀ , 12 ₁ , 12 ₄ , 12 _n ... main wiring conductor (electrode pattern)
10a, 10b, 14a, 14b ... copper plate layers 14, 14 ₁ , 14 ₄ ... signal board 14BR ... shield layer 15 ... shield metal plate 18 ₁ ... columnar connection electrodes 22, 22 ₁ , 22 ₄ ... top plate electrode 24 ... n ⁺ Drain region 25 ₄ ... extension electrodes 26, 26N ... semiconductor substrate (drift layer)
28 ... p body region 30 ... source region 32 ... gate insulating film 34 ... source electrode 36 ... drain electrodes 38, 38TG ... gate electrodes 44, 44U, 44B ... interlayer insulating film 50 ... gate driver 52 ... power module part 54 ... three phase AC motor 100, Q, Q1-Q6 ... Semiconductor device (SiC MISFET, semiconductor chip)
120 ... Resin layer Q _M1 , Q _M4 ... Active mirror clamping transistors D _G1 , D _G4 ... Gate diode BD ... Body diode D _S1 , D _S4 ... Snubber diode P ... Positive power terminal N ... Negative power terminals O, U , V, W: Output terminals GT, GT1, GT4: Gate terminals (signal terminals)
MGT1, MGT4 ... Active mirror clamp gate terminals MST1, MST4 ... Active mirror clamp source terminals SST1, SST4 ... Source sense terminals (signal terminals)
D, D1, D4 ... Drain (electrode pattern)
SS1, SS4 ... Source sense S1, S4 ... Source (electrode pattern)
GW1, GW4: gate wires SSW1, SSW4 ... source sense wires SL1, SL4 ... source sense signal wiring patterns GL1, GL4 ... gate signal wiring patterns BW _S1 , BW _S4 , BW _R1 , BW _R44 , BW _G1 , BW _GS , BW _GK ... Bonding wire SP ... Source pad electrode SSP ... Source sense pad electrode GP ... Gate pad electrode A ... Anode electrode K ... Cathode electrode EP ... Ground pattern TP1, TP4 ... Adjacent pattern electrode _Cgs ... Gate-source capacitance C _gd ... Capacitance between gate and drain C _ds ... Capacitance between drain and source C _GP ... Parasitic gate capacitance C _gp ... Distributed gate capacitance C1, C _E ... Capacitors C _B , C _PN , C _PN1 , C _PN2 , C _PN3 , C _S1, C _S4 ... snubber capacitor C _G1, C _G4 ... Over preparative negative bias capacitor _{L GP, L GP1, L GP4} ... parasitic gate inductance _{L SP, L SP1, L SP4} ... parasitic source inductance l _gp ... distribution gate inductance _{L1, L G, L E,} L CE, L C1 ... Inductances LS1, LP1 ... Power terminal inductances R _S1 , R _S4 ... Snubber resistances V _gs , V _gs , H, V _gs , L ... Gate-source sense voltages V _ds , V _ds , H, V _ds , L ... Drain _-Source -to-source voltage _Vgd ... Gate-drain voltage E ... Power supply voltage _Ii ... Inflow current _Id , H, _Id , L ... Drain current.

Claims (14)

A main board;
A first MISFET disposed on the main substrate;
A second MISFET disposed on the main substrate;
A first control circuit that is connected between a first gate and a first source of the first MISFET and controls a path of a current that is conducted from the first source toward the first gate;
A first signal substrate disposed on the main substrate and mounted with a first gate signal wiring pattern connected to the first gate and a first source sense signal wiring pattern connected to the first source; A power circuit comprising:
The first control circuit includes a third MISFET connected between the first gate signal wiring pattern and the first source sense signal wiring pattern,
The power circuit is connected to a source of the third MISFET and a source sense of the first MISFET, and includes a first gate capacitor for applying a gate negative bias. A second control circuit that is connected between the second gate and the second source of the second MISFET and controls a path of a current that is conducted from the second source toward the second gate;
A second signal substrate mounted on the main substrate and mounted with a second gate signal wiring pattern connected to the second gate and a second source sensing signal wiring pattern connected to the second source; In addition,
The second control circuit includes a fourth MISFET connected between the second gate signal wiring pattern and the second source sense signal wiring pattern,
2. The power circuit according to claim 1, wherein the power circuit is connected between a source of the fourth MISFET and a source sense of the second MISFET and includes a second gate capacitor for applying a gate negative bias.   The power circuit according to claim 1, further comprising a first inductance having one end connected to a drain end of the third MISFET.   The power circuit according to claim 2, comprising a second inductance having one end connected to a drain end of the fourth MISFET.   5. The power circuit according to claim 1, further comprising a third inductance having one end connected to one end of the first gate capacitor and a source end of the first MISFET.   5. The power circuit according to claim 2, further comprising a fourth inductance having one end connected to one end of the second gate capacitor and a source end of the second MISFET. 6. The other end of the first inductance is connected to the first terminal, the other end of the third inductance is connected to the second terminal, and the gate of the third MISFET is connected to the third terminal,
The power circuit according to claim 5, wherein a distance between the first terminal and the second terminal is longer than a distance between the second terminal and the third terminal. The other end of the second inductance is connected to the fourth terminal, the other end of the fourth inductance is connected to the fifth terminal, and the gate of the fourth MISFET is connected to the sixth terminal,
The power circuit according to claim 6, wherein a distance between the fourth terminal and the fifth terminal is longer than a distance between the fifth terminal and the sixth terminal. A seventh terminal connected to a source of the third MISFET;
The seventh terminal is disposed on an extension line between the first terminal and the second terminal, and a distance between the seventh terminal and the third terminal is between the first terminal and the second terminal. The power circuit according to claim 7, wherein the power circuit is shorter than the distance. An eighth terminal connected to the source of the fourth MISFET;
The eighth terminal is disposed on an extension line between the fourth terminal and the fifth terminal, and a distance between the eighth terminal and the sixth terminal is between the fourth terminal and the fifth terminal. The power circuit according to claim 8, wherein the power circuit is shorter than the distance.   The power circuit according to claim 7, wherein the third MISFET is disposed inside the first terminal and the second terminal.   9. The power circuit according to claim 8, wherein the fourth MISFET is disposed inside the fourth terminal and the fifth terminal.   The power circuit according to claim 1, wherein the third MISFET is connected in parallel between the first gate and the first source of the first MISFET.   The power circuit according to claim 2, wherein the fourth MISFET is connected in parallel between the second gate and the second source of the second MISFET.

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