JP2005159197A - Semiconductor module and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent characteristics of a semiconductor module from decreasing owing to a decrease in inductance of an electrode terminal in such a case. <P>SOLUTION: The semiconductor module 100 is equipped with a metal plate 1, an insulating substrate 2, and a semiconductor element 4. The insulating substrate 2 is laminated on the metal plate 1 and has a circuit pattern 3 on the surface on the opposite side from the metal plate 1. The circuit pattern 3 includes a circuit wiring part 32 and an electrode terminal part 31. The electrode terminal part 31 is connected to the circuit wiring part 32. The semiconductor element 4 is mounted on the insulating substrate 2. The semiconductor element 4 is connected to the circuit wiring part 32. The semiconductor element 4 and circuit wiring part 32 are covered with an insulator 6. The electrode terminal part 31 is exposed on the surface of the insulating substrate 2 and linearly extends. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor module and a semiconductor device.

  In the conventional semiconductor module, a circuit for controlling the operation of the semiconductor element, the voltage applied to the semiconductor element, and the like is manufactured in parallel with the manufacture of the semiconductor module. For this reason, it is necessary to change the manufacturing process of the semiconductor module every time the control circuit is changed, and there is a problem that the cost is increased.

  Therefore, a semiconductor module has been developed in which an electrode terminal different from the electrode terminal for applying a voltage is provided. The electrode terminal extends at an angle with respect to the insulating substrate, and an element having a control circuit is attached later.

  A technique for reducing inductance in a hybrid integrated circuit device is disclosed in Patent Document 1. Patent Document 2 discloses a technique that can dissipate heat generated in a main circuit in a semiconductor power module. Patent Document 3 discloses a technique for realizing a high withstand voltage and inductance reduction of a main current terminal in a semiconductor device.

JP 2000-313564 A JP 2000-133768 A JP-A-9-121019

  In the semiconductor module, circuit portions, that is, semiconductor elements, electrode terminals, and the like are covered with an insulator such as silicon gel. Silicon gel or the like expands to absorb moisture. For this reason, stress is generated in the electrode terminal, and the electrode terminal is easily deteriorated by this stress. For this reason, the intensity | strength of the electrode terminal was raised by making the shape of an electrode terminal into a bend shape. Similarly, the electrode terminal to which a control circuit element or the like can be retrofitted has also been increased in strength by being bent.

  Generally, when the shape of the electrode terminal is a bend, the inductance of the electrode terminal is increased. In particular, when the inductance of the electrode terminal to which the control circuit element can be retrofitted becomes high, the control function may be lowered. For this reason, there is a possibility that problems such as deterioration of the characteristics of the semiconductor module may occur.

  The present invention has been made in view of the above circumstances, and by reducing the inductance of the electrode terminal, it is possible to prevent the characteristics of the semiconductor module from being deteriorated due to the inductance.

  A semiconductor module according to the present invention includes a metal plate, an insulating substrate stacked on the metal plate, and having a circuit pattern on a surface opposite to the metal plate, and a semiconductor element mounted on the insulating substrate The circuit pattern includes a circuit wiring portion and an electrode terminal portion, the electrode terminal portion is linear, and the semiconductor element and the circuit wiring portion are covered with an insulator, and the electrode terminal portion One end is exposed from the periphery of the insulator.

  According to the semiconductor module of the present invention, since the electrode terminal portion is linear, the inductance is reduced. Therefore, it is possible to prevent the characteristics of the semiconductor module from being deteriorated due to inductance. Further, since the electrode terminal portion is not inclined with respect to the insulating substrate, the manufacturing cost can be reduced, the productivity can be improved, and the case can be downsized.

Embodiment 1 FIG.
FIG. 1 is a conceptual plan view of a semiconductor module according to the present embodiment. FIG. 2 is a cross-sectional view of the semiconductor module 100 shown in FIG.

  The semiconductor module 100 includes a metal plate 1, an insulating substrate 2, and a semiconductor element 4. The insulating substrate 2 is laminated on the metal plate 1 and has a circuit pattern 3 on the surface opposite to the metal plate 1. The circuit pattern 3 includes a circuit wiring part 32 and an electrode terminal part 31. The electrode terminal portion 31 is connected to the circuit wiring portion 32. The semiconductor element 4 is placed on the insulating substrate 2. The semiconductor element 4 is connected to the circuit wiring portion 32. The semiconductor element 4 and the circuit wiring part 32 are covered with the insulator 6.

  One end of the electrode terminal portion 31 is exposed on the surface of the insulating substrate 2 from the periphery of the insulator 6 and extends linearly in a direction parallel to the direction of the position AA. FIG. 1 shows a case where the electrode terminal portion 31 includes three electrode terminals 311, 312, and 313. For example, when the semiconductor element 4 includes a transistor, the electrode terminals 311, 312, and 313 may be connected to the emitter (E), the collector (C), and the base (B), respectively.

  1 and 2 show a case where the semiconductor module 100 further includes electrode terminals 51 and 52. The electrode terminals 51 and 52 are covered with the insulator 6, one of the end portions is connected to the circuit wiring portion 32, and the other is exposed on the surface of the insulator 6. The electrode terminals 51 and 52 have a bend shape.

  According to the semiconductor module 100 described above, since the electrode terminal portion 31 is linear, the inductance is reduced. Therefore, it is possible to prevent the characteristics of the semiconductor module 100 from being deteriorated due to inductance. Further, since the electrode terminal portion 31 is not inclined with respect to the insulating substrate 2, it is possible to reduce the manufacturing cost, improve the productivity, downsize the case, and the like.

  The semiconductor module 100 may be a case where the electrode terminal portion 31 includes only two electrode terminals 311 and 312 as shown in FIG. For example, when the semiconductor element 4 includes a transistor, the electrode terminals 311 and 312 may be connected to any two of the emitter (E), the collector (C), and the base (B).

Embodiment 2. FIG.
In the present embodiment, a capacitor is connected from the outside to the electrode terminal portion 31 described in the first embodiment. FIG. 4 is a circuit diagram of the semiconductor module according to the present embodiment.

  FIG. 4 shows a case where the semiconductor element 4 includes an insulated bipolar transistor (IGBT) and a free wheel diode (FWD). The IGBT has an emitter (E), a collector (C), and a gate (G), and can be understood as a transistor having a gate (G). The FWD is connected in parallel with the IGBT between the emitter and the collector.

  The electrode terminals 311 and 312 are connected to the collector (C) and the emitter (E), respectively. The hatched portions in the figure indicate that the electrode terminals 311 and 312 are exposed on the surface of the insulating substrate 2. The same applies to FIGS. 5 and 7 described in the following embodiments.

  The electrode terminals 51 and 52 are connected to the collector (C) and the emitter (E), respectively. The inductances L1 and L2 of the electrode terminals 51 and 52 are respectively shown between the electrode terminal 51 and the collector (C) and between the electrode terminal 52 and the emitter (E). For example, a power source is connected to the electrode terminals 51 and 52, and a voltage is applied to the IGBT and FWD.

  The capacitor is connected between the electrode terminals 311 and 312 in parallel with the IGBT and FWD. That is, it can be understood that the capacitor is connected to the IGBT and the FWD through the electrode terminal portion 31 including the electrode terminals 311 and 312.

  According to the above-described semiconductor module, since the capacitor is connected in parallel with the IGBT and FWD, it is possible to suppress the voltage applied to the IGBT and FWD from vibrating.

Embodiment 3 FIG.
In the present embodiment, a Zener diode is connected from the outside to the electrode terminal portion 31 described in the first embodiment. FIG. 5 is a circuit diagram of the semiconductor module according to the present embodiment. The semiconductor element 4 and the electrode terminals 51 and 52 shown in FIG. 5 have the same contents as in the second embodiment.

  The electrode terminals 311 and 312 are connected to the gate (G) and the emitter (E), respectively. Two Zener diodes connected in series in opposite directions are connected between the electrode terminals 311 and 312 in parallel with the IGBT. The Zener diode is controlled by clamping the voltage of the gate (G). That is, the Zener diode can be grasped as a circuit element connected from the outside.

  In this case, it can be understood that the semiconductor element 4 includes a transistor (IGBT) having a gate, and the circuit element is connected to the transistor through the electrode terminal portion 31 including the electrode terminals 311 and 312.

  According to the semiconductor module described above, since the Zener diode is connected in parallel to the transistor via the gate (G) and the emitter (E), it is possible to suppress a rapid change in the gate voltage due to the inductance. be able to.

Embodiment 4 FIG.
In the present embodiment, the semiconductor device includes a plurality of semiconductor modules described in the first embodiment. FIG. 6 is a plan view conceptually showing the semiconductor device according to the present embodiment.

  FIG. 6 shows a case where the semiconductor device includes two semiconductor modules 100 and 101. The semiconductor modules 100 and 101 are the same as the semiconductor module shown in FIG. However, in the semiconductor module 101, the electrode terminals 53 and 54 correspond to the electrode terminals 51 and 52, and the electrode terminals 314 and 315 included in the electrode terminal portion 31 correspond to the electrode terminals 311 and 312, respectively.

  The semiconductor modules 100 and 101 are connected via the electrode terminal part 31 with which each is provided. FIG. 6 shows a case where the electrode terminal 311 and the electrode terminal 314 and the electrode terminal 312 and the electrode terminal 315 are connected by the wiring 21 made of a copper material or the like.

  According to the semiconductor device described above, since the semiconductor module having a small inductance is provided, the inductance of the semiconductor device is also reduced.

  In the semiconductor device described above, as shown in FIG. 6, it is desirable that the semiconductor modules 100 and 101 have the electrode terminal portion 31 on the side where the counterpart is located. As a result, the semiconductor modules 100 and 101 can be connected by the shortest possible wiring 21, so that the inductance caused by the wiring can be reduced. Therefore, the inductance of the semiconductor device can be further reduced.

  FIG. 7 is a circuit diagram in the case where the semiconductor element 4 provided in each of the semiconductor modules 100 and 101 includes IGBT and FWD in the semiconductor device described above. The circuit diagram corresponding to the semiconductor modules 100 and 101 is the same as when the capacitor is omitted in the circuit diagram shown in FIG. However, in the circuit diagram corresponding to the semiconductor module 101, the inductances L3 and L4 correspond to the inductances L1 and L2.

  According to the semiconductor device shown in the circuit diagram described above, the electrode terminals 311 and 314 connected to the collector of the IGBT and the electrode terminals 312 and 315 connected to the emitter of the IGBT are connected by the wiring 21 respectively. The voltages applied to the respective semiconductor elements 4 of the semiconductor modules 100 and 101 can be made uniform.

  In any of the above-described embodiments, circuit elements can be retrofitted according to the application. Here, the circuit element indicates a capacitor in the second embodiment, a Zener diode in the third embodiment, and one semiconductor module in the third embodiment. Therefore, circuit design near the semiconductor element 4 is facilitated.

2 is a conceptual plan view of a semiconductor module described in the first embodiment. FIG. 1 is a conceptual cross-sectional view of a semiconductor module described in a first embodiment. 2 is a conceptual plan view of a semiconductor module described in the first embodiment. FIG. FIG. 3 is a conceptual circuit diagram of a semiconductor module described in a second embodiment. FIG. 5 is a conceptual circuit diagram of a semiconductor module described in a third embodiment. FIG. 10 is a conceptual plan view of a semiconductor device described in a fourth embodiment. FIG. 10 is a conceptual circuit diagram of a semiconductor device described in a fourth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Metal plate, 2 Insulating substrate, 3 Circuit pattern, 4 Semiconductor element, 31 Electrode terminal part, 32 Circuit wiring part, 100, 101 Semiconductor module.

Claims (5)

A metal plate,
An insulating substrate laminated on the metal plate and having a circuit pattern on a surface opposite to the metal plate;
A semiconductor element placed on the insulating substrate,
The circuit pattern includes a circuit wiring portion and an electrode terminal portion,
The electrode terminal portion is linear,
A semiconductor module, wherein the semiconductor element and the circuit wiring part are covered with an insulator, and one end of the electrode terminal part is exposed from the periphery of the insulator. The semiconductor element includes a transistor having a gate and a free wheel diode,
The semiconductor module according to claim 1, wherein a capacitor is connected to the transistor and the free wheel diode via the electrode terminal portion. The semiconductor element includes a transistor having a gate,
The semiconductor module according to claim 1, wherein a circuit element that clamps and controls the voltage of the gate is connected to the transistor through the electrode terminal portion. A plurality of the semiconductor modules according to claim 1,
A semiconductor device in which the semiconductor modules are connected to each other through the electrode terminal portions included in each of the semiconductor modules. The semiconductor device according to claim 4, wherein the semiconductor modules have the electrode terminal portions on at least a side where a counterpart is located.

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