CN110033741B - Multiplexing circuit and display device - Google Patents
Multiplexing circuit and display device Download PDFInfo
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- CN110033741B CN110033741B CN201910319977.2A CN201910319977A CN110033741B CN 110033741 B CN110033741 B CN 110033741B CN 201910319977 A CN201910319977 A CN 201910319977A CN 110033741 B CN110033741 B CN 110033741B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The invention provides a multiplexing circuit and a display device. The multiplexing circuit includes: the control signal output module and the multiplexing module are electrically connected with the control signal output module; the control signal output module comprises a first wire, a second wire, a resistor and a capacitor; the first end of the first wire receives a control signal, and the second end of the first wire is electrically connected with the first end of the resistor; the first end of the second wire is electrically connected with the second end of the resistor, and the second end of the second wire is electrically connected with the multiplexing module; the first end of the capacitor is electrically connected with the second end of the resistor, the second end of the capacitor is grounded, and the resistor distribution on the transmission path of the control signal is destroyed by adding the resistor, so that the peak current of the circuit can be reduced, and the stability of the circuit is improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a multiplexing circuit and a display device.
Background
A Liquid Crystal Display (LCD) has many advantages such as a thin body, power saving, and no radiation, and is widely used. Most of the existing liquid crystal display devices in the market are backlight liquid crystal display devices, which include a liquid crystal display panel and a backlight module (backlight module). The liquid crystal display panel has the working principle that liquid crystal molecules are placed in two parallel glass substrates, and the liquid crystal molecules are controlled to change directions by electrifying the glass substrates or not, so that light rays of the backlight module are refracted out to generate pictures.
Generally, a Liquid Crystal display panel is composed of a Color Filter (CF) substrate, a Thin Film Transistor (TFT) substrate, Liquid Crystal (LC) sandwiched between the Color Filter substrate and the TFT substrate, and a Sealant frame (Sealant). The thin film transistor substrate generally includes a glass substrate and a thin film transistor array formed on the glass substrate, and common thin film transistors in the prior art include an amorphous silicon (a-Si) thin film transistor, a Low Temperature Polysilicon (LTPS) thin film transistor, and an oxide semiconductor (oxide semiconductor) thin film transistor, and the oxide semiconductor thin film transistor has a high electron mobility, and compared with the Low Temperature polysilicon thin film transistor, the oxide semiconductor thin film transistor has a simple process, and has a high compatibility with the amorphous silicon thin film transistor, and thus is widely applied.
As shown in fig. 1, the conventional multiplexing circuit includes a signal source 100, a multiplexing module 200, and a capacitor 300, the signal source 100 is electrically connected to a first end of the capacitor 300 and the multiplexing module 200, a second end of the capacitor 300 is grounded, the signal source 100 is configured to provide a control signal to the multiplexing module 200 to control on and off of each signal path in the multiplexing module 200, the control signal is transmitted through a trace 400, in the prior art, at an instant when the control signal starts to be output or stops being output, an instantaneous peak current occurs on the trace 400 due to charging and discharging effects of the capacitor 300, and an amount of the peak current is far greater than a current when the circuit normally works, which may damage a circuit structure, affecting the stability of the circuit.
Disclosure of Invention
The invention aims to provide a multiplexing circuit which can reduce the peak current of the circuit and improve the stability of the circuit.
It is another object of the present invention to provide a display device having a multiplexing circuit with a small peak current and high stability.
To achieve the above object, the present invention provides a multiplexing circuit comprising: the control signal output module and the multiplexing module are electrically connected with the control signal output module;
the control signal output module comprises a first wire, a second wire, a resistor and a capacitor;
the first end of the first wire receives a control signal, and the second end of the first wire is electrically connected with the first end of the resistor;
the first end of the second wire is electrically connected with the second end of the resistor, and the second end of the second wire is electrically connected with the multiplexing module;
the first end of the capacitor is electrically connected with the second end of the resistor, and the second end of the capacitor is grounded.
The resistance value of the resistor is equal to R-R ', wherein R is the resistance of a preset reference line, R' is the sum of the resistances of the first line and the second line, the length of the reference line is equal to the sum of the lengths of the first line and the second line, and the line width is smaller than the line widths of the first line and the second line.
The line widths of the first wire and the second wire are both 30-50 μm.
The line width of the reference routing line is 6-10 mu m.
The reference wire is made of the same material as the first wire and the second wire.
The multiplexing circuit further comprises a signal source, and the first end of the first wire receives a control signal from the signal source.
The number of the control signal output modules is multiple, the multiplexing module comprises a plurality of switch units which are sequentially arranged, and each control signal output module is electrically connected with one switch unit correspondingly.
The multiplexing module also comprises an input end and a plurality of output ends respectively corresponding to the plurality of switch units;
the control end of each switch unit is electrically connected with the control signal output module corresponding to the switch unit, the first end is electrically connected with the input end of the multiplexing module, and the second end is electrically connected with the output end corresponding to the switch unit.
The switch unit is a thin film transistor.
The invention also provides a display device comprising the multiplexing circuit.
The invention has the beneficial effects that: the present invention provides a multiplexing circuit comprising: the control signal output module and the multiplexing module are electrically connected with the control signal output module; the control signal output module comprises a first wire, a second wire, a resistor and a capacitor; the first end of the first wire receives a control signal, and the second end of the first wire is electrically connected with the first end of the resistor; the first end of the second wire is electrically connected with the second end of the resistor, and the second end of the second wire is electrically connected with the multiplexing module; the first end of the capacitor is electrically connected with the second end of the resistor, the second end of the capacitor is grounded, and the resistor distribution on the transmission path of the control signal is destroyed by adding the resistor, so that the peak current of the circuit can be reduced, and the stability of the circuit is improved. The invention also provides a display device having a multiplexing circuit with small peak current and high stability.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a schematic diagram of a prior art multiplexing circuit;
FIG. 2 is a schematic diagram of a multiplexing circuit of the present invention;
fig. 3 is a schematic view of a display device according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 1, the present invention provides a multiplexing circuit, including: the device comprises a control signal output module 1 and a multiplexing module 2 electrically connected with the control signal output module 1;
the control signal output module 1 includes a first trace 10, a second trace 20, a resistor 30 and a capacitor 40;
a first end of the first trace 10 receives the control signal De, and a second end of the first trace is electrically connected to a first end of the resistor 30;
the first end of the second trace 20 is electrically connected to the second end of the resistor 30, and the second end is electrically connected to the multiplexing module 2;
the first end of the capacitor 40 is electrically connected to the second end of the resistor 30, and the second end is grounded.
Specifically, the multiplexing circuit further includes a signal source 60, and the first end of the first trace 10 receives a control signal De from the signal source 60.
It should be noted that, in the present invention, the line widths of the first trace 10 and the second trace 20 are both larger than the line width of the conventional trace, so under the condition that the material and the length are not changed, the resistances of the first trace 10 and the second trace 20 are smaller than those of the conventional trace, and increasing the line width of the trace can improve the current endurance of the trace, meanwhile, the present invention further adds a resistor 30 to compensate for the reduction of the resistance of the trace itself caused by the increase of the line width, thereby ensuring that the total resistance and the Resistance Capacitance (RC) on the control signal De transmission line are not changed.
It should be noted that, in the present invention, by increasing the line widths of the first trace 10 and the second trace 20 and adding the resistor 30, the resistor can be concentrated in the region between the capacitor 40 and the signal source 60 on the premise of ensuring that the total resistance of the circuit is not changed, so that when the control signal De starts to be output or stops being output, the peak current generated by charging and discharging the capacitor 40 is reduced, thereby preventing the circuit from being damaged due to the excessive peak current, and ensuring the stability of the circuit.
Specifically, the resistance of the resistor 30 is equal to R-R ', where R is a preset resistance of a reference trace, R' is a sum of resistances of the first trace 10 and the second trace 20, the length of the reference trace is equal to the sum of the lengths of the first trace 10 and the second trace 20, the line width is smaller than the line widths of the first trace 10 and the second trace 20, and the reference trace is also the above-mentioned conventional trace, that is, the trace before the line width is increased.
Preferably, the line widths of the first trace 10 and the second trace 20 are both 30-50 μm, and the line width of the reference trace is 6-10 μm.
Specifically, the reference trace is made of the same material as the first trace 10 and the second trace 20, and preferably, the reference trace is made of copper as the first trace 10 and the second trace 20.
Through experimental comparison, the peak current of the existing multiplexing circuit and the multiplexing circuit of the present invention shows that the total resistance of the wires in the existing multiplexing circuit is 2500 Ω, the sum of the resistances of the first wire 10 and the second wire 20 in the multiplexing circuit of the present invention is 500 Ω, the resistance value of the resistor 30 is 2000 Ω, the total resistance is equal to that of the existing multiplexing circuit, the peak current of the existing multiplexing circuit is 39.2mA, and the peak current of the multiplexing circuit of the present invention is 9.5 mA.
Specifically, as shown in fig. 2, the number of the control signal output modules 1 is multiple, the multiplexing module 2 includes multiple switch units 21 arranged in sequence, and each control signal output module 1 is electrically connected to one switch unit 21 correspondingly.
The multiplexing module 2 further includes an Input terminal and a plurality of Output terminals respectively corresponding to the plurality of switch units 21; the control end of each switch unit 21 is electrically connected to the control signal output module 1 corresponding to the switch unit 21, the first end is electrically connected to the input end of the multiplexing module 2, and the second end is electrically connected to the output end corresponding to the switch unit 21.
Preferably, the switch unit 21 is a thin film transistor, a gate of the thin film transistor is a control terminal of the switch unit 21, a source of the thin film transistor is a first terminal of the switch unit 21, and a drain of the thin film transistor is a second terminal of the switch unit 21.
Further, the control signals De received from the signal source 60 of the different control signal output modules 1 may have different waveforms, so that the respective switching units 21 are turned on at different times.
Referring to fig. 3, the present invention further provides a display device 101 including the above-mentioned multiplexing circuit 102.
In summary, the present invention provides a multiplexing circuit, including: the control signal output module and the multiplexing module are electrically connected with the control signal output module; the control signal output module comprises a first wire, a second wire, a resistor and a capacitor; the first end of the first wire receives a control signal, and the second end of the first wire is electrically connected with the first end of the resistor; the first end of the second wire is electrically connected with the second end of the resistor, and the second end of the second wire is electrically connected with the multiplexing module; the first end of the capacitor is electrically connected with the second end of the resistor, the second end of the capacitor is grounded, and the resistor distribution on the transmission path of the control signal is destroyed by adding the resistor, so that the peak current of the circuit can be reduced, and the stability of the circuit is improved. The invention also provides a display device having a multiplexing circuit with small peak current and high stability.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.
Claims (9)
1. A multiplexing circuit, comprising: the device comprises a control signal output module (1) and a multiplexing module (2) electrically connected with the control signal output module (1);
the control signal output module (1) comprises a first wire (10), a second wire (20), a resistor (30) and a capacitor (40);
the first end of the first wire (10) receives a control signal (De), and the second end of the first wire is electrically connected with the first end of the resistor (30);
the first end of the second wire (20) is electrically connected with the second end of the resistor (30), and the second end is electrically connected with the multiplexing module (2);
the first end of the capacitor (40) is electrically connected with the second end of the resistor (30), and the second end is grounded;
the resistance value of the resistor (30) is equal to R-R ', wherein R is the resistance of a preset reference line, R' is the sum of the resistances of the first line (10) and the second line (20), the length of the reference line is equal to the sum of the lengths of the first line (10) and the second line (20), and the line width is smaller than the line widths of the first line (10) and the second line (20).
2. The multiplexing circuit according to claim 1, wherein the line widths of the first trace (10) and the second trace (20) are both 30-50 μm.
3. The multiplexing circuit of claim 1 wherein the reference trace has a line width of 6-10 μm.
4. Multiplexing circuit according to claim 1 characterized in that the reference trace is of the same material as the first trace (10) and the second trace (20).
5. The multiplexing circuit of claim 1 further comprising a signal source (60), the first end of the first trace (10) receiving a control signal (De) from the signal source (60).
6. The multiplexing circuit according to claim 1, wherein the number of the control signal output modules (1) is plural, the multiplexing module (2) comprises a plurality of switch units (21) arranged in sequence, and each control signal output module (1) is electrically connected to one switch unit (21).
7. The multiplexing circuit according to claim 6 wherein the multiplexing module (2) further comprises an Input terminal (Input) and a plurality of Output terminals (Output) respectively corresponding to the plurality of switch units (21);
the control end of each switch unit (21) is electrically connected with the control signal Output module (1) corresponding to the switch unit (21), the first end is electrically connected with the Input end (Input) of the multiplexing module (2), and the second end is electrically connected with the Output end (Output) corresponding to the switch unit (21).
8. A multiplexing circuit according to claim 7 wherein the switching cells (21) are thin film transistors.
9. A display device comprising a multiplexing circuit according to any one of claims 1 to 8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910319977.2A CN110033741B (en) | 2019-04-19 | 2019-04-19 | Multiplexing circuit and display device |
| PCT/CN2019/088663 WO2020211166A1 (en) | 2019-04-19 | 2019-05-27 | Multiplexing circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910319977.2A CN110033741B (en) | 2019-04-19 | 2019-04-19 | Multiplexing circuit and display device |
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| Publication Number | Publication Date |
|---|---|
| CN110033741A CN110033741A (en) | 2019-07-19 |
| CN110033741B true CN110033741B (en) | 2020-02-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910319977.2A Active CN110033741B (en) | 2019-04-19 | 2019-04-19 | Multiplexing circuit and display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110033741B (en) |
| WO (1) | WO2020211166A1 (en) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2685135B2 (en) * | 1989-01-12 | 1997-12-03 | 富士通株式会社 | Semiconductor integrated circuit |
| US4956586A (en) * | 1989-03-03 | 1990-09-11 | Hewlett-Packard Company | Frequency independent CRT horizontal sweep generator having current feedback and improved pincushion correction circuitry |
| JP3742597B2 (en) * | 2002-01-31 | 2006-02-08 | 寛治 大塚 | Signal transmission system |
| CN202855266U (en) * | 2012-10-26 | 2013-04-03 | 京东方科技集团股份有限公司 | Pixel circuit and display device |
| CN103383834B (en) * | 2013-07-02 | 2015-08-05 | 京东方科技集团股份有限公司 | A kind of image element circuit, display panel and display device |
| CN206540959U (en) * | 2017-03-19 | 2017-10-03 | 河北工业大学 | One kind surveys capacitance variations multichannel DA-AD Acquisition Circuit |
| CN108831402B (en) * | 2018-08-24 | 2021-04-16 | 南京中电熊猫液晶显示科技有限公司 | Display device, driving method thereof and voltage adjusting method |
| CN109450420B (en) * | 2018-10-29 | 2022-06-03 | 龙迅半导体（合肥）股份有限公司 | Switching circuit and high-speed multiplexing/distributing device |
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2019
- 2019-04-19 CN CN201910319977.2A patent/CN110033741B/en active Active
- 2019-05-27 WO PCT/CN2019/088663 patent/WO2020211166A1/en active Application Filing
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| Publication number | Publication date |
|---|---|
| WO2020211166A1 (en) | 2020-10-22 |
| CN110033741A (en) | 2019-07-19 |
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