JP2766490B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device that prevents a semiconductor from being damaged by noise, surge voltage and current (hereinafter referred to as ESD) applied to the semiconductor. .

[Conventional technology]

FIG. 9 is a configuration diagram showing a protection circuit portion of a conventional semiconductor device. In this figure, 1 is a semiconductor device, 2 is an input or output pin (hereinafter referred to as an external pin), 3 is a protection circuit against ESD to the input or output pin 2, and 4 is an internal circuit of the semiconductor device 1.

Normally, since the internal circuit 4 is very easily damaged by ESD, a protection circuit 3 for weakening the energy of ESD is provided between the external pin 2 and the internal circuit 4. This protection circuit 3
For example, there is a configuration as shown in FIG.
In the example shown in the figure, two diodes 5 are used. In addition to this example, there is also a complicated configuration including a MOS transistor, a diode, a resistor, and a capacitor. Further, even if the elements included in the protection circuit 3 are not specially provided for the protection circuit, the internal circuit 4 may be deformed or parasitically formed. In the conventional example, an independent protection circuit 3 is provided for each external pin 2.

 Next, the operation will be described.

Assume that an ESD having a voltage higher than that of the external pin 2 is applied. If this application is applied directly to the internal circuit 4, the circuit will be destroyed, but the protection circuit 3 will absorb the energy of the ESD and the high voltage and protect the internal circuit 4.

On the other hand, when a signal necessary for the operation of the semiconductor device 1 is input or output to the external pin 2, the voltage is sufficiently lower than the ESD, and the operation of the semiconductor device 1 is performed without operating the protection circuit 3. There is no problem even if there is a protection circuit 3 in the.

Since it is unpredictable to which pin of the semiconductor device 1 the ESD is applied, a protection circuit 3 having exactly the same or equivalent performance is provided for each pin.

In recent years, the miniaturization of semiconductor devices has progressed, and internal circuits 4
, A sufficient protection circuit 3 is required. In order for the protection circuit 3 to absorb strong ESD energy, the area required for the protection circuit 3 must be increased.

[Problems to be solved by the invention]

Since the conventional semiconductor device is configured as described above, it is necessary to provide a protection circuit 3 having a large area for each pin in order to obtain a sufficient ESD resistance. Even if the size of the protection circuit 4 can be made small, the provision of the protection circuit 3 results in a large size, resulting in poor efficiency. Further, since the protection circuit 3 of one set of each pin is used, there is a problem that the protection circuit 3 itself is destroyed when an ESD that is higher than the ESD expected at the time of designing the protection circuit 3 is applied.

The present invention has been made in order to solve the above-described problems, and can reduce the area of the protection circuit and reduce the ESD.
It is an object to obtain a semiconductor device having a sufficiently high withstand voltage.

[Means for solving the problem]

A semiconductor device according to the present invention is a semiconductor device having a plurality of pins for connecting an internal circuit and an external signal line,
A first pin included in the plurality of pins, a first wiring connecting the first pin to the internal circuit, a second pin included in the plurality of pins, the second pin, and the internal circuit And a second wiring disposed adjacent to the first wiring and a first diffusion layer provided on a semiconductor substrate, and connected to the first wiring to form the first wiring. A first protection circuit for absorbing an abnormal voltage or current applied from a pin, and a second diffusion layer provided on a semiconductor substrate, and connected to the second wiring and connected to the second pin; A second protection circuit that absorbs an applied abnormal voltage or current, and a first protection circuit that straddles the first and second wirings and is insulated from the first and second wirings; A third arrangement for forming a capacitive coupling element for capacitively coupling with the other pins. It is characterized in that it comprises and.

Further, a plurality of the third wirings are provided.

Further, the third wiring has a structure arranged above the first and second wirings.

Further, the third wiring has a structure disposed below the first and second wirings.

A semiconductor device according to another aspect of the present invention is a semiconductor device including a plurality of pins for connecting an internal circuit and an external signal line, wherein a first pin included in the plurality of pins, A first wiring having an extension connected to the internal circuit and having a branch extending between both ends of the connection; a second pin included in the plurality of pins;
And the internal circuit are connected to each other and are disposed adjacent to the first wiring, and are branched and extended between both ends of the connection, and the extended portion is adjacent to the extended portion of the first wiring. And an abnormal voltage or current formed by a second wiring arranged in parallel with the first diffusion layer provided on the semiconductor substrate and connected to the first wiring and applied from the first pin And a second protection layer formed on a semiconductor substrate and connected to the second wiring to absorb an abnormal voltage or current applied from the second pin. A second protection circuit, and both extension portions of the first and second wirings provided on the semiconductor substrate and arranged in parallel across the first and second diffusion layers. A pair of Ms connected in series between the first pin and the second pin; And an insulating film for forming an OSFET.

Furthermore, a semiconductor device according to still another aspect of the present invention is a semiconductor device having a plurality of pins for connecting an internal circuit and an external signal line, wherein the first pin included in the plurality of pins includes the first pin and the first pin. A first wiring having a plurality of extensions formed in a comb shape by branching a pin and the internal circuit at right angles between both ends of the connection, and a second pin included in the plurality of pins; A plurality of extending portions that connect the second pin and the internal circuit and that are arranged adjacent to the first wiring and that are formed in a comb shape by branching at right angles between both ends of the connection; And a second wiring formed so that the plurality of extensions formed in the comb teeth shape and the plurality of extensions of the first wiring mesh with the comb teeth with a predetermined gap. , Formed by a first diffusion layer provided on a semiconductor substrate; A first protection circuit connected to a wiring for absorbing an abnormal voltage or current applied from the first pin, and a second diffusion layer provided on a semiconductor substrate; And a second protection circuit for connecting and absorbing an abnormal voltage or current applied from the second pin.

[Action]

According to another aspect of the present invention, a semiconductor device having a plurality of pins for connecting an internal circuit and an external signal line includes a first pin included in the plurality of pins and a first pin for connecting the first pin to the internal circuit. One wiring and a second wiring included in a plurality of pins.
, The second pin and the internal circuit, and the first
A second wiring connected adjacent to the first wiring, a first protection circuit connected to the first wiring and absorbing an abnormal voltage or current applied from the first pin, and a second protection circuit connected to the second wiring. And a second protection circuit that absorbs an abnormal voltage or current applied from the pins of the first and second lines, and connects the first wiring and the second wiring directly connected to the external signal line via a capacitive coupling element for the protection circuit. The pins are connected with a high impedance during normal operation, and the pins are connected with a low impedance when an abnormal voltage or current is applied to the pins. Even if the capacity of the protection circuit connected to each pin is reduced, sufficient ESD energy absorption capacity can be provided.
By providing energy absorption capability, internal circuits can be prevented from being destroyed by ESD energy.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a top view showing a pattern of a protection circuit portion of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit of FIG. 1 and 2, reference numerals 11a and 11b denote aluminum wirings on a semiconductor chip directly connected to different external pins, respectively. 12a and 12b are contact portions for connecting the diodes 5a and 5b provided for the protection circuit and the aluminum wirings 11a and 11b, respectively. 13 is the aluminum wiring 11
a and 11b are other insulated aluminum wirings. By providing the aluminum wiring 13, as shown in the equivalent circuit of FIG. 2, a capacitance 14a is formed between the aluminum wirings 11a and 13, and a capacitance is formed between the aluminum wirings 11b and 13. Capacity 14b
Are formed, and the external pins are capacitively coupled.

FIGS. 3 and 4 show another embodiment of the present invention.
3 (a) is a top view showing a pattern of a protection circuit portion of the semiconductor device, FIG. 3 (b) is a sectional view taken along line XX of FIG. 3 (a), and FIG. It is an equivalent circuit of FIG.
In this embodiment, the diode 5 in the protection circuit portion of each pin is used.
The aluminum wirings 11c and 11d, which are insulated from the lower substrate 16 by an insulating film 17 and connected to the aluminum wirings 11a and 11b, respectively, are arranged between the wirings a and 5b. 18a, 18b is a diffusion layer constituting the diodes 5a, 5b, 19a, 19b is the diffusion layer 18a,
This is a MOSFET in which 18b is a source / drain electrode and aluminum wirings 11c and 11d are independent gate electrodes. That is, the first and second insulating films 17 are provided on the semiconductor substrate 16 over the diffusion layers 18a and 18b and arranged in parallel.
Extension parts 11c and 1 that are branched from the wirings 11a and 11b
By mounting 1d, a pair of MOSFETs 19a and 19b connected in series between the first pin 2a and the second pin 2b is formed.

 Next, the operation will be described.

In the embodiment shown in FIGS. 1 and 2, the capacitance 14 cannot be ignored at a very short pulse width and a high voltage such as ESD, and is coupled with the external pins 2a and 2b with low impedance. By this action, for example, the ES applied to the external pin 2a
Although D is applied to the diode 5a, it is also applied to the diode 5b through the capacitance 14, and both the diodes 5a and 5b absorb the energy of the ESD. Therefore, as before, each external pin has an independent diode 5
Although the energy of ESD was absorbed by a and 5b, the ESD absorption capacity of the diodes 5a and 5b can be reduced,
In other words, the area of the diodes 5a and 5b can be reduced.

Also, in the case of the embodiment shown in FIGS.
The wires a and 2b are joined by MOS 19a and 19b, and external pins
When ESD is applied to either of 2a and 2b, MOS 19a and 19b
It turns on or enters a short-circuit state such as punch-through, and both the diodes 5a and 5b absorb the ESD energy.

These couplings work only when an abnormal voltage or current other than a signal for normal operation of the semiconductor device such as ESD is applied, and otherwise the impedance is extremely high and has no effect on the operation of the semiconductor device. No effect.

In the embodiment shown in FIG. 1, the number of the aluminum wires 13 for connecting the external pins is one, but as shown in FIG. 5, a plurality of aluminum wires 13, for example, two aluminum wires 13 and 13a are formed. Is also good. Further, instead of the aluminum wiring, as shown in FIG. 6, the same effect can be obtained by another wiring 15 below the aluminum wirings 11a and 11b. Further, as shown in FIG. 7, it is more effective to cover the diode portion with wiring for coupling.

Further, in all of the embodiments described above, the case of two external pins has been described, but the same effect can be obtained by combining two or more pins.

Further, in the embodiments shown in FIGS. 1, 5, 6 and 7, the external pins 2a and 2b are connected by another layer of wiring, but in the same layer as shown in FIG. The same effect can also be obtained by bringing the aluminum wiring closer (comb-shaped in the example). That is, in the semiconductor device shown in FIG.
The aluminum wiring 11a is provided with a plurality of extending portions formed at right angles and formed in a comb shape, and the aluminum wiring 11b is provided with a plurality of extending portions formed at right angles and formed in a comb shape. In addition, the plurality of extending portions of the aluminum wiring 11b formed in the shape of the comb teeth are engaged with the plurality of extending portions of the aluminum wiring 11a with a predetermined gap, so that A similar effect can be obtained by forming a capacitance in the capacitor and capacitively coupling the external pins.

〔The invention's effect〕

As described above, according to the present invention, during normal operation, the pins are insulated from each other and have high impedance,
Pins are coupled with low impedance only when a very narrow pulse width such as ESD and a high voltage abnormal voltage or current is applied to the pins, so connect to each pin regardless of the type of internal circuit Even if the capacity of the protection circuit is lowered, sufficient ESD energy absorption capacity can be provided, and the protection circuit area of each input / output pin is made the same as before, so that the ESD energy absorption capacity can be increased more than before. Internal circuits can be prevented from being destroyed by ESD energy.

[Brief description of the drawings]

FIG. 1 is a top view of a pattern of a protection circuit portion of a semiconductor device showing one embodiment of the present invention, FIG. 2 is an equivalent circuit of FIG. 1, and FIG. 3 (a) is another embodiment of the present invention. FIG. 3B is a top view of a pattern of a protection circuit portion of the semiconductor device, showing FIG.
Is a sectional view taken along line XX of FIG. 3 (a), and FIG.
FIG. 5 (a) is an equivalent circuit, FIG. 5 is a view showing an embodiment in which a plurality of coupling wires in FIG. 1 are provided, and FIG. 6 is a diagram in which the coupling wires in FIG. FIG.
The figure shows an embodiment in which the coupling wiring in FIG. 1 is enlarged to cover even the diode portion. FIG. 8 shows an embodiment in which the coupling between the external pins is formed in the same wiring layer. 9 and 10 are views showing a protection circuit portion of a conventional semiconductor device. In the figure, 5a and 5b are diodes, 11a and 11b are aluminum wirings, 12a and 12b are contact parts, 13 is another aluminum wiring, 1
4 is the capacitance.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-113951 (JP, A) JP-A-63-5551 (JP, A) JP-A-63-132467 (JP, A) JP-A-62 172760 (JP, A) JP-A-57-87161 (JP, A) JP-A-60-81868 (JP, A) JP-A-58-34972 (JP, A) (58) Fields investigated (Int. ⁶ , DB name) H03F 1/42-1/56 H01L 23/56-23/56 Z H02H 7/00, 7/10-7/20 IPC theme code (5J017, 5F 069, 5G053)

Claims (6)

(57) [Claims] 1. A semiconductor device having a plurality of pins for connecting an internal circuit and an external signal line, wherein a first pin included in the plurality of pins is connected to the first pin and the internal circuit. A first wiring, a second pin included in the plurality of pins, a second wiring connecting the second pin and the internal circuit, and being arranged adjacent to the first wiring;
A first protection circuit formed by a first diffusion layer provided on a semiconductor substrate and connected to the first wiring to absorb an abnormal voltage or current applied from the first pin; and a semiconductor substrate. A second protection circuit formed by a second diffusion layer provided thereon and connected to the second wiring and absorbing an abnormal voltage or current applied from the second pin; A third wiring that straddles the second wiring and is insulated from the first and second wirings and forms a capacitive coupling element that capacitively couples the first pin and the second pin; A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein a plurality of said third wirings are provided. 3. The semiconductor device according to claim 1, wherein said third wiring has a structure arranged above the first and second wirings. 4. The semiconductor device according to claim 1, wherein the third wiring has a structure arranged below the first and second wirings. 5. A semiconductor device having a plurality of pins for connecting an internal circuit to an external signal line, wherein the first pin included in the plurality of pins is connected to the first pin and the internal circuit. And connecting a first wiring having an extension portion branched and extended between both ends of the connection, a second pin included in the plurality of pins, the second pin, and the internal circuit, A second wiring which is arranged adjacent to the first wiring, is branched and extended between both ends of the connection, and has an extended portion disposed in parallel with the extended portion of the first wiring. A first protection circuit formed by a first diffusion layer provided on a semiconductor substrate and connected to the first wiring and absorbing an abnormal voltage or current applied from the first pin; Formed by a second diffusion layer provided on a semiconductor substrate, and A second protection circuit connected to the second wiring and absorbing an abnormal voltage or current applied from the second pin; and a second protection circuit provided on the semiconductor substrate across the first and second wiring layers and in parallel with the second protection circuit. The first and second arranged
And an insulating film forming a pair of MOSFETs connected in series between the first pin and the second pin by mounting both extensions of the wiring. 6. A semiconductor device having a plurality of pins for connecting an internal circuit and an external signal line, wherein a first pin included in the plurality of pins is connected to the first pin and the internal circuit. A first wiring having a plurality of extending portions formed in a comb shape by branching at right angles between both ends of the connection, a second pin included in the plurality of pins, the second pin and the internal A plurality of extending portions which are connected to a circuit and are arranged adjacent to the first wiring, are branched at right angles between both ends of the connection, and are formed in a comb-teeth shape; A plurality of formed extension portions are provided on the semiconductor substrate and a second wiring formed so that the plurality of extension portions of the first wiring mesh with the comb teeth with a predetermined gap therebetween; A first diffusion layer, which is connected to the first wiring and is marked by the first pin; A first protection circuit for absorbing the abnormal voltage or current to be applied, and a second diffusion layer provided on a semiconductor substrate, and connected to the second wiring and applied from the second pin. A second protection circuit for absorbing an abnormal voltage or current;