JP5452155B2 - Surge voltage suppression device and motor control device - Google Patents

Description

  The present invention relates to a surge voltage suppression device that suppresses a surge voltage generated at the motor end when a motor is driven by an inverter, and a motor control device including the surge voltage suppression device.

  The voltage-type PWM inverter outputs a rectangular wave (pulse) voltage. Since such an output voltage has a high voltage change rate (dV / dt), it includes a very high frequency component. The output voltage of the inverter is supplied to the motor via a cable. For this reason, a surge voltage is generated at the motor end due to reflection resonance due to the difference in impedance between the cable and the motor. This surge voltage depends on the length and type (impedance) of the cable, the laying method, etc., and the maximum value is known to be twice or more the voltage at the output terminal of the inverter. Due to the surge voltage, the insulation of the winding portion of the motor winding, particularly on the side close to the inverter, is deteriorated. If the insulation deterioration of the motor winding proceeds, there is a possibility that the insulation breakdown may occur in the worst case, and in this case, a very dangerous state is caused.

Therefore, it is widely practiced to suppress the generation of a surge voltage by adding an AC reactor, a surge voltage suppression filter or the like to the inverter output terminal or the motor terminal. However, these additional devices are generally expensive and large and heavy. For this reason, the installation requires a great deal of labor and a large installation space.
On the other hand, Patent Document 1 discloses a technique for suppressing a surge voltage by using a semiconductor element for surge absorption. According to this device, when a surge voltage exceeding a predetermined voltage is applied, the semiconductor element passes a current and clamps the voltage to a predetermined value. Such an operation suppresses the surge voltage.

Japanese Patent No. 3742636 JP-A-61-1220

  As a semiconductor element for surge absorption generally used, for example, a Zener diode can be cited. At present, the rated voltage of the Zener diode (rated value of the Zener voltage) is about 400 V at the maximum. On the other hand, the voltage value of the surge voltage generated in the motor is at least about 1000V. For this reason, when the semiconductor element described in Patent Document 1 is connected between, for example, each phase of the motor end driven by the above-described inverter, the following problem arises.

  That is, in order to suppress the surge voltage generated at the motor end, it is necessary to realize a clamp voltage higher than the single clamp voltage by connecting a plurality of the semiconductor elements in series between the phases. However, when a plurality of semiconductor elements are connected in series as described above, the voltage shared by each semiconductor element becomes unequal due to variations in the characteristics of each element. If the shared voltage becomes unequal, there is a possibility that an element sharing a high voltage will fail.

  Semiconductor device failures can be broadly divided into short-circuit mode and open-mode. Even when a failure occurs in open-mode, a short-circuit failure occurs first, and the weakest part inside the device is blown out by excessive current that flows. Finally, it becomes the release mode. That is, when a semiconductor element fails, a short circuit state always occurs first. From this, when one of the semiconductor elements connected in series fails, the semiconductor element is always short-circuited. Then, when the voltage shared by the failed semiconductor element is applied to the remaining semiconductor elements, they may fail in a chained manner. When all the semiconductor elements are in a failure state, the motor phases are short-circuited.

  Normally, when each phase of the motor is short-circuited, an output current overcurrent protection function is operated on the inverter side to shut off the inverter output. However, if the failed semiconductor element enters the open mode before this protection function operates, the short circuit state of the motor is eliminated. In this case, although the function for suppressing the surge voltage is invalidated due to the failure of the semiconductor element, the operation is continued without noticing it, and there is a possibility that the above-described problem due to the surge voltage occurs. On the other hand, even when the above protective function is activated and the inverter output is shut off, excessive current may flow in the temporary short circuit state before the shutoff, possibly adversely affecting other devices in the main system There is.

  Therefore, it is conceivable to add a configuration for detecting such a failure of the semiconductor element. For example, in Patent Document 2, a light emitting diode or photocoupler light emitting element is connected in series with a surge voltage absorbing semiconductor element, and the low impedance state before the semiconductor element is completely short-circuited is described as the light emitting state of the light emitting diode. Alternatively, a technique for detecting based on a driving state of a light receiving element of a photocoupler is disclosed.

  If it is attempted to detect a failure of the semiconductor element for surge absorption connected between the phases of the motor using the technique of Patent Document 2, the following problems arise. That is, the period during which the element is in the low impedance state described above is not always long. Therefore, there is a possibility that the semiconductor element is completely short-circuited before this low impedance state is detected and any protection operation is performed. In such a case, a detection element such as a semiconductor element and a light emitting diode may also fail due to a short-circuit current flowing, and effective failure detection cannot be performed.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent a failure caused by variations in characteristics of a semiconductor element used for suppressing a surge voltage and to immediately detect a failure state of the semiconductor element. The present invention is to provide a surge voltage suppressing device capable of performing the above and a motor control device including the surge voltage suppressing device.

  In order to achieve the above object, the surge voltage suppression device of the present invention is a surge voltage suppression device that suppresses a surge voltage generated at the motor end when the motor is driven by a voltage-type PWM inverter. The voltage of each phase is provided corresponding to each phase of the motor end, and when the voltage of the phase exceeds the predetermined clamp voltage, current flows from the motor end, A clamping unit that limits to a clamping voltage, a protection unit that is provided corresponding to the clamping unit, and that performs a protective operation that immediately shuts off an energization path interposed by the clamping unit when the corresponding clamping unit is short-circuited; When it is detected that the protection operation has been performed by the corresponding protection unit, the clamp unit corresponding to the protection unit is in a failure state. A failure detection unit that outputs a failure detection signal representing the above to the outside, wherein the clamp unit includes first and second power MOSFETs having a body diode built in between a drain and a source, The gate and the source of the second power MOSFET are short-circuited, and the first power MOSFET and the second power MOSFET are connected in series so that the rectification directions by the body diodes are opposite to each other. It is configured.

  According to the said structure, the clamp part is comprised with power MOSFET which was not used for the surge absorption use conventionally. The power MOSFETs are widely distributed up to those having a high withstand voltage value between the drain and the source, and the withstand voltage value can be selected according to a predetermined clamp voltage. Only one of the first and second power MOSFETs is avalanche-operated according to the polarity of the voltage of each phase, and the drain-source voltage is limited to the withstand voltage capability value. The surge voltage is limited to a predetermined clamp value.

  According to the present invention, only one of the first and second power MOSFETs constituting the clamp unit performs the clamping operation according to the polarity of the voltage of each phase, which is caused by variations in characteristics of each semiconductor element. There will be no failure to occur. In addition, since it has a detection unit that outputs a failure detection signal indicating that the clamp unit corresponding to the protection unit is in a failure state when it detects that the protection operation by the protection unit has been performed, the surge voltage It is possible to reliably prevent the operation of the inverter from being continued in a state where it cannot be suppressed.

1 is a schematic configuration diagram of a motor control device showing a first embodiment of the present invention. Diagram showing the electrical configuration of the surge voltage suppressor The figure which shows the structure which concerns on the failure detection of a clamp part The block diagram of the clamp part which shows the 2nd Embodiment of this invention FIG. 2 equivalent view showing the third embodiment of the present invention The block diagram of the detection part which shows the 4th Embodiment of this invention FIG. 6 equivalent view showing the fifth embodiment of the present invention FIG. 6 equivalent view showing the sixth embodiment of the present invention FIG. 6 equivalent view showing the seventh embodiment of the present invention 1 equivalent diagram FIG. 6 equivalent diagram showing an eighth embodiment of the present invention 1 equivalent diagram FIG. 6 equivalent view showing the ninth embodiment of the present invention 3 equivalent figure FIG. 6 equivalent diagram showing the tenth embodiment of the present invention 3 equivalent figure FIG. 1 equivalent view showing an eleventh embodiment of the present invention FIG. 2 equivalent diagram showing a twelfth embodiment of the present invention FIG. 2 equivalent diagram showing a thirteenth embodiment of the present invention 1 equivalent diagram

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 schematically shows the electrical configuration of the motor control device. A motor control device 1 shown in FIG. 1 controls a motor 3 by PWM driving a general-purpose voltage source inverter 2. Each phase terminal of the motor 3 is connected to each output terminal of the inverter 2 via voltage supply lines 4u, 4v, 4w (corresponding to cables). The motor 3 is, for example, a three-phase AC motor.

  The inverter 2 includes a DC power supply circuit (not shown), an inverter main circuit, a gate drive circuit (shown with reference numeral 5 in FIG. 3), a control unit (shown with reference numeral 6 in FIG. 3), and the like. Has been. The DC power supply circuit rectifies and smoothes the AC supplied from the AC power supply and outputs the rectified and smoothed output. The inverter main circuit is configured by connecting switching elements to a three-phase full bridge, and converts a DC voltage output from the DC power supply circuit into a three-phase AC voltage. This three-phase AC voltage is supplied to the motor 3 that is a load of the inverter 2. The control unit 6 controls the drive of each switching element of the inverter main circuit via the gate drive circuit 5 so that the inverter main circuit outputs a three-phase AC voltage having a specified frequency that is pulse-width modulated.

  Surge voltage suppression devices 7, 8 and 9 are connected between the voltage supply lines 4u-4v, between the voltage supply lines 4v-4w and between the voltage supply lines 4u-4w, respectively. The surge voltage suppression devices 7 to 9 suppress a surge voltage generated at the end of the motor 3, and include a clamp unit 10, a protection unit 11, a detection unit 12, and terminals P1 to P3.

  The clamp unit 10 limits the voltage between the terminals P1 and P2 to a predetermined clamp voltage VCP. The protection unit 11 performs a protection operation for cutting off the energization path between the terminals P1 and P2 when the clamp unit 10 is short-circuited. The detection unit 12 detects that the protection operation by the protection unit 11 has been performed. When detecting the protection operation, the detection unit 12 sends a failure detection signal indicating that the clamp unit 10 is in a failure state via the terminal P3. Output to inverter 2. Note that a plurality of signal lines are actually connected between the inverter 2 and the detection unit 12, but in FIG. 1, these plurality of signal lines are represented as one composite signal line 13 (multi-core cable). ing.

  FIG. 2 shows a specific configuration of the surge voltage suppressor. FIG. 2 shows only the configuration of the surge voltage suppression device 7, but the surge voltage suppression devices 8 and 9 are similarly configured. The clamp unit 10 includes transistors M1 and M2. The transistors M1 and M2 are N-channel type power MOSFETs and include body diodes BD1 and BD2 connected between the drain and the source, respectively. As the transistors M1 and M2, transistors having a drain-source breakdown voltage capability value (effective breakdown voltage) of about 1000 V are selected and used. Thereby, although the detailed operation will be described later, the clamp voltage VCP of the clamp unit 10 is about 1000V.

  In each of the transistors M1 and M2, the gate and the source are short-circuited and are normally fixed in an off state. The sources of the transistors M1 and M2 are connected to each other. The drain of the transistor M1 is connected to the node Na, and the drain of the transistor M2 is connected to the node Nb.

  The protection unit 11 includes a fast-acting fuse F1. Both terminals of the fuse F1 are connected to nodes Nc and Nd, respectively. The protection part 11 and the clamp part 10 are connected in series between the terminal P1 and the terminal P2. That is, the terminal P1 and the node Nc are connected, the node Nd and the node Na are connected, and the node Nb is connected to the terminal P2.

  The detection unit 12 includes a photocoupler PC1, diodes D1 and D2, and resistors R1 and R2. Between the node Ne and the node Nf, a light emitting diode LD1, a diode D1, and a resistor R1, which are primary side light emitting elements of the photocoupler PC1, are connected in series. A diode D2 and a resistor R1 are connected in series between the node Ng and the node Nf. The node Ne is connected to the terminal P1, the node Nf is connected to the terminal P2, and the node Ng is connected in common to the node Na of the clamp unit 10 and the node Nd of the protection unit 11. The resistor R1 limits the current flowing through the energization path between the terminal P1 and the terminal P2, and has a high resistance value. In the diode D2, the potential at the interconnection point Nh between the diode D1 and the resistor R1 is obtained by subtracting the forward voltage VF of the diode D2 from the voltage at the terminal P1 in a state where the fuse F1 is conductive and in a specific condition described later. It is provided to fix the voltage.

  The photocoupler PC1 is of a transistor output type, and its secondary side light receiving element is configured by integrating a photodiode PD1 and an NPN transistor T1. The cathode of the photodiode PD1 and the collector of the transistor T1 are connected in common and connected to the node Ni. The emitter of the transistor T1 is connected to the node Nj and is connected to the node Nk via the resistor R2. The resistor R2 is a pull-down resistor that limits the collector current of the transistor T1 and fixes the potential of the node Nj to the potential of the node Nk while the transistor T1 is off. Nodes Ni and Nk are connected to terminal Vcc and terminal N, respectively. The surge voltage suppression device 7 is supplied with a DC voltage Vcc from the inverter 2 via terminals Vcc and N. The node Nj is connected to a terminal Vo that is an output terminal of a failure detection signal. These terminals Vcc, Vo, and N correspond to the terminal P3 in FIG.

  In this embodiment, the state in which the transistor T1 is turned on and the voltage at the terminal Vo becomes equal to the voltage at the terminal Vcc (DC voltage Vcc = H level) corresponds to the state in which the failure detection signal is output. A state in which the transistor T1 is turned off and the voltage at the terminal Vo becomes equal to the voltage at the terminal N (ground potential = L level) corresponds to a state in which no failure detection signal is output. In the present embodiment, the detection current supply unit 14 is configured by the diodes D1 and D2 and the resistor R1.

  FIG. 3 shows a configuration of a portion related to failure detection of the clamp portion in the motor control device. The terminals Vcc of the surge voltage suppression devices 7 to 9 are all connected to the supply terminal of the DC voltage Vcc inside the inverter 2. The terminals N of the surge voltage suppression devices 7 to 9 are all connected to a ground potential (reference potential) supply terminal inside the inverter 2. The terminals Vo of the surge voltage suppression devices 7 to 9 are all connected to the control unit 6 inside the inverter 2. With such a configuration, the DC voltage Vcc based on the ground potential is supplied from the inverter 2 to the surge voltage suppression devices 7 to 9. Further, the voltage at each terminal Vo of the surge voltage suppression devices 7 to 9 is input to the control unit 6 of the inverter 2.

  The control unit 6 is configured mainly with a microcomputer including, for example, a CPU, a ROM, a RAM, and the like. The control unit 6 includes a latch circuit configured by software. The control unit 6 detects the rising of the voltage at each terminal Vo input using the latch circuit. When the controller 6 detects the rising of the voltage at the terminal Vo a predetermined number of times, the controller 6 determines that a failure detection signal is given from the corresponding surge voltage suppressor, and executes predetermined failure handling control. As this failure countermeasure control, for example, control for cutting off the output of the inverter 2 via the gate drive circuit 5, control for displaying that the surge voltage suppression devices 7 to 9 are faulty via the display unit 15, etc. is there.

Next, the operation of the surge voltage suppressor having the above configuration will be described.
Hereinafter, the operation of the surge voltage suppression device 7 connected between the voltage supply lines 4u-4v will be described as an example. However, the surge voltage suppression devices 8 and 9 are also operated in the same manner. In the following, the voltage at the terminal P1 is represented as VP1, and the voltage at the terminal P2 is represented as VP2. First, an operation in a state where neither of the transistors M1 and M2 has failed will be described.

(1) Operation when “Clamp Voltage VCP> Voltage VP1−Voltage VP2> 0” In this case, no surge voltage exceeding the clamp voltage VCP is generated at the motor 3 end. At this time, both the transistors M1 and M2 are in a normal off state. For this reason, a current flows through a path of the terminal P1, the fuse F1, the diode D2, the resistor R1, and the terminal P2. Since the potential of the node Nh is fixed at “voltage VP1−forward voltage VF”, no current flows through the light emitting diode LD1 of the photocoupler PC1. For this reason, the transistor T1 is turned off, and the voltage of the terminal Vo becomes L level.

(2) Operation when “Clamp Voltage VCP> Voltage VP2−Voltage VP1> 0” Also in this case, no surge voltage exceeding the clamp voltage VCP is generated at the motor 3 end. At this time, both the transistors M1 and M2 are in a normal off state. However, in this case, no current flows between the terminals P1 and P2 due to the backflow prevention action (rectification action) of the diodes D1 and D2. Accordingly, the transistor T1 is turned off, and the voltage at the terminal Vo becomes L level.

(3) Operation when “Voltage VP1−Voltage VP2> Clamping Voltage VCP” When the voltage between the terminals P1 and P2 with respect to the potential of the terminal P2 is to exceed the clamp voltage VCP, the transistor M1 is avalanche. Perform the action. That is, a current flows between the drain and source of the transistor M1 whose gate and source are short-circuited, and the drain-source voltage is stabilized at the withstand voltage capability value (= clamp voltage VCP). At this time, the drain current of the transistor M1 flows to the terminal P2 through the body diode BD2. By such an operation, the voltage between the terminals P1 and P2, that is, the voltage between the voltage supply lines 4u and 4v is limited to the clamp voltage VCP of about 1000V. Also at this time, the transistor T1 is off, and the voltage of the terminal Vo becomes L level.

(4) Operation when “Voltage VP2−Voltage VP1> Clamping Voltage VCP” When the voltage between the terminals P2 and P1 with reference to the potential of the terminal P1 is going to exceed the clamping voltage VCP, the transistor M2 becomes avalanche. Perform the action. That is, a current flows between the drain and source of the transistor M2 whose gate and source are short-circuited, and the drain-source voltage is stabilized at the withstand voltage capability value (= clamp voltage VCP). At this time, the drain current of the transistor M2 flows to the terminal P1 through the body diode BD1. By such an operation, the voltage between the terminals P2 and P1, that is, the voltage between the voltage supply lines 4v and 4u is limited to the clamp voltage VCP of about 1000V. Also at this time, the transistor T1 is off, and the voltage of the terminal Vo becomes L level.

  Next, an operation when at least one of the transistors M1 and M2 fails will be described. The transistors M1 and M2 are always accompanied by a short-circuit state when a failure occurs. When the transistor M1 is short-circuited, an excessive short-circuit current flows from the terminal P1 to the terminal P2 in the states (1) and (3) described above. Further, when the transistor M2 is short-circuited, an excessive short-circuit current flows from the terminal P2 to the terminal P1 in the states (2) and (4) described above. When an excessive current flows in this manner, the fuse F1 is immediately blown, and the energization path between the terminals P1 and P2 is interrupted. In this way, the failed clamp part 10 is quickly disconnected from the main system.

  However, in this state, there is a possibility that the operation of the inverter 2 may be continued while the surge voltage generated between the voltage supply lines 4u and 4v cannot be suppressed. Therefore, in the present embodiment, it is detected that the clamp unit 10 is in a failure state as described below, and a failure detection signal indicating that is output to the inverter 2. That is, when the fuse F1 is blown, the potential fixed state of the node Nh by the diode D2 is released.

  When the potential fixed state of the node Nh is released, the states (1) and (3) described above (exactly, the voltage VP1−voltage VP2 changes the forward voltage of the diode D1 to the forward voltage of the light emitting diode LD1). In a state higher than the applied voltage), a current flows through a path of the terminal P1, the light emitting diode LD1, the diode D1, the resistor R1, and the terminal P2. That is, since a current flows through the light emitting diode LD1 of the photocoupler PC1, the transistor T1 is turned on, and the voltage at the terminal Vo becomes H level.

  On the other hand, in the above-described states (2) and (4) (more precisely, the state where the voltage VP1−the voltage VP2 is lower than the forward voltage of the light emitting diode LD1 plus the forward voltage of the diode D1). The current does not flow through the light emitting diode LD1, the transistor T1 is turned off, and the voltage at the terminal Vo becomes L level. By such an operation, a failure detection signal is intermittently output from the surge voltage suppression device 7 to the inverter 2.

  In the inverter 2, when the control unit 6 detects that a failure detection signal is given from the surge voltage suppression device 7, the control unit 6 executes predetermined failure handling control. That is, when the control unit 6 detects the rising of the voltage at the terminal Vo of the surge voltage suppression device 7 for a predetermined number of times, the control unit 6 determines that the surge voltage suppression device 7 is in a failure state, and controls or displays the output of the inverter 2. Control for causing the unit 15 to display that the surge voltage suppression device 7 is in a failure state is performed.

  As described above, the motor control device 1 according to the present embodiment includes the surge voltage suppression devices 7 to 9 between the voltage supply lines 4u and 4v, between the voltage supply lines 4v and 4w, and between the voltage supply lines 4u and 4w. Thus, the surge voltage generated between the phases at the end of the motor 3 can be limited to the clamp voltage VCP. And the surge voltage suppression apparatuses 7-9 are provided with the clamp part 10 comprised by the transistors M1 and M2 which consist of power MOSFET which was not used as a surge absorption use conventionally. This power MOSFET is widely distributed from a low to a high withstand voltage between drain and source.

  The clamp unit 10 uses a power MOSFET having a high withstand voltage value as the transistors M1 and M2, and is configured as a connection configuration in which only one of them operates according to the polarity of each phase voltage. Suppressing operation is realized. Therefore, according to the configuration of the present embodiment, a failure caused by variation in characteristics of each semiconductor device, which has been a problem in the prior art in which a plurality of semiconductor devices are connected in series and a clamping operation is realized by all of the operations. Will not occur.

  The surge voltage suppression devices 7 to 9 include a protection unit 11 that performs a protection operation to cut off the energization path between the terminals P1 and P2 when the clamp unit 10 fails. As a result, it is possible to prevent a situation in which the transistors M1 and M2 are short-circuited and an excessive short-circuit current continues to flow between the phases. Furthermore, since the protection unit 11 is configured by the fast-acting fuse F1, the failed clamp unit 10 is quickly disconnected from the main system, and the influence of the short-circuit current on the main system can be reduced.

  The surge voltage suppression devices 7 to 9 include a detection unit 12 that detects that the protection operation by the protection unit 11 has been performed. When detecting the protection operation, the detection unit 12 outputs a failure detection signal indicating that the clamp unit 10 is in a failure state to the inverter 2. When the failure detection signal is given, the inverter 2 executes predetermined failure response control such as stopping the operation of the inverter 2. Thereby, it is possible to reliably prevent the operation of the inverter 2 from being continued in a state where the surge voltage generated between the phases at the end of the motor 3 cannot be suppressed.

(Second Embodiment)
Hereinafter, a second embodiment in which the configuration of the clamp portion is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 4 shows the clamp part of this embodiment. As shown in FIG. 4, the transistors M21 and M22 are P-channel type power MOSFETs, each having body diodes BD21 and BD22 connected between the drain and source. The transistors M21 and M22 are selected and used with a drain-source breakdown voltage capability value (effective breakdown voltage) of about 1000V.

  In each of the transistors M21 and M22, the gate and the source are short-circuited and are normally fixed in an off state. The drains of the transistors M21 and M22 are connected to each other. The source of the transistor M21 is connected to the node Na, and the source of the transistor M22 is connected to the node Nb. Even when the clamp part 21 having such a configuration is used in place of the clamp part 10 in the surge voltage suppression devices 7 to 9, the same operations and effects as those of the first embodiment can be obtained.

(Third embodiment)
Hereinafter, a third embodiment in which the configuration of the detection unit is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 5 is a view corresponding to FIG. 2 in the first embodiment. The same reference numerals are given to the same parts as those in the above-described embodiments, and the description thereof will be omitted. The detection unit 31 of the present embodiment is different from the detection unit 12 of the first embodiment in that the diode D2 is omitted. Further, the connection state of the light emitting diode LD1, the diode D1, and the resistor R1 is changed. That is, the light emitting diode LD1, the diode D1, and the resistor R1 of the photocoupler PC1 are connected in series between the node Ne and the node Ng. In the present embodiment, the detection current supply unit 32 is configured by the diode D1 and the resistor R1.

  According to such a configuration, when the transistors M1 and M2 fail and are short-circuited, and the fuse F1 is blown, current flows through the path of the terminal P1, the light emitting diode LD1, the resistor R1, the transistor M1, the body diode BD2, and the terminal P2. It will be in a state where it can flow. Therefore, in the above configuration, since the failure state of the clamp unit 10 can be detected in such a case, the same effect as the first embodiment can be obtained while simplifying the configuration of the detection unit 31.

  In the above configuration, the failure state of the clamp unit 10 cannot be detected in the following cases. In other words, when the transistors M1 and M2 fail and are temporarily short-circuited, and when a transition is made to a failure in the open mode before the fuse F1 is blown, current cannot flow through the path through the light emitting diode LD1. Therefore, although the clamp part 10 is broken in the open state, the state cannot be detected. However, the above-described problem in the present embodiment can be solved by using a fuse F1 that blows faster.

(Fourth embodiment)
Hereinafter, a fourth embodiment in which the configuration of the detection unit is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 6 shows the configuration of the detection unit of the present embodiment, and the same parts as those of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted. The detection unit 41 of the present embodiment differs from the detection unit 12 of the first embodiment in that a photocoupler PC41 is provided instead of the photocoupler PC1 and a resistor R41 is newly provided.

  The photocoupler PC41 is of a thyristor output type, and a resistor R41 is connected between the gate and cathode of a photothyristor PT41 which is a light receiving element. The resistor R41 is provided to limit the gate current that flows when the light emitting diode LD1 emits light and to ensure that the gate current does not flow during a period when the light emitting diode LD1 does not emit light. The anode of the photothyristor PT41 is connected to the node Ni. The cathode of the photothyristor PT41 is connected to the node Nj and to the node Nk via the resistor R2.

  When the detection unit 41 having the above configuration is used in place of the detection unit 12 of the surge voltage suppression devices 7 to 9, the following detection operation is performed. That is, when the fuse F1 is blown due to the failure of the transistors M1 and M2, a current flows through the path of the terminal P1, the light emitting diode LD1, the diode D1, the resistor R1, and the terminal P2. As a result, the light emitting diode LD1 emits light and a gate current is supplied to the photothyristor PT41. As a result, the photothyristor PT41 is turned on. This state is continued until the current flowing between the anode and cathode of the photothyristor PT41 becomes equal to or less than a predetermined value regardless of the supply state of the gate current. Therefore, after the photothyristor PT41 is turned on, the state where the voltage at the node Nj becomes equal to the voltage at the node Ni is maintained until the supply of the DC voltage Vcc is stopped. That is, failure detection signals are continuously output from the surge voltage suppression devices 7 to 9 to the inverter 2.

  When the detection unit 41 having such a configuration is used, the control unit 6 of the inverter 2 detects the voltage at the terminal Vo and determines whether or not the voltage level is the H level. The failure state of the devices 7-9 can be determined. Therefore, the latch circuit that detects the rising of the voltage at the terminal Vo in the control unit 6 can be omitted. Therefore, according to the present embodiment, the same effects as those of the first embodiment can be obtained, and the configuration and control contents of the control unit 6 can be simplified as compared with the first embodiment.

(Fifth embodiment)
Hereinafter, a fifth embodiment in which the configuration of the detection unit is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 7 shows the configuration of the detection unit of the present embodiment, and the same parts as those of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted. The detection unit 51 of the present embodiment is provided with a photocoupler PC51 instead of the photocoupler PC1 with respect to the detection unit 12 of the first embodiment, and a point that a resistance R51 and a thyristor 52 are newly provided. Is different.

  The photocoupler PC51 is of a high-speed IC output type, and a DC voltage Vcc is supplied to the photoIC 53 which is a light receiving element via nodes Ni and Nk. The output signal of the photo IC 53 is given to the gate of the thyristor 52 through the current limiting resistor R51. The anode of the thyristor 52 is connected to the node Ni. The cathode of the thyristor 52 is connected to the node Nj and to the node Nk via the resistor R2.

  When the detection unit 51 having the above configuration is used in place of the detection unit 12 of the surge voltage suppression devices 7 to 9, the following detection operation is performed. That is, when the fuse F1 is blown due to the failure of the transistors M1 and M2, a current flows through the path of the terminal P1, the light emitting diode LD1, the diode D1, the resistor R1, and the terminal P2. As a result, a gate current is supplied from the photo IC 53 to the thyristor 52 through the resistor R51, and the thyristor 52 is turned on. This state is continued until the current flowing between the anode and the cathode of the thyristor 52 becomes a certain value or less regardless of the supply state of the gate current. Therefore, after the thyristor 52 is turned on, the state where the voltage at the node Nj becomes equal to the voltage at the node Ni is maintained until the supply of the DC voltage Vcc is stopped. That is, failure detection signals are continuously output from the surge voltage suppression devices 7 to 9 to the inverter 2.

  Therefore, the same operation and effect as the fourth embodiment can be obtained by the configuration of the present embodiment. Further, since the photocoupler PC51 is of a high-speed IC output type, the thyristor 52 can be turned on and a failure detection signal can be output even if the current flowing through the light emitting diode LD1 is short. This makes it possible to detect the failure state of the surge voltage suppression devices 7 to 9 even during low-speed operation where the pulse width of the output voltage of the inverter 2 becomes narrow or when a low carrier frequency is set.

(Sixth embodiment)
Hereinafter, a sixth embodiment in which the configuration of the detection unit is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 8 shows the configuration of the detection unit of the present embodiment, and the same parts as those of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted. The detection unit 61 of this embodiment is different from the detection unit 12 of the first embodiment in that a resistor R61 is provided instead of the resistor R2.

  The cathode of the photodiode PD1 and the collector of the transistor T1 are connected in common. The collector of the transistor T1 is connected to the node Nj and to the node Ni through the resistor R61. The emitter of the transistor T1 is connected to the node Nk. The resistor R61 is a pull-up resistor that limits the collector current of the transistor T1 and fixes the potential of the node Nj to the potential of the node Ni while the transistor T1 is off.

  In the present embodiment, the state in which the transistor T1 is turned on and the voltage at the terminal Vo becomes equal to the voltage at the terminal N (ground potential = L level) corresponds to the state in which the failure detection signal is output. A state in which the transistor T1 is turned off and the voltage at the terminal Vo becomes equal to the voltage at the terminal Vcc (DC voltage Vcc = H level) corresponds to a state in which no failure detection signal is output.

  Further, the control unit 6 of the inverter 2 detects the falling of the voltage of each terminal Vo input using the latch circuit, and when detecting the rising for a predetermined number of times, the failure detection signal is sent from the corresponding surge voltage suppressor. Is determined, and predetermined failure handling control is executed.

  As in the above configuration, even when the node Nj (terminal Vo) of the detection unit 61 that is the output node of the failure detection signal is pulled up, the first embodiment is configured to pull down the output node of the failure detection signal. Actions and effects similar to those of the form can be obtained. Note that the detection units 41 and 51 shown in FIGS. 6 and 7 can also be changed to a configuration in which the node Nj is pulled up as in the present embodiment.

(Seventh embodiment)
Hereinafter, a seventh embodiment in which the configuration of the detection unit is changed with respect to the first embodiment will be described with reference to FIGS. 9 and 10.
FIG. 9 shows the configuration of the detection unit of the present embodiment, and the same parts as those of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted. The detection unit 71 of this embodiment is different from the detection unit 12 of the first embodiment in that a resistor R71 (corresponding to a resistance element) and a temperature relay TR71 (corresponding to a signal output unit) are used instead of the photocoupler PC1 and the resistor R2. It differs from the point that it has.

  A resistor R71, a diode D1, and a resistor R1 are connected in series between the node Ne and the node Nf. The temperature relay TR71 is a temperature detection element (not shown) provided in the vicinity of the resistor R71, and a normally open contact S71 (contact A) that operates (closes) when the temperature detected by the temperature detection element exceeds a predetermined temperature. And. That is, the contact S71 of the temperature relay TR71 closes when the temperature of the resistor R71 becomes equal to or higher than a predetermined temperature. Both terminals of the contact S71 are connected to nodes Nl and Nm, respectively.

  The nodes Nl and Nm are connected to a contact input terminal (not shown) of the control unit 6 of the inverter 2. The control unit 6 includes a circuit (not shown) that detects the operating state of the contact S71 based on the contact signals of the nodes Nl and Nm connected to the contact input terminals. For example, the control unit 6 determines that the contact S71 is in an operating state when the contact signals of the nodes Nl and Nm are at the same potential. In the present embodiment, the detection current supply unit 72 is configured by the diodes D1 and D2 and the resistors R1 and R71. Further, the state where the contact S71 of the temperature relay TR71 is closed corresponds to the state where the failure detection signal is output.

  When the detection unit 71 having the above configuration is used in place of the detection unit 12 of the surge voltage suppression devices 7 to 9, the following detection operation is performed. That is, when the fuse F1 is blown due to the failure of the transistors M1 and M2, current flows intermittently through the path of the terminal P1, the resistor R71, the diode D1, the resistor R1, and the terminal P2. In response to this, the temperature of the resistor R71 gradually increases, and when the temperature becomes equal to or higher than a predetermined temperature, the contact S71 of the temperature relay TR71 is closed. This state is continued until the temperature of the resistor R71 becomes lower than the predetermined temperature. That is, failure detection signals are continuously output from the surge voltage suppression devices 7 to 9 to the inverter 2. When the control unit 6 detects that the contact S71 is in an operating state based on the contact signals of the nodes Nl and Nm, the control unit 6 determines that the surge voltage suppression device is in a failure state, and executes predetermined failure handling control.

  Therefore, the same operation and effect as those of the first embodiment can be obtained also by the configuration of the present embodiment. Furthermore, since the failure detection signal is continuously output, the configuration of the input unit of the control unit 6 that inputs the failure detection signal can be simplified. Moreover, since the detection unit 71 can operate without receiving power supply from the outside, it is not necessary to supply the DC voltage Vcc required in the detection unit 12 of the first embodiment.

  Moreover, when applying the detection part 71 to the surge voltage suppression apparatuses 7-9, you may connect each node Nl and Nm like FIG. FIG. 10 is a view corresponding to FIG. 1 in the first embodiment. In FIG. 10, illustration of structures other than contact S71 is abbreviate | omitted about the surge voltage suppression apparatuses 7-9. As shown in FIG. 10, the nodes Nl of the surge voltage suppression devices 7 to 9 are connected in common and the nodes Nm are connected in common. That is, the contacts S71 of the surge voltage suppression devices 7-9 are connected in parallel to each other. These commonly connected nodes Nl and Nm are connected to the contact input terminal of the control unit 6 of the inverter 2.

  In this case, the control unit 6 may perform the following failure detection. That is, when a failure detection signal is output from at least one of the surge voltage suppression devices 7 to 9, that is, when at least one contact S71 is closed, each contact of the commonly connected nodes Nl and Nm The signals are at the same potential. The control unit 6 may determine that at least one of the surge voltage suppression devices 7 to 9 is in a failure state when the contact signals of the nodes Nl and Nm have the same potential, and execute predetermined failure response control. . In this case, a state in which at least one of the contacts S71 of the temperature relays TR71 of the surge voltage suppression devices 7 to 9 is closed corresponds to a state in which a failure detection signal is output.

(Eighth embodiment)
Hereinafter, an eighth embodiment in which the configuration of the detection unit is changed with respect to the first embodiment will be described with reference to FIGS. 11 and 12.
FIG. 11 shows the configuration of the detection unit of the present embodiment, and the same parts as those of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted. The detection unit 81 of this embodiment is different from the detection unit 71 of the seventh embodiment in that a thermistor TH81 is provided instead of the temperature relay TR71.

  The thermistor TH81 is disposed in the vicinity of the resistor R71. Thereby, the resistance value of the thermistor TH81 changes according to the temperature change of the resistor R71. Both terminals of the thermistor TH81 are connected to nodes Nl and Nm, respectively. The control unit 6 includes a resistance value detection circuit that detects a resistance value between the nodes Nl and Nm (not shown). This resistance value detection circuit, for example, allows a constant current to flow between the nodes Nl and Nm, and detects the resistance value of the thermistor TH81 from the voltage value generated between the nodes Nl and Nm. In this case, the resistance value of the thermistor TH81 when the temperature of the resistor R71 is a predetermined temperature (for example, a high temperature that is not possible in normal operation) is measured, and the predetermined resistance value is used as a failure determination threshold value. May be used. In the present embodiment, the state where the resistance value of the thermistor TH81 is equal to or lower than a predetermined resistance value corresponds to the state where the failure detection signal is output.

  When the detection unit 81 having the above configuration is used in place of the detection unit 12 of the surge voltage suppression devices 7 to 9, the following detection operation is performed. That is, when the fuse F1 is blown due to the failure of the transistors M1 and M2, a current flows intermittently through the resistor R71 and the temperature rises. When the temperature of the resistor R71 becomes equal to or higher than the predetermined temperature, the resistance value of the thermistor TH81 becomes equal to or lower than the predetermined resistance value. This state is continued until the temperature of the resistor R71 becomes lower than the predetermined temperature. That is, failure detection signals are continuously output from the surge voltage suppression devices 7 to 9 to the inverter 2. When the control unit 6 detects that the resistance between the nodes Nl and Nm is equal to or less than a predetermined resistance value, the control unit 6 determines that the surge voltage suppression device is in a failure state, and executes predetermined failure response control.

  Therefore, the same operation and effect as those of the first embodiment can be obtained also by the configuration of the present embodiment. Furthermore, since the detection unit 81 can operate without receiving power supply from the outside, it is not necessary to supply the DC voltage Vcc required in the detection unit 12 of the first embodiment.

  Moreover, when applying the detection part 81 to the surge voltage suppression apparatuses 7-9, you may connect each node Nl and Nm like FIG. FIG. 12 is a view corresponding to FIG. 1 in the first embodiment. In FIG. 12, the illustration of the components other than the thermistor TH81 in the surge voltage suppression devices 7 to 9 is omitted. As shown in FIG. 12, the node Nm of the surge voltage suppression device 9 and the node Nl of the surge voltage suppression device 7 are connected, and the node Nm of the surge voltage suppression device 7 and the node Nl of the surge voltage suppression device 8 are connected. To do. The node Nl of the surge voltage suppression device 9 and the node Nm of the surge voltage suppression device 8 are connected to the control unit 6 of the inverter 2, respectively. That is, the thermistors TH81 of the surge voltage suppression devices 7-9 are connected in series.

  In this case, the control unit 6 detects the series combined resistance value of each thermistor TH81, and may perform the following failure detection based on the value. That is, when a failure detection signal is output from at least one of the surge voltage suppression devices 7 to 9, that is, when it is detected that the series combined resistance value of each thermistor TH81 has decreased by at least the predetermined resistance value, What is necessary is just to determine that at least any one of the surge voltage suppression devices 7 to 9 is in a failure state, and execute predetermined failure response control. In this case, a state in which the series combined resistance value of each thermistor TH81 is reduced by at least a predetermined resistance value corresponds to a state in which a failure detection signal is output.

(Ninth embodiment)
Hereinafter, a ninth embodiment in which the configuration of the detection unit is changed with respect to the first embodiment will be described with reference to FIGS. 13 and 14.
FIG. 13 shows the configuration of the detection unit of the present embodiment, and the same parts as those of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted. The detection unit 91 of the present embodiment is different from the detection unit 12 of the first embodiment in that the resistor R2 and the node Nk are omitted. That is, the emitter of the transistor T1 is connected to the node Nj.

  FIG. 14 corresponds to FIG. 3 in the first embodiment, and shows a configuration of a portion related to failure detection of the clamp portion in the motor control device. The surge voltage suppression devices 7 to 9 of the present embodiment are collectively configured as a surge voltage suppression unit 92. The surge voltage suppression unit 92 includes a resistor R91, a terminal P91, a terminal P92, and a terminal P93.

  Each terminal Vcc (= each node Ni) of the surge voltage suppression devices 7 to 9 is connected to the terminal P91 of the surge voltage suppression unit 92. Each terminal Vo (= node Nj) of the surge voltage suppression devices 7 to 9 is connected to the terminal P92 of the surge voltage suppression unit 92 and to the terminal P93 via the resistor R91. The resistor R91 limits the collector current of each transistor T1 of the surge voltage suppression devices 7 to 9, and fixes the potential of the terminal P92 to the potential of the terminal P93 while all the transistors T1 are off. That is, in this embodiment, one resistor R91 functions as a pull-down resistor instead of the resistor R2 provided in each of the surge voltage suppression devices 7 to 9 in the first embodiment.

  In the present embodiment, at least one of the transistors T1 provided in the surge voltage suppression devices 7 to 9 is turned on so that the voltage at the terminal P92 becomes equal to the voltage at the terminal P91 (DC voltage Vcc = H level). Corresponds to a state in which a failure detection signal is output. Further, a state in which all the transistors T1 are turned off and the voltage at the terminal P92 is equal to the voltage at the terminal P93 (ground potential = L level) corresponds to a state where no failure detection signal is output.

  The inverter panel 93 accommodates the inverter 2 and peripheral devices, and includes a patrol lamp 94 and a relay 95. The relay 95 includes an exciting coil 95a and a contact point 95b that operates when the exciting coil 95a is excited. A patrol lamp 94 and a contact point 95b are connected in series between the supply terminal for the DC voltage Vcc and the supply terminal for the ground potential. One terminal of the exciting coil 95a is connected to a ground potential supply terminal.

  The terminal P91 of the surge voltage suppression unit 92 is connected to the supply terminal of the DC voltage Vcc inside the inverter panel 93. The terminal P92 of the surge voltage suppression unit 92 is connected to the other terminal of the exciting coil 95a inside the inverter panel 93. A terminal P93 of the surge voltage suppression unit 92 is connected to a ground potential (reference potential) supply terminal inside the inverter panel 93. With such a configuration, the DC voltage Vcc with reference to the ground potential is supplied from the inverter panel 93 to the surge voltage suppression devices 7 to 9. The voltage at the terminal P92 of the surge voltage suppression unit 92 is input to the control unit 6 of the inverter 2.

  According to the above configuration, when at least one of the clamp portions 10 of the surge voltage suppression devices 7 to 9 fails, at least one transistor T1 is turned on, and the voltage at the terminal P92 of the surge voltage suppression unit 92 becomes the voltage at the terminal P91. Will be equal. Then, in the inverter panel 93, the DC voltage Vcc is applied between the terminals of the exciting coil 95a, and the contact point 95b is closed. When the contact point 95b is closed, the DC voltage Vcc is applied to both ends of the patrol lamp 94, and the patrol lamp 94 is turned on.

  As described above, in this embodiment, when at least one of the surge voltage suppression devices 7 to 9 is in a failure state, the inverter panel 93 lights the patrol lamp 94 to notify the user of the state. . Thereby, it is possible to prevent the operation of the inverter 2 from being continued in a state where the surge voltage generated between the phases at the end of the motor 3 cannot be suppressed. Therefore, the present embodiment can provide the same effects as those of the first embodiment. Further, the terminals Vo of the surge voltage suppression devices 7 to 9 are commonly connected, and then pulled down by one resistor R91 provided in the surge voltage suppression unit 92 (wired OR connection). Therefore, it is possible to detect the failure state of the three surge voltage suppression devices 7 to 9 under the OR condition while reducing the number of parts constituting the detection unit 91.

(Tenth embodiment)
Hereinafter, a tenth embodiment in which the configuration of the detection unit is changed with respect to the sixth embodiment will be described with reference to FIGS. 15 and 16.
FIG. 15 shows the configuration of the detection unit of the present embodiment, and the same parts as those of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted. The detection unit 101 of this embodiment is different from the detection unit 61 of the sixth embodiment shown in FIG. 8 in that the resistor R61 and the node Ni are omitted. That is, the collector of the transistor T1 is connected to the node Nj.

  FIG. 16 corresponds to FIG. 3 in the first embodiment, and shows a configuration of a portion related to the failure detection of the clamp portion in the motor control device. Each terminal Vo (= each node Nj) of the surge voltage suppression devices 7 to 9 is connected to the terminal P101 of the inverter 2. Each terminal N (= node Nk) of the surge voltage suppression devices 7 to 9 is connected to the terminal P102 of the inverter 2.

  In the inverter 2, the terminal P <b> 101 is connected to the control unit 6 and is connected to the supply terminal of the DC voltage Vcc via the resistor R <b> 101. The terminal P102 is connected to a ground potential supply terminal. The resistor R101 limits the collector current of each transistor T1 of the surge voltage suppression devices 7 to 9, and fixes the voltage at each terminal Vo to the DC voltage Vcc while all the transistors T1 are off. That is, in the present embodiment, one resistor R101 functions as a pull-up resistor instead of the resistor R61 provided in each of the surge voltage suppression devices 7 to 9 in the sixth embodiment. With such a configuration, the DC voltage Vcc based on the ground potential is supplied from the inverter 2 to the surge voltage suppression devices 7 to 9. Further, the voltage at the terminal Vo commonly connected to the surge voltage suppression devices 7 to 9 is input to the control unit 6 of the inverter 2.

  In the present embodiment, a failure occurs when at least one of the transistors T1 provided in the surge voltage suppression devices 7 to 9 is turned on and the voltage at each terminal Vo becomes equal to the voltage at the terminal N (ground potential = L level). This corresponds to a state in which a detection signal is output. Further, a state where all the transistors T1 are turned off and the voltage at the terminal Vo becomes equal to the DC voltage Vcc (= H level) corresponds to a state where no failure detection signal is output.

  According to the above configuration, when at least one of the clamp portions 10 of the surge voltage suppression devices 7 to 9 fails, at least one transistor T1 is turned on and the voltage at the terminal Vo becomes L level. When detecting the falling of the voltage at the terminal Vo, the control unit 6 of the inverter 2 determines that at least one of the surge voltage suppression devices 7 to 9 is in a failure state, and executes predetermined failure response control. Examples of the failure handling control include the following two controls.

  When the terminal P101 of the inverter 2 is assigned to function as an emergency stop signal input terminal, the following control is executed. That is, when the motor 3 is driven by the inverter 2, when at least one of the surge voltage suppression devices 7 to 9 fails and the voltage at the terminal P101 becomes L level, the control unit 6 generates an emergency stop signal. Judge that it was input. Thereby, the control part 6 interrupts | blocks the output of the inverter 2 via the gate drive circuit 5, and stops the drive of the motor 3 (emergency stop). Further, the control unit 6 displays “E” indicating an emergency stop on the display unit 15 to notify the user of the abnormality.

  Further, when the terminal P101 of the inverter 2 is assigned so as to function as an operation preparation completion terminal (ST terminal), the following control is executed. Normally, the ST terminal enables the operation of the inverter 2 when the terminal voltage is L level (when the input is conductive), but here, this function is inverted and used. That is, the inverter 2 can be operated when the terminal voltage is at the H level (when the input is open). When driving the motor 3 by the inverter 2, when at least one of the surge voltage suppression devices 7 to 9 fails and the voltage at the terminal P101 becomes L level, the control unit 6 operates the inverter 2. Judge that it is not possible. Thereby, the control part 6 stops sending the gate drive signal from the gate drive circuit 5 (free-run stop). Further, the control unit 6 causes the display unit 15 to display “OFF” indicating that the operation of the inverter 2 cannot be performed (the ST signal is off), and the user is informed of the abnormality. Inform.

  As described above, in the present embodiment, when at least one of the surge voltage suppression devices 7 to 9 is in a failure state, the motor 3 is stopped and the user is notified of the abnormal state. . Thereby, it is possible to prevent the operation of the inverter 2 from being continued in a state where the surge voltage generated between the phases at the end of the motor 3 cannot be suppressed. Therefore, the present embodiment can provide the same effects as those of the first embodiment. Moreover, after connecting each terminal Vo of the surge voltage suppression apparatuses 7-9 in common, it pulls up by one resistance R101 provided in the inverter 2 (wired OR connection). Therefore, the failure state of the three surge voltage suppression devices 7 to 9 can be detected under the OR condition while reducing the number of parts constituting the detection unit 101.

(Eleventh embodiment)
Hereinafter, an eleventh embodiment in which the surge voltage suppression device is constituted by a plurality of separable units will be described with reference to FIG.
FIG. 17 shows the configuration of the motor control device of the present embodiment, and the same parts as those of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted. The motor control device 111 differs from the motor control device 1 according to the first embodiment shown in FIG. 1 in that surge voltage suppression devices 7A to 9A are provided instead of the surge voltage suppression devices 7 to 9.

  The surge voltage suppression device 7 </ b> A includes a first unit 112 including the clamp unit 10 and the protection unit 11, and a second unit 113 including the detection unit 12. The node Nc of the protection unit 11 of the first unit 112 and the node Ne of the detection unit 12 of the second unit 113 are detachably connected. The node Na of the clamp unit 10 and the node Nd of the protection unit 11 in the first unit 112 and the node Ng of the detection unit 12 of the second unit 113 are detachably connected. The node Nb of the clamp unit 10 in the first unit 112 and the node Nf of the detection unit 12 of the second unit 113 are detachably connected. Thus, the first unit 112 and the second unit 113 are connected in a separable state. In addition, in FIG. 17, although illustration about the structure of surge voltage suppression apparatus 8A, 9A is abbreviate | omitted, it is comprised similarly to 7 A of surge voltage suppression apparatuses.

  As described above, even if the surge voltage suppression devices 7A to 9A are configured by the first unit 112 including the clamp unit 10 and the protection unit 11 and the second unit 113 including the detection unit 12, Operations and effects similar to those of the embodiment can be obtained. Furthermore, since the first unit 112 and the second unit 113 are connected in a separable state, the following effects can be obtained.

  For example, the 1st unit 112 provided with the clamp part and protection part of a predetermined composition in each above-mentioned embodiment is prepared as one kind of basic unit. And the 2nd unit 113 of the structure corresponding to the detection part in each said embodiment is prepared as a multiple types of option unit. In this way, the user can select one having a desired detector from a plurality of types of option units. Furthermore, by using one type of the first unit, the used parts and the assembly work are made common for the clamp part and the protection part, and as a result, the manufacturing cost of the surge voltage suppression device as a whole can be reduced.

(Twelfth embodiment)
Hereinafter, a twelfth embodiment in which the configuration of the surge voltage suppressor is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 18 shows the configuration of the surge voltage suppressor 121 of the present embodiment, and the same parts as those of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted. The surge voltage suppression device 121 of the present embodiment is different from the surge voltage suppression device 7 of the first embodiment shown in FIG. Instead, the difference is that the detector 123 is provided.

  The protection unit 122 and the detection unit 123 are configured by a fuse 124 with an internal contact (alarm contact). The fuse 124 is a fast-breaking type, and the contact portion 124b is activated when the fuse portion 124a is melted. The contact portion 124b is a normally open contact (A contact). Both terminals of the fuse portion 124a are connected to nodes Nc and Nd, respectively. Both terminals of the contact portion 125b are connected to the node Nn and the node No, respectively.

  Nodes Nn and No are connected to contact input terminals (not shown) of the control unit 6 of the inverter 2. The control unit 6 includes a circuit (not shown) that detects the operating state of the contact part 124b based on the contact signals of the nodes Nn and No connected to the contact input terminal. Thus, in this embodiment, the protection part 122 is comprised by the fuse part 124a, and the detection part 123 is comprised by the contact part 124b. The state where the contact portion 124b is activated and closed corresponds to the state where the failure detection signal is output.

  When the surge voltage suppression device 121 having the above configuration is used in place of the surge voltage suppression devices 7 to 9, the following detection operation is performed. That is, when the fuse portion 124a is melted due to the failure of the transistors M1 and M2, the contact portion 124b is closed. When the control unit 6 detects that the contact unit 124b is in an operating state based on the contact signals of the nodes Nn and No, the control unit 6 determines that the surge voltage suppression device is in a failure state, and executes predetermined failure handling control.

  Therefore, the same operation and effect as those of the first embodiment can be obtained also by the configuration of the present embodiment. Furthermore, compared with the above embodiments, the number of parts constituting the detection unit can be greatly reduced. In addition, since the detection unit 121 can operate without receiving power supply from the outside, it is not necessary to supply the DC voltage Vcc required in the detection unit 12 of the first embodiment.

  Moreover, when using the surge voltage suppression apparatus 121 instead of the surge voltage suppression apparatuses 7-9, you may connect node Nn and No like 7th Embodiment shown in FIG. That is, the nodes Nn of the three surge voltage suppression devices 121 are connected in common, and the nodes No are connected in common. These commonly connected nodes Nn and No are connected to the contact input terminals of the control unit 6 of the inverter 2. And what is necessary is just to change control of the control part 6 similarly to 7th Embodiment. If comprised in this way, the effect | action and effect similar to 7th Embodiment are acquired.

(13th Embodiment)
Hereinafter, a thirteenth embodiment in which the configuration of the surge voltage suppression device is changed with respect to the first embodiment will be described with reference to FIGS. 19 and 20.
19 and 20 show the configuration of the surge voltage suppression device of this embodiment and the motor control device using the same, and the same parts as those of the above embodiments are given the same reference numerals and the description thereof is omitted. As shown in FIG. 19, the surge voltage suppression device 131 is different from the surge voltage suppression device 7 of the first embodiment shown in FIG. And the terminal Pc is provided. A node Nb is connected to the terminal Pa, a node Nf is connected to the terminal Pb, and nodes Na and Nd are connected to the terminal Pc.

  When the surge voltage suppression device 131 configured as described above and the surge voltage suppression devices 132 and 133 configured in the same manner are used instead of the surge voltage suppression devices 7 to 9 according to the first embodiment, the connection as illustrated in FIG. It becomes a form. Surge voltage suppression devices 131 to 133 provided in motor control device 134 shown in FIG. 20 suppress a surge voltage generated between the phases at the end of motor 3.

  In the surge voltage suppressor 131, the terminal P1 is connected to the voltage supply line 4u, the terminal Pa is connected to the terminal Pc of the surge voltage suppressor 132, the terminal Pb is connected to the voltage supply line 4v, and the terminal Pc is suppressed from the surge voltage. It is connected to the terminal Pa of the device 133. In the surge voltage suppression device 132, the terminal P1 is connected to the voltage supply line 4v, the terminal Pa is connected to the terminal Pc of the surge voltage suppression device 133, and the terminal Pb is connected to the voltage supply line 4w. In the surge voltage suppression device 133, the terminal P1 is connected to the voltage supply line 4w, and the terminal Pb is connected to the voltage supply line 4u.

  According to the said connection form, each clamp part 10 of the surge voltage suppression apparatuses 131-133 suppresses the surge voltage which generate | occur | produces between each phase in the motor 3 end as follows. Between the voltage supply lines 4u and 4v, the protection unit 11 and the clamp unit 10 of the surge voltage suppression device 131 and the protection unit 11 of the surge voltage suppression device 132 are connected in series in this order. Therefore, the clamp part 10 of the surge voltage suppression device 131 functions to suppress the surge voltage generated between the voltage supply lines 4u and 4v. Further, the protection units 11 of the surge voltage suppression devices 131 and 132 protect the short-circuit failure of the clamp unit 10 of the surge voltage suppression device 131.

  Between the voltage supply lines 4v and 4w, the protection unit 11 and the clamp unit 10 of the surge voltage suppression device 132 and the protection unit 11 of the surge voltage suppression device 133 are connected in series in this order. Therefore, the clamp part 10 of the surge voltage suppressor 132 functions to suppress the surge voltage generated between the voltage supply lines 4v and 4w. Further, the protection units 11 of the surge voltage suppression devices 132 and 133 protect the short-circuit failure of the clamp unit 10 of the surge voltage suppression device 132.

  Between the voltage supply lines 4w and 4u, the protection unit 11 and the clamp unit 10 of the surge voltage suppression device 133 and the protection unit 11 of the surge voltage suppression device 131 are connected in series in this order. Therefore, the clamp part 10 of the surge voltage suppression device 133 functions to suppress the surge voltage generated between the voltage supply lines 4w and 4u. In addition, the protection units 11 of the surge voltage suppression devices 131 and 133 protect the short-circuit failure of the clamp unit 10 of the surge voltage suppression device 133.

  As described above, the surge voltage suppression devices 131 to 133 according to the present embodiment can also suppress the surge voltage generated between the phases at the end of the motor 3. Moreover, each clamp part 10 of the surge voltage suppression apparatuses 131-133 becomes a form protected by the two protection parts 11, respectively. In other words, each of the protection units 11 of the surge voltage suppression devices 131 to 133 performs a protection operation against a short circuit failure of the two clamp units 10. Furthermore, each detection part 12 of the surge voltage suppression apparatuses 131-133 detects the presence or absence of the protection operation by the protection part 11 corresponding to each. Therefore, according to this embodiment, the same operation and effect as those of the first embodiment can be obtained.

(Other embodiments)
The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The connection positions of the transistors M1 and M2 constituting the clamp unit 10 may be switched. Further, the connection positions of the transistors M21 and M22 constituting the clamp part 21 may be switched. That is, the transistors M1 (M21) and M2 (M22) may be connected in series so that the rectification directions of the body diodes are opposite to each other.
The transistor output type photocoupler in the first embodiment is not limited to the one in which the secondary side light receiving element is integrated. For example, the secondary side element may be constituted by a phototransistor. However, in this case, as the response performance of the secondary side element, it is necessary to have a response that can be sufficiently driven during the lighting period of the primary side light emitting element determined according to the output frequency of the inverter 2. .
The three surge voltage suppression devices 7 to 9 in the first to eighth embodiments may also be configured as one surge voltage suppression unit as in the ninth embodiment.
The DC voltage Vcc used in the surge voltage suppression devices 7 to 9 may be supplied from a device other than the inverter 2 or the inverter panel 93. Moreover, you may add the structure which produces | generates DC voltage Vcc based on the output voltage (voltage of the voltage supply lines 4u-4w) of the inverter 2 to a surge voltage suppression apparatus.

The contact S71 in the seventh embodiment and the contact portion 125b in the twelfth embodiment are both normally open contacts (A contacts), but instead use normally closed contacts (B contacts). May be. When such a normally closed contact is used, the contacts of the three surge voltage suppression devices may be connected in series, and contact signals at both ends thereof may be input to the control unit 6. When at least one of the three normally closed contacts is opened (actuated), the contact signal becomes non-conductive. The control unit 6 may determine that any one of the surge voltage suppression devices is in a failure state when the contact signal is in a non-conduction state.
In the eighth embodiment, when the inverter 2 has a function of detecting the resistance value of the thermistor (thermistor temperature detection function), this may be used. If the functions provided in advance are used, the configuration of the control unit 6 can be simplified accordingly. Further, the thermistor TH81 is used to detect the temperature change of the resistor R71, but the present invention is not limited to this, and for example, a thermocouple may be used.
In the seventh embodiment, when a temperature relay for overheat protection or the like is built in the motor 3, the contact of the temperature relay and the contact S71 of each temperature relay TR71 may be connected in series. In this way, the wiring between the motor 3 and the inverter 2 can be diverted.

In the ninth embodiment, the DC voltage supplied to the surge voltage suppression devices 7 to 9 and the DC voltage supplied to the patrol lamp 94 may be generated by different power supply circuits. Further, the patrol lamp 94 is not limited to one that is lit by a DC voltage, but may be one that is lit by an AC voltage, for example.
In each of the above embodiments, three surge voltage suppression devices are connected between the phases of the motor 3, but instead of or in addition to this, the surge voltage suppression device is connected between each phase of the motor 3 and the ground. May be. If it does in this way, the surge voltage which generate | occur | produces between each phase and earth | ground at the motor 3 end can be suppressed.
The resistor for pulling down the potential of the terminal Vo, which is the output terminal of the failure detection signal, and the resistor for pulling up need not be provided on the surge voltage suppressor side, but can be provided, for example, on the inverter side or the inverter panel side. It is.

  In the drawings, 1, 111, 134 are motor control devices, 2 is an inverter, 3 is a motor, 4u, 4v, 4w are voltage supply lines (cables), 7-9, 7A-9A, 121, 131-133 are surge voltages. Suppressor 10, 21 is a clamp part, 11, 122 is a protection part, 12, 31, 41, 51, 61, 71, 81, 91, 101, 123 are detection parts, 14, 32, 72 are detection current supply parts , 52 is a thyristor, 53 is a photo IC, 124b is an internal contact, BD1, BD2, BD21 and BD22 are body diodes, F1 and 124 are fuses, LD1 is a light emitting diode, M1 and M21 are transistors (first power MOSFET), M2 and M22 are transistors (second power MOSFETs), PC1, PC41 and PC51 are photocouplers, and PT41 is photothyris. (Thyristor), R71 is the resistance (resistance element), S71 is contact, T1 is a transistor, TH81 thermistor (signal output section), TR71 indicates a temperature relay (signal output section).

Claims (14)

When a motor is driven by a voltage-type PWM inverter, a surge voltage suppressing device that suppresses a surge voltage generated at the motor end,
It is provided corresponding to each phase of the motor end, and when the voltage of each phase exceeds the predetermined clamp voltage, a current is passed from the motor end, so that the voltage of each phase is changed to the clamp voltage. The clamping part to restrict,
A protection part that is provided corresponding to the clamp part, and that performs a protection operation to immediately shut off the energization path in which the clamp part is interposed when the corresponding clamp part is short-circuited;
When detecting that the protection operation is performed by the corresponding protection unit provided corresponding to the protection unit, a failure detection signal indicating that the clamp unit corresponding to the protection unit is in a failure state is externally provided. And a detector for outputting to
The clamp part is
Comprising first and second power MOSFETs having a body diode built in between the drain and source;
The gates and sources of the first and second power MOSFETs are short-circuited, and the first power MOSFET and the second power MOSFET are connected in series so that the rectification directions of the body diodes are opposite to each other. A surge voltage suppressor, characterized in that it is connected to the device. The surge voltage suppression device according to claim 1, wherein the clamp part and the protection part are connected in series between the phases of the motor end. The surge voltage suppression device according to claim 1 or 2, wherein the clamp part and the protection part are connected in series between each phase of the motor end and ground.
  The surge voltage suppression device according to any one of claims 1 to 3, wherein the protection unit is a fast-acting fuse connected in series to the energization path. The detector is
A transistor output type photocoupler;
When the protection operation is performed, a detection current supply unit that supplies a forward current to the light emitting diode on the primary side of the photocoupler from the motor end,
The surge voltage suppression device according to any one of claims 1 to 4, wherein the failure detection signal is output during a period in which a transistor on the secondary side of the photocoupler is in an on state. The detector is
A thyristor output type photocoupler;
When the protection operation is performed, a detection current supply unit that supplies a forward current to the light emitting diode on the primary side of the photocoupler from the motor end,
The surge voltage suppression device according to any one of claims 1 to 4, wherein the failure detection signal is output during a period when the thyristor on the secondary side of the photocoupler is in an ON state. The detector is
High-speed IC output type photocoupler,
When the protection operation is performed, a detection current supply unit that supplies a forward current from the motor end to the light emitting diode on the primary side of the photocoupler;
A thyristor to which an output signal of a photo IC on the secondary side of the photocoupler is applied to a gate;
The surge voltage suppression device according to any one of claims 1 to 4, wherein the failure detection signal is output during a period in which the thyristor is in an on state. The detector is
A resistance element;
When the protection operation is performed, a detection current supply unit that supplies current from the motor end to the resistance element;
5. The surge voltage suppression device according to claim 1, further comprising a signal output unit that outputs the failure detection signal when a temperature of the resistance element becomes equal to or higher than a predetermined temperature. 6.   The signal output unit is configured to include a temperature relay having a contact that operates when the temperature of the resistance element reaches a predetermined temperature or more, and outputs the failure detection signal during a period in which the contact is operating. The surge voltage suppressing device according to claim 8.   The surge voltage suppression device according to any one of claims 1 to 9, wherein the clamp part, the protection part, and the detection part are configured to be detachable. The fuse includes an internal contact that operates when blown,
The surge voltage suppression device according to claim 4, wherein the detection unit outputs the failure detection signal during a period in which the internal contact is operating.   When each of the detection units detects that the protection operation has been performed by at least one of the protection units, a failure detection signal indicating that at least one of the clamp units is in a failure state is output to the outside. The surge voltage suppression device according to any one of claims 1 to 11, wherein A voltage-type PWM inverter that drives the motor via a cable;
A motor control device comprising the surge voltage suppression device according to claim 1. The surge voltage suppressor sends the failure detection signal to the inverter;
The motor control device according to claim 13, wherein the inverter performs failure handling control for stopping driving of the motor when the failure detection signal is given.

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