JP5421049B2 - Surge voltage suppression device and motor control device - Google Patents

Description

  The present invention relates to a surge voltage suppression device that suppresses a surge voltage generated at the motor end when a motor is driven by an inverter, and a motor control device including the surge voltage suppression device.

  The voltage-type PWM inverter outputs a rectangular wave (pulse) voltage. Since such an output voltage has a high voltage change rate (dV / dt), it includes a very high frequency component. The output voltage of the inverter is supplied to the motor via a cable. For this reason, a surge voltage is generated at the motor end due to reflection resonance due to the difference in impedance between the cable and the motor. This surge voltage depends on the length and type (impedance) of the cable, the laying method, etc., and the maximum value is known to be twice or more the voltage at the output terminal of the inverter. Due to the surge voltage, the insulation of the winding portion of the motor winding, particularly on the side close to the inverter, is deteriorated. If the insulation deterioration of the motor winding proceeds, there is a possibility that the insulation breakdown may occur in the worst case, and in this case, a very dangerous state is caused.

Therefore, it is widely practiced to suppress the generation of a surge voltage by adding an AC reactor, a surge voltage suppression filter or the like to the inverter output terminal or the motor terminal. However, these additional devices are generally expensive and large and heavy. For this reason, the installation requires a great deal of labor and a large installation space.
On the other hand, Patent Document 1 discloses a technique for suppressing a surge voltage by using a semiconductor element for surge absorption. According to this device, when a surge voltage exceeding a predetermined voltage is applied, the semiconductor element passes a current and clamps the voltage to a predetermined value. Such an operation suppresses the surge voltage.

Japanese Patent No. 3742636 JP-A-61-1220

  As a semiconductor element for surge absorption generally used, for example, a Zener diode can be cited. At present, the rated voltage of the Zener diode (rated value of the Zener voltage) is about 400 V at the maximum. On the other hand, the voltage value of the surge voltage generated in the motor is at least about 1000V. For this reason, when the semiconductor element described in Patent Document 1 is connected between, for example, each phase of the motor end driven by the above-described inverter, the following problem arises.

  That is, in order to suppress the surge voltage generated at the motor end, it is necessary to realize a clamp voltage higher than the single clamp voltage by connecting a plurality of the semiconductor elements in series between the phases. However, when a plurality of semiconductor elements are connected in series as described above, the voltage shared by each semiconductor element becomes unequal due to variations in the characteristics of each element. If the shared voltage becomes unequal, there is a possibility that an element sharing a high voltage will fail.

  Semiconductor device failures can be broadly divided into short-circuit mode and open-mode. Even when a failure occurs in open-mode, a short-circuit failure occurs first, and the weakest part inside the device is blown out by excessive current that flows. Finally, it becomes the release mode. That is, when a semiconductor element fails, a short circuit state always occurs first. From this, when one of the semiconductor elements connected in series fails, the semiconductor element is always short-circuited. Then, when the voltage shared by the failed semiconductor element is applied to the remaining semiconductor elements, they may fail in a chained manner. When all the semiconductor elements are in a failure state, the motor phases are short-circuited.

  Normally, when each phase of the motor is short-circuited, an output current overcurrent protection function is operated on the inverter side to shut off the inverter output. However, if the failed semiconductor element enters the open mode before this protection function operates, the short circuit state of the motor is eliminated. In this case, although the function for suppressing the surge voltage is invalidated due to the failure of the semiconductor element, the operation is continued without noticing it, and there is a possibility that the above-described problem due to the surge voltage occurs. On the other hand, even when the above protective function is activated and the inverter output is shut off, excessive current may flow in the temporary short circuit state before the shutoff, possibly adversely affecting other devices in the main system There is.

  Therefore, it is conceivable to add a configuration for detecting such a failure of the semiconductor element. For example, in Patent Document 2, a light emitting diode or photocoupler light emitting element is connected in series with a surge voltage absorbing semiconductor element, and the low impedance state before the semiconductor element is completely short-circuited is described as the light emitting state of the light emitting diode. Alternatively, a technique for detecting based on a driving state of a light receiving element of a photocoupler is disclosed.

  If it is attempted to detect a failure of the semiconductor element for surge absorption connected between the phases of the motor using the technique of Patent Document 2, the following problems arise. That is, the period during which the element is in the low impedance state described above is not always long. Therefore, there is a possibility that the semiconductor element is completely short-circuited before this low impedance state is detected and any protection operation is performed. In such a case, a detection element such as a semiconductor element and a light emitting diode may also fail due to a short-circuit current flowing, and effective failure detection cannot be performed.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent a failure caused by variations in characteristics of a semiconductor element used for suppressing a surge voltage and to immediately detect a failure state of the semiconductor element. The present invention is to provide a surge voltage suppressing device capable of performing the above and a motor control device including the surge voltage suppressing device.

  In order to achieve the above object, the surge voltage suppression device of the present invention is a surge voltage suppression device that suppresses a surge voltage generated at the motor end when the motor is driven by a voltage-type PWM inverter. The voltage of each phase is provided corresponding to each phase of the motor end, and when the voltage of the phase exceeds the predetermined clamp voltage, current flows from the motor end, A clamping unit that limits to a clamping voltage, a protection unit that is provided corresponding to the clamping unit, and that performs a protective operation that immediately shuts off an energization path interposed by the clamping unit when the corresponding clamping unit is short-circuited; A detection unit that is provided corresponding to a protection unit and detects the protection operation by the corresponding protection unit; and when the detection unit detects a protection operation of the protection unit, A display unit that displays that the lamp unit is in a failure state, and the clamp unit includes first and second power MOSFETs having a body diode built in between a drain and a source. And the gate and the source of the second power MOSFET are short-circuited, and the first power MOSFET and the second power MOSFET are connected in series so that the rectification directions by the body diodes are opposite to each other. It is characterized by being configured.

  According to the said structure, the clamp part is comprised with power MOSFET which was not used for the surge absorption use conventionally. The power MOSFETs are widely distributed up to those having a high withstand voltage value between the drain and the source, and the withstand voltage value can be selected according to a predetermined clamp voltage. Only one of the first and second power MOSFETs is avalanche-operated according to the polarity of the voltage of each phase, and the drain-source voltage is limited to the withstand voltage capability value. The surge voltage is limited to a predetermined clamp value. And when this clamp part fails, the protection operation which interrupts | blocks the electricity supply path | route by a protection part is performed. When the detection unit detects the protection operation of the protection unit, the display unit displays that the clamp unit is in a failure state. As described above, since the failure state notification operation is completed in the apparatus, for example, wiring for outputting a signal indicating the failure state to the outside can be omitted.

  According to the present invention, only one of the first and second power MOSFETs constituting the clamp unit performs the clamping operation according to the polarity of the voltage of each phase, which is caused by variations in characteristics of each semiconductor element. There will be no failure to occur. In addition, when the protection operation by the protection unit is detected, the clamp unit is provided with a display unit for displaying that the failure state is present. For example, without providing wiring for outputting a signal indicating the failure state to the outside It is possible to notify the user of the failure of the part. Therefore, it is possible to reliably prevent the operation of the inverter from being continued in a state where the surge voltage cannot be suppressed.

1 is a schematic configuration diagram of a motor control device showing a first embodiment of the present invention. Diagram showing the electrical configuration of the surge voltage suppressor The block diagram of the clamp part which shows the 2nd Embodiment of this invention FIG. 2 equivalent view showing the third embodiment of the present invention FIG. 2 equivalent view showing a fourth embodiment of the present invention FIG. 2 equivalent view showing a fifth embodiment of the present invention FIG. 1 equivalent view showing a sixth embodiment of the present invention FIG. 2 equivalent diagram showing a seventh embodiment of the present invention 1 equivalent diagram

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2.
FIG. 1 schematically shows the electrical configuration of the motor control device. A motor control device 1 shown in FIG. 1 controls a motor 3 by PWM driving a general-purpose voltage source inverter 2. Each phase terminal of the motor 3 is connected to each output terminal of the inverter 2 via voltage supply lines 4u, 4v, 4w (corresponding to cables). The motor 3 is, for example, a three-phase AC motor.

  The inverter 2 includes a DC power supply circuit, an inverter main circuit, a gate drive circuit, a control unit (all not shown), and the like. The DC power supply circuit rectifies and smoothes the AC supplied from the AC power supply and outputs the rectified and smoothed output. The inverter main circuit is configured by connecting switching elements to a three-phase full bridge, and converts a DC voltage output from the DC power supply circuit into a three-phase AC voltage. This three-phase AC voltage is supplied to the motor 3 that is a load of the inverter 2. The control unit controls the driving of each switching element of the inverter main circuit via the gate drive circuit so that the inverter main circuit outputs a three-phase AC voltage having a specified frequency that is pulse-width modulated.

  Surge voltage suppression devices 7, 8 and 9 are connected between the voltage supply lines 4u-4v, between the voltage supply lines 4v-4w and between the voltage supply lines 4u-4w, respectively. The surge voltage suppression devices 7 to 9 suppress a surge voltage generated at the end of the motor 3, and include a clamp unit 10, a protection unit 11, a detection unit 12, a display unit 13, and terminals P1 and P2.

  The clamp unit 10 limits the voltage between the terminals P1 and P2 to a predetermined clamp voltage VCP. The protection unit 11 performs a protection operation for cutting off the energization path between the terminals P1 and P2 when the clamp unit 10 is short-circuited. The detection unit 12 detects that the protection operation by the protection unit 11 has been performed. When the detection operation is detected by the detection unit 12, the display unit 13 performs a display indicating that the clamp unit 10 is in a failure state.

  FIG. 2 shows a specific configuration of the surge voltage suppressor. FIG. 2 shows only the configuration of the surge voltage suppression device 7, but the surge voltage suppression devices 8 and 9 are similarly configured. The clamp unit 10 includes transistors M1 and M2. The transistors M1 and M2 are N-channel type power MOSFETs and include body diodes BD1 and BD2 connected between the drain and the source, respectively. As the transistors M1 and M2, transistors having a drain-source breakdown voltage capability value (effective breakdown voltage) of about 1000 V are selected and used. Thereby, although the detailed operation will be described later, the clamp voltage VCP of the clamp unit 10 is about 1000V.

  The transistors M1 and M2 (corresponding to the first and second power MOSFETs) are short-circuited between the gate and the source, and are normally fixed in the off state. The sources of the transistors M1 and M2 are connected to each other. The drain of the transistor M1 is connected to the node Na, and the drain of the transistor M2 is connected to the node Nb.

  The protection unit 11 includes a fast-acting fuse F1. Both terminals of the fuse F1 are connected to nodes Nc and Nd, respectively. The protection part 11 and the clamp part 10 are connected in series between the terminal P1 and the terminal P2. That is, the terminal P1 and the node Nc are connected, the node Nd and the node Na are connected, and the node Nb is connected to the terminal P2.

  The detection unit 12 includes diodes D1 and D2 and a resistor R1. A diode D1 and a resistor R1 are connected in series between the node Ne and the node Nf. A diode D2 and a resistor R1 are connected in series between the node Ng and the node Nf. The display unit 13 includes a light emitting diode LD1 (corresponding to a light emitting element). The light emitting diode LD1 has an anode connected to the node Nh and a cathode connected to the node Ni.

  The node Nh of the display unit 13 is connected to the terminal P1, and the node Ni is connected to the node Ne of the detection unit 12. The node Nf of the detection unit 12 is connected to the terminal P2, and the node Ng of the detection unit 12 is commonly connected to the node Na of the clamp unit 10 and the node Nd of the protection unit 11. The resistor R1 limits the current flowing through the energization path between the terminal P1 and the terminal P2, and has a high resistance value. The diodes D1 and D2 prevent backflow between the terminals P1 and P2 due to their rectifying action. The diode D2 is configured such that the potential of the node Nj, which is an interconnection point between the diode D1 and the resistor R1, is changed from the voltage at the terminal P1 to the forward direction of the diode D2 in a state where the fuse F1 is conductive and under a specific condition described later. The voltage VF is fixed to a reduced voltage.

  In the surge voltage suppression device 7, the light emitting diode LD1 is provided in such a manner that its lighting state is visible from the outside. Although details will be described later in the description of the operation, the surge voltage suppression device 7 of the present embodiment notifies the user that the clamp portion 10 is in a failure state by turning on the light emitting diode LD1. Yes.

Next, the operation of the surge voltage suppressor having the above configuration will be described.
Hereinafter, the operation of the surge voltage suppression device 7 connected between the voltage supply lines 4u-4v will be described as an example. However, the surge voltage suppression devices 8 and 9 are also operated in the same manner. In the following, the voltage at the terminal P1 is represented as VP1, and the voltage at the terminal P2 is represented as VP2. First, an operation in a state where neither of the transistors M1 and M2 has failed will be described.

(1) Operation when “Clamp Voltage VCP> Voltage VP1−Voltage VP2> 0” In this case, no surge voltage exceeding the clamp voltage VCP is generated at the motor 3 end. At this time, both the transistors M1 and M2 are in a normal off state. For this reason, a current flows through a path of the terminal P1, the fuse F1, the diode D2, the resistor R1, and the terminal P2. Note that since the potential of the node Nj is fixed at “voltage VP1−forward voltage VF”, no current flows through the path through which the light emitting diode LD1 is interposed, and the light emitting diode LD1 is turned off.

(2) Operation when “Clamp Voltage VCP> Voltage VP2−Voltage VP1> 0” Also in this case, no surge voltage exceeding the clamp voltage VCP is generated at the motor 3 end. At this time, both the transistors M1 and M2 are in a normal off state. However, in this case, no current flows between the terminals P1 and P2 due to the rectifying action of the diodes D1 and D2. Therefore, the light emitting diode LD1 is in a light-off state.

(3) Operation when “Voltage VP1−Voltage VP2> Clamping Voltage VCP” When the voltage between the terminals P1 and P2 with respect to the potential of the terminal P2 is to exceed the clamp voltage VCP, the transistor M1 is avalanche. Perform the action. That is, a current flows between the drain and source of the transistor M1 whose gate and source are short-circuited, and the drain-source voltage is stabilized at the withstand voltage capability value (= clamp voltage VCP). At this time, the drain current of the transistor M1 flows to the terminal P2 through the body diode BD2. By such an operation, the voltage between the terminals P1 and P2, that is, the voltage between the voltage supply lines 4u and 4v is limited to the clamp voltage VCP of about 1000V. Also at this time, no current flows through the path through which the light emitting diode LD1 is interposed, and the light emitting diode LD1 is in a light-off state.

(4) Operation when “Voltage VP2−Voltage VP1> Clamping Voltage VCP” When the voltage between the terminals P2 and P1 with reference to the potential of the terminal P1 is going to exceed the clamping voltage VCP, the transistor M2 becomes avalanche. Perform the action. That is, a current flows between the drain and source of the transistor M2 whose gate and source are short-circuited, and the drain-source voltage is stabilized at the withstand voltage capability value (= clamp voltage VCP). At this time, the drain current of the transistor M2 flows to the terminal P1 through the body diode BD1. By such an operation, the voltage between the terminals P2 and P1, that is, the voltage between the voltage supply lines 4v and 4u is limited to the clamp voltage VCP of about 1000V. Also at this time, no current flows through the path through which the light emitting diode LD1 is interposed, and the light emitting diode LD1 is in a light-off state.

  Next, an operation when at least one of the transistors M1 and M2 fails will be described. The transistors M1 and M2 are always accompanied by a short-circuit state when a failure occurs. When the transistor M1 is short-circuited, an excessive short-circuit current flows from the terminal P1 to the terminal P2 in the states (1) and (3) described above. Further, when the transistor M2 is short-circuited, an excessive short-circuit current flows from the terminal P2 to the terminal P1 in the states (2) and (4) described above. When an excessive current flows in this manner, the fuse F1 is immediately blown, and the energization path between the terminals P1 and P2 is interrupted. In this way, the failed clamp part 10 is quickly disconnected from the main system.

  However, in this state, there is a possibility that the operation of the inverter 2 may be continued while the surge voltage generated between the voltage supply lines 4u and 4v cannot be suppressed. Therefore, in the present embodiment, it is detected that the clamp unit 10 is in a failure state as follows and the user is notified of it. That is, when the fuse F1 is blown, the potential fixed state of the node Nj by the diode D2 is released.

  When the potential fixed state of the node Nj is released, the states (1) and (3) described above (exactly, the voltage VP1−voltage VP2 changes the forward voltage of the diode D1 to the forward voltage of the light emitting diode LD1). In a state higher than the applied voltage), a current flows through a path of the terminal P1, the light emitting diode LD1, the diode D1, the resistor R1, and the terminal P2. As a result, the light emitting diode LD1 is turned on. On the other hand, in the above-described states (2) and (4) (more precisely, the state where the voltage VP1−the voltage VP2 is lower than the forward voltage of the light emitting diode LD1 plus the forward voltage of the diode D1). No current flows through the path where the light emitting diode LD1 is interposed. As a result, the light emitting diode LD1 is turned off.

  With such an operation, forward current is intermittently supplied from the voltage supply lines 4u and 4v to the light emitting diode LD1, and the light emitting diode LD1 is repeatedly turned on and off (flashing state). The blinking frequency of the light emitting diode LD1 is determined according to the carrier frequency of the inverter 2. Usually, the carrier frequency of the inverter 2 is variable in the range of several kHz (for example, 1 kHz or 2 kHz) to several tens of kHz (for example, 16 kHz). For this reason, the blinking frequency of the light emitting diode LD1 is also several kHz to several tens of kHz. Thus, the light-emitting diode LD1 blinking at a high speed appears to be constantly lit by human eyes.

  Therefore, the user can recognize that the light emitting diode LD1 is lit and determine that the clamp unit 10 is in a failure state. Normally, when the user determines that the clamp unit 10 is in a malfunctioning state, that is, a state in which the surge suppression function is invalidated, for example, the user takes measures such as stopping the operation of the inverter 2. For this reason, the situation where the operation of the inverter 2 is continued while the surge voltage is not suppressed can be prevented.

  As described above, the motor control device 1 according to the present embodiment includes the surge voltage suppression devices 7 to 9 between the voltage supply lines 4u and 4v, between the voltage supply lines 4v and 4w, and between the voltage supply lines 4u and 4w. Thus, the surge voltage generated between the phases at the end of the motor 3 can be limited to the clamp voltage VCP. And the surge voltage suppression apparatuses 7-9 are provided with the clamp part 10 comprised by the transistors M1 and M2 which consist of power MOSFET which was not used as a surge absorption use conventionally. This power MOSFET is widely distributed from a low to a high withstand voltage between drain and source.

  The clamp unit 10 uses a power MOSFET having a high withstand voltage value as the transistors M1 and M2, and is configured as a connection configuration in which only one of them operates according to the polarity of each phase voltage. Suppressing operation is realized. Therefore, according to the configuration of the present embodiment, a failure caused by variation in characteristics of each semiconductor device, which has been a problem in the prior art in which a plurality of semiconductor devices are connected in series and a clamping operation is realized by all of the operations. Will not occur.

  The surge voltage suppression devices 7 to 9 include a protection unit 11 that performs a protection operation to cut off the energization path between the terminals P1 and P2 when the clamp unit 10 fails. As a result, it is possible to prevent a situation in which the transistors M1 and M2 are short-circuited and an excessive short-circuit current continues to flow between the phases. Furthermore, since the protection unit 11 is configured by the fast-acting fuse F1, the failed clamp unit 10 is quickly disconnected from the main system, and the influence of the short-circuit current on the main system can be reduced.

  The surge voltage suppression devices 7 to 9 include a detection unit 12 that detects a protection operation of the protection unit 11 and a display unit 13 that includes a light emitting diode LD1 that is turned on when the protection operation is detected. The light emitting diode LD1 is provided in a manner in which the lighting state is visible from the outside in the surge voltage suppression devices 7 to 9. For this reason, the user can know the failure state of the clamp part 10 by the lighting state of light emitting diode LD1. And if it takes an appropriate measure such as stopping the operation of the inverter 2 when it is determined that the clamp portion 10 is in a failure state, the inverter can be controlled in a state in which the surge voltage generated between the phases at the end of the motor 3 cannot be suppressed. It is possible to reliably prevent the second operation from being continued.

  Since the display unit for displaying the failure state of the clamp unit 10 is provided in the surge voltage suppression devices 7 to 9, the notification operation of the failure state of the clamp unit 10 is completed in the surge voltage suppression devices 7 to 9. For this reason, for example, wiring for outputting a detection signal indicating a failure state to an external device such as the inverter 2 can be omitted. Thus, the following effects can be obtained by eliminating the need for the detection signal wiring.

  For example, when a detection wiring is provided, it is necessary to take measures against noise in the wiring. According to the present embodiment, the cost for wiring is naturally reduced. However, since there is no wiring for detection, it is not necessary to take the above countermeasures against noise. The problem due to the surge voltage described above becomes more prominent as the installation location of the inverter 2 and the installation location of the motor 3 are separated, that is, the wiring distance of the voltage supply lines 4u to 4w is longer. In such a case, providing the wiring for the detection signal further complicates the installation work and makes it difficult to take measures against the noise as compared with the case where the wiring is short. According to the present embodiment, it is possible to eliminate the occurrence of various problems relating to the wiring described above.

(Second Embodiment)
Hereinafter, a second embodiment in which the configuration of the clamp portion is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 3 shows the clamp part of the present embodiment. As shown in FIG. 3, the transistors M21 and M22 are P-channel type power MOSFETs, each having body diodes BD21 and BD22 connected between the drain and source. The transistors M21 and M22 are selected and used with a drain-source breakdown voltage capability value (effective breakdown voltage) of about 1000V.

  In each of the transistors M21 and M22, the gate and the source are short-circuited and are normally fixed in an off state. The drains of the transistors M21 and M22 are connected to each other. The source of the transistor M21 is connected to the node Na, and the source of the transistor M22 is connected to the node Nb. Even when the clamp part 21 having such a configuration is used in place of the clamp part 10 in the surge voltage suppression devices 7 to 9, the same operations and effects as those of the first embodiment can be obtained.

(Third embodiment)
Hereinafter, a third embodiment in which the configuration of the detection unit is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 4 is a view corresponding to FIG. 2 in the first embodiment, and the same parts as those in the above-described embodiments are denoted by the same reference numerals and description thereof is omitted. The detection unit 31 of the present embodiment is different from the detection unit 12 of the first embodiment in that the diode D2 is omitted. Further, the connection state between the light emitting diode LD1 of the display unit 13, the diode D1, and the resistor R1 is changed. That is, the light emitting diode LD1, the diode D1, and the resistor R1 are connected in series between the node Nh and the node Ng.

  According to such a configuration, when the transistors M1 and M2 fail and are short-circuited, and the fuse F1 is blown, the path of the terminal P1, the light emitting diode LD1, the diode D1, the resistor R1, the transistor M1, the body diode BD2, and the terminal P2 In this state, a current can flow. Therefore, in the above configuration, since the failure state of the clamp unit 10 can be detected and the light emitting diode LD1 can be turned on in such a case, the same effect as that of the first embodiment can be achieved while simplifying the configuration of the detection unit 31. Is obtained.

  In the above configuration, the failure state of the clamp unit 10 cannot be detected in the following cases. In other words, when the transistors M1 and M2 fail and are temporarily short-circuited, and when a transition is made to a failure in the open mode before the fuse F1 is blown, current cannot flow through the path through the light emitting diode LD1. Therefore, although the clamp part 10 is broken in the open state, the state cannot be detected. However, the above-described problem in the present embodiment can be solved by using a fuse F1 that blows faster.

(Fourth embodiment)
Hereinafter, a fourth embodiment in which the configuration of the surge voltage suppression device is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 5 shows the configuration of the surge voltage suppression device 41 of the present embodiment, and the same parts as those of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted. The surge voltage suppression device 41 according to the present embodiment is different from the surge voltage suppression device 7 according to the first embodiment shown in FIG. Instead, the difference is that the detector 43 is provided.

  The protection unit 42 is configured by a fuse 44 with an internal contact (alarm contact). The fuse 44 is a fast-acting type, and when the fuse portion 44a is melted, the contact portion 44b is activated. The contact portion 44b is a normally open contact (A contact). Both terminals of the fuse portion 44a are connected to nodes Nc and Nd, respectively. The detection unit 43 includes a contact part 44b of a fuse 44, a diode D1, and a resistor R1 connected in series between the node Ne and the node Nf.

  When the surge voltage suppression device 41 having the above configuration is used in place of the surge voltage suppression devices 7 to 9, the following detection operation is performed. That is, when the fuse portion 44a is melted due to the failure of the transistors M1 and M2, the contact portion 44b is closed. Thereby, a current flows intermittently through the path of the terminal P1, the light emitting diode LD1, the diode D1, the resistor R1, and the terminal P2, and the light emitting diode LD1 blinks at high speed. Accordingly, the surge voltage suppression device 41 having the above-described configuration can provide the same operations and effects as those of the first embodiment.

(Fifth embodiment)
Hereinafter, a fifth embodiment in which the configuration of the surge voltage suppression device is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 6 shows the configuration of the surge voltage suppression device 51 of the present embodiment, and the same parts as those of the above-described embodiments are denoted by the same reference numerals and description thereof is omitted. The surge voltage suppression device 51 of the present embodiment is different from the surge voltage suppression device 41 of the fourth embodiment shown in FIG. Instead, the display unit 53 is different from the point that a power supply circuit 54 is newly provided.

  The detection unit 52 includes a contact portion 44b of a fuse 44 connected between the node Ne and the node Nf. The display unit 53 includes a lamp indicator 55 connected between the node Nh and the node Ni. The lamp indicator 55 (corresponding to a light emitting element) is lit with a current flowing when a DC voltage is applied to both ends thereof. The power supply circuit 54 receives a voltage (voltages of the voltage supply lines 4u to 4w) given through the terminals P1 and P2, and generates and outputs a predetermined DC voltage. The DC voltage output from the power supply circuit 54 is applied between the nodes Nh and Nf.

  The lamp indicator 55 is provided in the surge voltage suppression device 51 in such a manner that its lighting state is visible from the outside. The surge voltage suppression device 51 of the present embodiment notifies the user that the clamp unit 10 is in a failure state by turning on the lamp indicator 55.

  When the surge voltage suppression device 51 having the above configuration is used in place of the surge voltage suppression devices 7 to 9, the following detection operation is performed. That is, when the fuse portion 44a is melted due to the failure of the transistors M1 and M2, the contact portion 44b is closed. Thereby, the DC voltage output from the power supply circuit 54 is applied to both ends of the lamp display 55, and the lamp display 55 is turned on. Accordingly, the surge voltage suppression device 51 having the above-described configuration can provide the same operations and effects as those of the first embodiment.

(Sixth embodiment)
Hereinafter, a sixth embodiment in which the surge voltage suppression device is configured from a plurality of separable units will be described with reference to FIG.
FIG. 7 shows the configuration of the motor control device of the present embodiment. The same parts as those of the above-described embodiments are denoted by the same reference numerals, and description thereof is omitted. The motor control device 61 differs from the motor control device 1 according to the first embodiment shown in FIG. 1 in that surge voltage suppression devices 7A to 9A are provided instead of the surge voltage suppression devices 7 to 9.

  The surge voltage suppression device 7A includes a first unit 62 including a clamp unit 10, a terminal P1, and a terminal P2, and a second unit 63 including a protection unit 11, a detection unit 12, and a display unit 13. In the first unit 62, the terminal P1 is connected to the node Nk. The node Nk of the first unit 62, the node Nc of the protection unit 11 of the second unit 63, and the node Nh of the display unit 13 are detachably connected. The node Na of the clamp unit 10 in the first unit 62 and the node Nd of the protection unit 11 and the node Ng of the detection unit 12 in the second unit 63 are detachably connected. The node Nb of the clamp unit 10 in the first unit 62 and the node Nf of the detection unit 12 in the second unit 63 are detachably connected. Thus, the first unit 62 and the second unit 63 are connected in a separable state. In addition, in FIG. 7, although illustration about the structure of surge voltage suppression apparatus 8A, 9A is abbreviate | omitted, it is comprised similarly to the surge voltage suppression apparatus 7A.

  As described above, even when the surge voltage suppression devices 7A to 9A are configured by the first unit 62 including the clamp unit 10 and the second unit 63 including the protection unit 11, the detection unit 12, and the display unit 13. The same operations and effects as those of the first embodiment can be obtained. Further, since the first unit 62 and the second unit 63 are configured to be connected in a separable state, the following effects can be obtained.

  For example, the first unit 62 including the clamp portion having the predetermined configuration in each of the above embodiments is prepared as one type of basic unit. And the 2nd unit 63 of the structure corresponding to the protection part in each said embodiment, a detection part, and a display part is prepared as a multiple types of option unit. In this way, the user can select a desired one from a plurality of types of option units. Furthermore, by using one type of the first unit, the parts used and the assembly work are made common for the clamp portion, and as a result, the manufacturing cost of the entire surge voltage suppression device series can be reduced.

(Seventh embodiment)
Hereinafter, a seventh embodiment in which the configuration and the like of the surge voltage suppression device are changed with respect to the first embodiment will be described with reference to FIGS. 8 and 9.
8 and 9 show the configurations of the surge voltage suppression device of this embodiment and the motor control device using the same, and the same parts as those in the above embodiments are given the same reference numerals and the description thereof is omitted. As shown in FIG. 8, the surge voltage suppression device 71 is different from the surge voltage suppression device 7 of the first embodiment shown in FIG. 2 in that it has terminals Pa and Pb instead of the terminal P2, and a new one. And the terminal Pc is provided. A node Nb is connected to the terminal Pa, a node Nf is connected to the terminal Pb, and nodes Na and Nd are connected to the terminal Pc.

  When the surge voltage suppression device 71 configured as described above and the surge voltage suppression devices 72 and 73 configured in the same manner are used in place of the surge voltage suppression devices 7 to 9 according to the first embodiment, the connection as shown in FIG. It becomes a form. In FIG. 9, the detection unit 12 and the display unit 13 are shown as one block. Surge voltage suppression devices 71 to 73 provided in the motor control device 74 shown in FIG. 9 suppress a surge voltage generated between the phases at the end of the motor 3.

  In the surge voltage suppressor 71, the terminal P1 is connected to the voltage supply line 4u, the terminal Pa is connected to the terminal Pc of the surge voltage suppressor 72, the terminal Pb is connected to the voltage supply line 4v, and the terminal Pc is suppressed from the surge voltage. It is connected to the terminal Pa of the device 73. In the surge voltage suppression device 72, the terminal P1 is connected to the voltage supply line 4v, the terminal Pa is connected to the terminal Pc of the surge voltage suppression device 73, and the terminal Pb is connected to the voltage supply line 4w. In the surge voltage suppressor 73, the terminal P1 is connected to the voltage supply line 4w, and the terminal Pb is connected to the voltage supply line 4u.

  According to the said connection form, each clamp part 10 of the surge voltage suppression apparatuses 71-73 suppresses the surge voltage which generate | occur | produces between each phase at the motor 3 end as follows. Between the voltage supply lines 4u and 4v, the protection unit 11 and the clamp unit 10 of the surge voltage suppression device 71 and the protection unit 11 of the surge voltage suppression device 72 are connected in series in this order. Therefore, the clamp part 10 of the surge voltage suppression device 71 functions to suppress the surge voltage generated between the voltage supply lines 4u and 4v. Further, the protection units 11 of the surge voltage suppression devices 71 and 72 protect the short-circuit failure of the clamp unit 10 of the surge voltage suppression device 71.

  Between the voltage supply lines 4v and 4w, the protection unit 11 and the clamp unit 10 of the surge voltage suppression device 72 and the protection unit 11 of the surge voltage suppression device 73 are connected in series in this order. Therefore, the clamp part 10 of the surge voltage suppression device 72 functions to suppress the surge voltage generated between the voltage supply lines 4v and 4w. Further, the protection units 11 of the surge voltage suppression devices 72 and 73 protect the short-circuit failure of the clamp unit 10 of the surge voltage suppression device 72.

  Between the voltage supply lines 4w and 4u, the protection unit 11 and the clamp unit 10 of the surge voltage suppression device 73 and the protection unit 11 of the surge voltage suppression device 71 are connected in series in this order. Therefore, the clamp part 10 of the surge voltage suppressing device 73 functions to suppress the surge voltage generated between the voltage supply lines 4w and 4u. Further, the protection units 11 of the surge voltage suppression devices 71 and 73 protect the short-circuit failure of the clamp unit 10 of the surge voltage suppression device 73.

  As described above, the surge voltage suppression devices 71 to 73 of the present embodiment can also suppress the surge voltage generated between the phases at the end of the motor 3. Moreover, each clamp part 10 of the surge voltage suppression apparatuses 71-73 becomes a form protected by the two protection parts 11, respectively. In other words, each of the protection units 11 of the surge voltage suppression devices 71 to 73 performs a protection operation against a short circuit failure of the two clamp units 10. Furthermore, when each detection unit 12 of the surge voltage suppression devices 71 to 73 detects the protection operation by the corresponding protection unit 11 and each display unit 13 detects the protection operation by the corresponding detection unit 12, It is displayed that the clamp part 10 corresponding to the protection part 11 is in a failure state. Therefore, according to this embodiment, the same operation and effect as those of the first embodiment can be obtained.

(Other embodiments)
The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The connection positions of the transistors M1 and M2 constituting the clamp unit 10 may be switched. Further, the connection positions of the transistors M21 and M22 constituting the clamp part 21 may be switched. That is, the transistors M1 (M21) and M2 (M22) may be connected in series so that the rectification directions of the body diodes are opposite to each other.
Three surge voltage suppression devices provided corresponding to each phase may be configured as one unit.
As the fuse constituting the protection unit, a fuse provided with a fusing display unit for performing a predetermined display indicating that the fusing is performed at the time of fusing may be used. In this case, the fuse is arranged in a form in which the display state of the fusing display portion is easily visible from the outside. In this way, when the fuse is blown due to the failure of the clamp part, the blown display part performs a predetermined display. The user can determine that the clamp portion is in a failure state based on this display. According to the said structure, since the fusing display part with which a fuse is equipped functions as a detection part and a display part, the number of parts for comprising a surge voltage suppression apparatus can be reduced significantly.

In the fifth embodiment, the lamp indicator 55 may be turned on when an AC voltage is applied to both ends thereof. In that case, the power supply circuit 54 may have a configuration in which a voltage supplied via the terminals P1 and P2 is input, and a predetermined AC voltage is generated and output. In addition, the power supply circuit 54 is provided in each of the three surge voltage suppression devices. However, one power supply circuit 54 is provided independently from each surge voltage suppression device, and the three surge voltage suppression devices in the three surge voltage suppression devices are provided. A voltage may be supplied to each lamp indicator 55. Further, the lamp indicator 55 is provided in each of the three surge voltage suppression devices. However, only one of the surge voltage suppression devices is provided with the lamp indicator 55, and both ends of the three contact portions 44b are parallel to each other. It is good also as a structure connected to. In this way, when at least one of the three clamp portions 10 fails, the lamp indicator 55 is turned on. Therefore, the failure state of the three surge voltage suppression devices can be detected under the OR condition.
In 6th Embodiment, although it isolate | separated into the 1st unit 62 provided with the clamp part 10, and the 2nd unit 63 provided with the protection part 11, the detection part 12, and the display part 13, it does not need to be restricted to this. For example, you may isolate | separate into the 1st unit provided with the clamp part 10 and the protection part 11, and the 2nd unit provided with the detection part 12 and the display part 13. FIG. That is, a part of the clamp unit 10, the protection unit 11, the detection unit 12, and the display unit 13 may be configured to be detachable.
In each of the above embodiments, three surge voltage suppression devices are connected between the phases of the motor 3, but instead of or in addition to this, the surge voltage suppression device is connected between each phase of the motor 3 and the ground. May be. If it does in this way, the surge voltage which generate | occur | produces between each phase and earth | ground at the motor 3 end can be suppressed.

  In the drawings, 1, 61, 74 are motor control devices, 2 is an inverter, 3 is a motor, 4u, 4v, 4w are voltage supply lines (cables), 7-9, 41, 51, 7A-9A, 71-73 are Surge voltage suppressor, 10 and 21 are clamping parts, 11 and 42 are protection parts, 12, 31, 43 and 52 are detection parts, 13 and 53 are display parts, 44b is a contact part (internal contact), and 55 is a lamp display. BD1, BD2, BD21 and BD22 are body diodes, F1 and 44 are fuses, LD1 is a light emitting diode (light emitting element), M1 and M21 are transistors (first power MOSFET), and M2 and M22 are transistors. (Second power MOSFET) is shown.

Claims (11)

When a motor is driven by a voltage-type PWM inverter, a surge voltage suppressing device that suppresses a surge voltage generated at the motor end,
It is provided corresponding to each phase of the motor end, and when the voltage of each phase exceeds the predetermined clamp voltage, a current is passed from the motor end, so that the voltage of each phase is changed to the clamp voltage. The clamping part to restrict,
A protection part that is provided corresponding to the clamp part, and that performs a protection operation to immediately shut off the energization path in which the clamp part is interposed when the corresponding clamp part is short-circuited;
A detection unit provided corresponding to the protection unit and detecting the protection operation by the corresponding protection unit;
When the protection operation of the protection unit is detected by the detection unit, a display unit that displays that the clamp unit is in a failure state,
The clamp part is
Comprising first and second power MOSFETs having a body diode built in between the drain and source;
The gates and sources of the first and second power MOSFETs are short-circuited, and the first power MOSFET and the second power MOSFET are connected in series so that the rectification directions of the body diodes are opposite to each other. A surge voltage suppressor, characterized in that it is connected to the device. The display unit
Provided corresponding to the detection unit,
2. The surge voltage according to claim 1, wherein when the protection operation of the protection unit is detected by the corresponding detection unit, a display indicating that the clamp unit corresponding to the protection unit is in a failure state is performed. Suppression device.   The surge voltage suppressor according to claim 1 or 2, wherein the clamp part is connected between the phases of the motor end.   The surge voltage suppression device according to any one of claims 1 to 3, wherein the clamp part is connected between each phase of the motor end and ground. The display unit is composed of a light emitting element that emits light when a predetermined current flows.
5. The surge voltage suppression device according to claim 1, wherein the detection unit supplies a predetermined current from the motor end to the light emitting element when detecting the protection operation. 6. The light emitting element is a light emitting diode,
6. The surge voltage suppressor according to claim 5, wherein the detection unit intermittently supplies a forward current from the motor end to the light emitting diode when detecting the protection operation.   The surge voltage suppression device according to any one of claims 1 to 6, wherein the protection unit is a fast-acting fuse connected in series to the energization path. The fuse includes an internal contact that operates when blown,
The surge voltage suppression device according to claim 7, wherein the detection unit includes the internal contact and detects the protection operation according to an operation of the internal contact. The fuse includes a fusing display unit for performing a display indicating fusing at the time of fusing,
The surge voltage suppression device according to claim 7, wherein the detection unit and the display unit are configured by the fusing display unit.   The surge voltage suppression device according to any one of claims 1 to 8, wherein a part of the clamp unit, the protection unit, the detection unit, and the display unit is detachable. A voltage-type PWM inverter that drives the motor via a cable;
A motor control device comprising the surge voltage suppression device according to claim 1.

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