JPH03270067A - Semiconductor integrated device - Google Patents

Abstract

PURPOSE:To avoid electrostatic breakdown while considering various noise countermeasures by forming power supply pads exclusive for each of a plurality of internal circuits formed onto a chip and mounting resistance elements mutually connecting the power supply pads. CONSTITUTION:Both power supply pads 26, 27 and both grounding pads 28, 29 are connected by resistance elements 46, 47 respectively. Since a section between power terminals 21, 22 (between the power supply pads 26, 27) is connected by the resistance element 46, discharge currents mainly flow through the resistance element 46, thus reducing currents to an internal circuit bonded with the power supply pads 26, 27, then avoiding the electrostatic breakdown of the internal circuit. When a package 20 is incorporated into an equipment, supply currents can be fed at every internal circuit without being subjected to the effect of the resistance element 46 because the power terminals 21, 22 and an external power supply are connected by low impedance, and various noise countermeasures can be executed without trouble. Since the floating capacitance C46, C47 of the resistance elements 46, 47 works as bypass capacitors in addition to the execution of said countermeasures, various noises can further be suppressed.

Description

[Detailed Description of the Invention] [Summary] With regard to a semiconductor integrated device that employs a multi-power supply system, the purpose of this invention is to avoid electrostatic damage while taking measures against various noises, and to provide a dedicated circuit for each of a plurality of internal circuits formed on a chip. The present invention relates to a semiconductor integrated device having power supply pads, including a resistive element for connecting the power supply pads.[Field of Industrial Application] The present invention relates to a semiconductor integrated device, and particularly to a semiconductor integrated device employing a multi-power supply system.

In recent years, the operating speed of semiconductor integrated devices has tended to increase further, but this has made it more important than ever to take measures against various noises in input/output signals, such as simultaneous switching noise, ringing noise, and glitch noise. It has become.

For example, simultaneous switching noise (also called ground bounce) is the noise that occurs when the reference potential fluctuates (the power supply potential drops or the ground potential rises) when multiple output circuits operate simultaneously. If the threshold value of the stage is exceeded, it may cause malfunction.

Here, the amount of change in potential is determined by the inductance of the lead of the pan cage and the bonding wire, their resistance meter, and the speed of current change (di/dt). For this reason, the higher the operating speed of the semiconductor integrated device is, the larger the di/dt becomes, which increases the degree to which large switching noise that exceeds the darkness value of the next stage is generated, resulting in operational inconveniences.

[Conventional technology]

A multi-power supply system is known as one of such noise countermeasures. In this method, a dedicated power supply terminal/ground terminal is provided for each internal circuit formed on the chip, and by flowing power supply current/ground current through multiple channels for each internal circuit, bonding wires and leads can be connected. This is designed to minimize the amount of noise generated by inductance and resistance bones.

[Problems to be Solved by the Invention] However, in such conventional devices, the power terminals/ground terminals of each internal circuit are insulated from each other, so if the chip (or pancage) is touched with bare hands, There were problems such as electrostatic damage to internal circuits.

That is, in Fig. 7, for example, if the power supply terminal (or ground terminal) A of the pan cage is connected to the ground and the other power supply terminal (or ground terminal) B is touched with bare hands, the distance between both terminals A and B will be Since it is in an insulated state, the discharge current i flows from the terminal B through the internal circuits Ca and cb and from the terminal A to the ground, and as a result, the internal circuits Ca, Cb are destroyed by the discharge current i.

The present invention was made in view of these problems, and
The purpose is to avoid electrostatic damage while taking various noise countermeasures.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention. In this diagram,
1O is a chip, 11a to 11n are a plurality of internal circuits formed on the chip, and 12a to 12n are the plurality of internal circuits 11.
This is a dedicated power supply pad (ground punt) for each a-1 inch, and is constructed by connecting these dedicated power supply pads 123 to 12n with each other using resistive elements 13a to 13m.

Here, the meaning of the above-mentioned chip also includes a pancake.

When interpreted as a package, the above power supply pad should be read as a power supply terminal (ground terminal).

That is, the power supply terminals of each of the plurality of internal circuits 118 to lln are connected to each other by each of the resistive elements 13a to 13m.

[Effect]

In the present invention, static electricity flowing from one power supply pad to another power supply pad, for example, is mainly caused to flow through the resistance element that connects these power supply pads. Therefore, the amount of current flowing to the internal circuit is reduced, and as a result, electrostatic damage to the internal circuit is avoided.

In addition, when the chip is incorporated into equipment and used, the power supply pad and external power supply are connected with low impedance, so the power supply current for each of the multiple internal circuits is reduced between each power supply pad and the external power supply. The signal can be streamed without any problem, and there will be no problems in terms of noise countermeasures.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

2 to 6 are diagrams showing an embodiment of a semiconductor integrated device according to the present invention.

First, to explain the conceptual configuration of this embodiment, in FIG. 2, 20 is an IC (integrated circuit).
The package 20 is provided with two power terminals 21, 22 and two ground terminals 23, 24, and a chip 25 is mounted thereon. Although not shown, a plurality of internal circuits are formed on the chip 25, and power pads 26 and 27 and ground pads I and 28 and 29 are formed for each internal circuit. In addition, 3
0 to 33 are input/output signal terminals, 34 to 37 are input/output signal pads, and 38 to 45 are bonding wires.

Here, the power supply punts 2ε and 27 and the ground pads 28 and 29 are connected by resistive elements 46 and 47, respectively. FIG. 3 shows a preferred example of the resistive elements 46 and 47.

In this figure, P,,P! is power supply punt 26 and 2
7 (or ground pads 28 and 29), p,
, p are extended from aluminum wiring lines , Lt, and connected to a resistive element 46 (or 47) formed, for example, by polysilicon (Poly-Si) or impurity diffusion. The resistive elements 46 and 47 thus formed have a predetermined resistance value R, and have a floating capacitance of 1 between them and the substrate (the path shown in the figure).
gives rise to c. C4 in Figure 2? C4? is this stray capacitance C
represents.

In the above configuration, for example, if one power terminal 21 is connected to the ground and the other power terminal 22 is touched, static electricity accumulated in the human body will cause the other power terminal 22 to be touched.
2 (power supply pad 27) to one power supply terminal 21 (power supply bundt 26), but in this embodiment, a resistive element 46 connects these power supply terminals 21 and 22 (between power supply pads 26 and 27). Since the connection is made, the discharge current mainly flows through the resistor element 46, and as a result, the power supply pad 2
The current flowing to the internal circuit (not shown) connected to 6.27 can be reduced, and electrostatic damage to the internal circuit can be avoided.

In addition, when the pan cage 20 is assembled into a device, the electric terminal 21
22 and the external power supply are connected at low impedance, the power supply current can be supplied to each internal circuit without being affected by the resistive element 46, and various noise countermeasures such as simultaneous switching noise can be taken without any problems. can. In addition, the stray capacitances IC4b and C4'l of the resistive elements 46 and 47 act as bypass capacitors, which has the unique effect of further suppressing various noises.

Needless to say, the resistance value R of the resistance elements 46 and 47 needs to be set to an optimum value by taking various conditions into consideration. For example, (1) the power supply impedance is sufficiently higher than that when the package 20 is incorporated into a device; (2) the chip 2
Considering various conditions such as the impedance of the internal circuit formed on the resistor 5, it is preferable to set the number to Ω (for example, R=IKΩ) in this embodiment.

Of course, other values may be passed depending on the type of IC and its usage. It is desirable to set the optimum value based on the results of simulations, experiments, etc.

FIG. 4 is a detailed configuration diagram of this embodiment.9 In this figure, 50 is a chip, and on the chip 50 there is one internal logic circuit 51, eight input circuits 52 to 59 (see FIG. 5(a)). ), two output circuits 60 and 61 (see Fig. 5 (
b)), three input/output circuits 62 to 64 (see Fig. 5(c)
), one power supply pad 65, six ground pads 66 to 71, and five resistance elements 72 to 76 are formed. Note that 77 to 81 represent inverter gates.

FIG. 6 is a diagram showing the main part of FIG. 4, and includes input/output circuits 62 to 6.
4 is a configuration diagram including a power pad 65 and ground pads 66 to 69.

That is, in these figures, the input/output circuits 62 to 64 (and output circuits 60, 61) formed on the chip 50 are treated as a plurality of internal circuits, and a dedicated ground pad 66 to 68, 70, . 71, and one grounded bunt Gcollo is used as a common putt Gcomo, and this common bunt Gcollo and other grounded bunts (
66, 67, 68, 70 and 71> are connected by resistance elements 72 to 76, respectively.

In this way, the number of resistive elements and the number of wires can be reduced, which is advantageous when the number of electric B terminals is large.

Of course, if there is enough space to install the resistors and wiring, you can connect the resistor elements in a matrix using all the target power supply pads as intersection points, but this method is preferable from the standpoint of avoiding electrostatic damage. It is desirable to adopt In addition, 4th.
For convenience of explanation, FIG. 6 shows only an example of application to a ground pad/node, but it goes without saying that when a plurality of power pads are provided, the power pads/nodes are also connected to each other with a resistive element.

[Effects of the Invention] According to the present invention, since a plurality of power supply pads are connected to each other by a resistive element, static electricity can be caused to flow through the resistive element. Therefore, electrostatic damage to internal circuits can be avoided while taking measures against various noises.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIGS. 2 to 6 are diagrams showing an embodiment of a semiconductor integrated device according to the present invention, FIG. 2 is a conceptual diagram thereof, and FIG. 3 is a resistor element thereof. Figure 4 is a detailed diagram of the configuration, Figures 5 (a), (b), and (c) are configuration diagrams of the input circuit, output circuit, and input/output circuit, and Figure 6 is the detailed configuration diagram of Figure 4. It is a main part configuration diagram. FIG. 7 is a diagram illustrating electrostatic damage in a conventional example. 72-76... Resistance elements. 10... Chip, 11a~lln... Multiple internal circuits, 12a~
12n...Power pad, 132~13m...
...Resistance element, 25... Chip, 26.27...--Power supply pad, 28.29... Ground pad (power supply pad), 4
6.47... Resistance element, 50... Chip, 60-61... Output circuit (multiple internal circuits),
62 to 64... Input/output circuit (multiple internal circuits)
66-71... Ground pad (power pad), 1
0 Principle configuration diagram of the present invention Fig. 1 Fig. 5 Fig. 5 A diagram explaining electrostatic damage of a conventional package.

Claims (1)

[Claims] 1. A semiconductor integrated device having dedicated power supply pads for each of a plurality of internal circuits formed on a chip, characterized in that the semiconductor integrated device is provided with a resistance element that connects the power supply pads to each other.