KR960002096B1 - Semiconductor device having electrostatic discharge protection - Google Patents

Abstract

The semiconductor memory device having a power pin, a sensor amp, and an input buffer includes: a pad which is connected to the power pin; a first diffused line which is connected to the pad; a second diffused line which is connected the sensor amp. and which is divided by field oxide layer and which is formed with the same impurity of the first diffused line a third diffused line which is connected to input buffer and which is formed with the same impurity of the first diffused line and a resistance means which is connected to the second and third diffused lines.

Description

Semiconductor device with electrostatic discharge protection

1A shows a schematic arrangement of power pads and power lines of a conventional semiconductor device using power lines separated for each use.

1B is a view showing a planar arrangement around a pad for power supply in a conventional semiconductor device using power lines separated for each use.

1C is a cross-sectional view taken along the line X-X 'of FIG.

Figure 1d is an electrical equivalent circuit according to the structure of (b).

2A, 2B and 3A, 3B show examples of planar arrangements around power pads in a conventional semiconductor device.

4 shows an embodiment according to the present invention.

FIG. 5 is an electrical equivalent circuit diagram showing electrical relationships between power lines having different uses according to FIG. 4.

6A is a graph showing a noise interference state according to the magnitude of a resistor (shown in FIGS. 4 and 5) during normal operation of a semiconductor device according to the present invention.

FIG. 6B is a graph showing the charge / discharge state at any power line according to the magnitude of the resistance (shown in FIGS. 4 and 5) during the electrostatic discharge (ESD) test of the semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an input protection function against electrostatic discharge (hereinafter referred to as "ESD").

In the CMOS type semiconductor device used as a memory element, it must be protected against a special external environment. The semiconductor memory device as a logic element is designed to operate in a voltage range of about several volts to several tens of volts internally. Thus, when the voltage applied to the pin is applied at a remarkably high voltage level beyond this voltage range, a short circuit between the conducting wires spaced at the interval of microns and a wiring layer and an oxide film formed in the thickness of the angstrom unit Of course, destruction of the unit elements on the input side may inevitably occur. Such phenomena are generated by static electricity flowing into the fins of the semiconductor device, and are called "electrostatic breakdown" or "electrostatic discharge (ESD)".

The evaluation of ESD is carried out in one step of the test process after the chip assembly process. One chip is provided with a plurality of pins for signal input together with power supply pins (hereinafter referred to as " power pins "), and pads are connected to the pins. Initially, all active circuits in the chip were designed to be powered through a single power pin and pad, but power noise was induced in other circuits not operating at the same time.

Thus, as shown in FIG. 1A, a configuration in which several pads 4, 6, and 8 are connected to each other from one pin is used. If the power pins XP connected to the three pads 4, 6, and 8 shown above receive the ground voltage Vss, the first pad 4 is used as the ground voltage line for the sense amplifier and the second pad 6 is the TTL input. The third pad 8 may be used as a ground voltage line for other peripheral circuits.

Although not shown in FIG. 1A, means for input protection, such as FIG. 1B, is designed around each pad. FIG. 1B shows the planar structure of the input protection device formed around an arbitrary pad, and FIG. 1C shows the cross-sectional structure along the cutting line X-X 'of FIG. 1B, and FIG. 1D shows the first b and It shows the electrical equivalent circuit according to c. Referring to FIGS. 1B and C, the left and right sides of the pad 10 are connected to n ⁺ diffusion lines (or n ⁺ diffusion regions) 12 and 14 formed in the lower substrate 30, respectively. n ⁺ diffusion lines (or n ⁺ diffusion regions) 12 and 14 are formed in n ⁻ diffusion lines (or n ⁺ diffusion regions) 11 and 13, respectively.

The power supply voltage Vcc line 23 spaced apart from the first pad protection line 16 consisting of the n ⁺ and n ⁻ diffusion lines 11 and 12 by the field oxide film 15 is connected to the first pad protection line ( Like 16, n ⁺ and n ⁻ diffusion lines (or n ⁺ and n ⁻ diffusion regions) 22 and 21 are formed. In the same manner, the ground voltage Vss line 33 spaced apart by the field oxide film 15 from the second pad protection line 17 consisting of the n ⁺ and n ⁻ diffusion lines 13 and 14 is the second voltage. Similar to the pad protection line 17, n ⁺ and n ⁻ diffusion lines (or n ⁺ and n ⁻ diffusion regions) 32 and 31 are configured. The configuration of the input protection device around the pad 10 as shown in Figs. 1A and 1C is npn bipolar transistors FT1 and FT2 which are field transistors connected to the left and right sides of the pad 10, as shown in Fig. 1D. Appears. The FT1 and FT2 in the form of field transistors have a common base on the semiconductor substrate 30, the emitters being the n ⁺ diffusion regions 21 and 31, respectively, and the collectors are the n ⁺ diffusions, respectively. Corresponds to the regions 11 and 13. In the prior art, the configuration of the input protection device formed around the pad has a form such as the first b, c, d.

2 and 3 show conventional examples of the input protection device around the pad employing the above-described configuration. Referring to FIGS. 2A and 2B, the part C indicated by the dotted line indicates that the power voltage line UVcc1 for the first use (for example, the sense amplifier) is UVcc2 and the second power supply line for the second use (for the input buffer, for example). The part connected to UVcc3 for the power supply voltage line for the third use (eg for other peripheral circuits), and the part S indicated by the dotted line indicates the ground voltage line UVss1 for the second use (for example for the sense amplifier). For example, the ground voltage line for the input buffer is connected to UVss2 and the ground voltage line for the third purpose (for other peripheral circuits). Note that the configuration of each power line is composed of n ⁺ and n ⁻ diffusion regions as shown in 1c. In the conventional input protection device configured as shown in FIG. 2A, as shown in the equivalent circuit diagram of FIG. 2B, the emitter terminal of the field transistor FT1 is connected to the collectors of the field transistors FT3 and FT4 through the power voltage line UVcc1 of the first use. Therefore, when a stress of thousands of volts is applied to the power supply voltage pin, a large amount of stress current stays in the field transistor, which may put a heavy burden on the input protection device composed of the field transistors. In addition, this causes a problem that the input protection characteristics are deteriorated. In severe cases, the input protection may be paralyzed by destroying the field transistors.

Meanwhile, referring to FIG. 3A and FIG. 3B, which is an equivalent circuit diagram of another conventional example, in FIG. 3A, the occupying area of the pad protecting line 16 or 17 shown in FIG. 1B is increased and the circumferential length thereof is increased. Increasingly, the respective application voltage lines UVcc1, UVcc2, UVcc3 and ground voltage lines UVss1, UVss2, and UVss3 are directly connected by the pad protection line 16 or 17 to the structure shown in FIG. 2C. That is, as shown in FIG. 3B, collectors of field transistors connected to each power line are directly connected to the pad 10. In such a configuration, since power lines having different uses are configured in the same way as having separate input protection devices, the input protection function against ESD applied from the outside is good, but the power lines around one pad may be As can be seen in Fig. 3a, all of the pad protection lines 16 or 17 must be connected, so that the area of the input protection device increases due to the expansion of the pad protection line.

Accordingly, an object of the present invention is to provide a semiconductor device having a good input protection against stress applied from the outside of the chip.

Another object of the present invention is to provide an input protection device having a good input protection function in a limited area.

In order to achieve the object of the present invention, the present invention is a semiconductor memory device having a power pin, a sense amplifier and an input buffer, a pad connected to the power pin, a first diffusion line connected to the pad, and the diffusion line And a second diffusion line separated by a field oxide film and composed of the same impurities as the impurity component of the first diffusion line, and electrically connected to the sense amplifier, and composed of the same impurities as the impurity component of the first diffusion line, And a third diffusion line electrically connected to the input buffer, and resistance means for connecting the second diffusion line and the third diffusion line.

Hereinafter, the configuration and operation of the preferred embodiment of the present invention will be described in detail with reference to FIGS. 4 to 6. Note that the same reference numerals as those in the drawings and the like referred to in the foregoing description in the following description refer to the same components.

Referring to FIG. 4 showing a planar configuration of an input protection device around an arbitrary pad according to an embodiment of the present invention, and FIG. 5 showing an equivalent circuit according to FIG. (16) and the second pad protection line 17, the pad protection lines 16 and 17 are composed of n ⁺ and n ⁻ diffusion regions as shown in FIG. The first pad protection line 16 is connected to the UVcc1 power supply voltage line for the first use through the collector-emitter path of the field transistor FTC1, and the second pad protection line 17 is the collector-emitter of the field transistor FTS1. It is connected to UVss1 by the ground voltage line of the first use through the path. Here, it should be noted that the power supply line UVcc1 of the first use and the ground voltage line UVss1 of the first use are respectively connected to the power supply line UVcc2, UVcc3 and the second and third use of the power supply voltage line of the second and third through the resistance. It is connected to the voltage lines UVss2 and UVss3.

The resistor, that is, a resistor CR12 connecting the UVcc1 power supply line UVcc1 for the first use and the UVcc2 power supply voltage line for the second use, and a CR13 connecting the UVcc1 power supply line UVcc1 for the third use and the UVcc3 connection for the third use And a resistor SR12 connecting the ground voltage line UVss1 for the first use and UVss2 for the ground voltage line for the second use, and a resistor SR13 connecting the UVss1 for the ground voltage line for the first use and the UVss3 for the third use; The low pass filter functions as a coupling capacitor between conductive lines used as power lines between power lines having different uses.

This resistance may be made of polycrystalline silicon or the like used as a conventional resistance material in a semiconductor device, or may be formed of an impurity diffusion region or a metal material. desirable.

The need for the ESD stress current applied to the pin of the chip to flow through the input protection path as soon as possible and to reduce the time the stress current flows, the resistance shown in Figure 3 in this regard, It can be seen that it is more advantageous than using the conventional field transistors. As is generally known, current flow in bipolar transistors is caused by stochastic combinations of electrons and holes, so that power lines are connected through npn bipolar field transistors during ESD tests as in the conventional case. It can be understood that the connection time through the resistor is shorter in the residence time of the stress current, that is, the discharge time of the stress current.

A value of a few kVs to several tens of kΩ, which is a suitable resistance value of the resistors CR12, CR13, SR12, and SR13, is small enough to be neglected for the stress voltage of thousands of volts having a low frequency component, but may be applied during operation of the semiconductor device. It has a relatively large effect on voltage of several volts with high frequency. This action of the resistor, since power lines of different uses are connected through the resistors as shown in FIG. .

FIG. 6a shows a graph in which power noise generated in a power line for a certain use is attenuated according to the value of the resistance in a power line of another use connected through a resistor. The horizontal axis represents time, and the vertical axis represents voltage level of power supply noise. This graph is the result of computer simulation. If this is applied to Fig. 4, the power noise generated by UVcc1 with the power voltage line of the first use is determined by UVcc2 with the power voltage line of the second use according to the resistance value of the resistor CR12. The degree of attenuation can be seen in the graph of FIG. 6A. As can be seen from the graph, as the value of the resistor CR12 increases, the attenuation width of power supply noise decreases, and the decrease rate decreases as the resistance value increases.

On the other hand, Figure 6b is a result obtained through the ESD simulation test performed after fabricating a chip having an input protection device as shown in Figure 4, showing the state of charge and discharge of the stress voltage according to the resistance value. The vertical axis represents the stress voltage level, and the horizontal axis represents the time related to the charge and discharge. Looking at the graph of Figure 6b, when the test stress voltage of 2000 volts is applied, it can be seen that as the resistance value increases, the level of the stress voltage is lowered but the charge and discharge time is further increased. Therefore, an appropriate value of the resistance used in the present invention may be preferably set from the test results of FIG.

As described above, the present invention has the advantage of suppressing the influence of the power noise induced from any power line on the neighboring power line by connecting the power lines of different uses through the resistor. In addition, the present invention provides an effective input protection function with a simple configuration without the need to increase the area for the configuration of the input protection device for ESD by simply connecting the power lines of different uses with only the resistor instead of the conventional field transistor. There is an advantage to realize. In addition, the present invention has the effect of improving the input protection characteristics for ESD by reducing the residence time of the stress current as compared to the conventional.

Claims (4)

A semiconductor memory device having a power pin, a sense amplifier, and an input buffer, comprising: a pad connected to the power pin, a first diffusion line connected to the pad, and the diffusion line separated from each other by a field oxide film; A second diffusion line made of the same impurities as the impurity component of the diffusion line and electrically connected to the sense amplifier, and a third diffusion line made of the same impurities as the impurity component of the first diffusion line and electrically connected to the input buffer. And a resistance means connecting the second diffusion line and the third diffusion line. The semiconductor device according to claim 1, wherein said resistance means is a polysilicon resistor, a diffusion resistor or a metal resistor. A semiconductor device having a plurality of signal input pins, the semiconductor device comprising: a pad connected to the pin, a first pad protection line and a second pad protection line respectively connected to one side of the pad and the other side of the pad, and through the field transistor; A first power voltage line and a first ground voltage line connected to each of the first and second pad protection lines, power voltage lines and ground voltage lines spaced apart from the pad, and the first power voltage line and the first power voltage line And a resistance means connecting each ground voltage line to the power supply voltage lines and the ground voltage lines. 4. The semiconductor device according to claim 3, wherein said resistance means is a polysilicon resistor, a diffusion resistor or a metal resistor.