JPS59215749A - Low noise package for semiconductor integrated circuit - Google Patents
Low noise package for semiconductor integrated circuitInfo
- Publication number
- JPS59215749A JPS59215749A JP9010183A JP9010183A JPS59215749A JP S59215749 A JPS59215749 A JP S59215749A JP 9010183 A JP9010183 A JP 9010183A JP 9010183 A JP9010183 A JP 9010183A JP S59215749 A JPS59215749 A JP S59215749A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- package
- integrated circuit
- substrate
- supply wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、高速・高集積度の半導体集積回路を搭載する
パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a package mounting a high-speed, highly integrated semiconductor integrated circuit.
（従来技術）
半導体技術の発達による１チツプ上の高集積化に伴い、
この種のパッケージの多端子化が進んでいる。従来のこ
の種のパッケージ構造はチップの電源端子・信号端子か
らパッケージの外部端子までの配線層が一層で構成され
ていたので多端子化によりパッケージ寸法が大きくなる
ため、チップからパッケージの端子までの配線距離が長
くなり、抵抗およびインダクタンスが増加する。このた
め多くの出力回路が同時に出力信号を切換る際に発生す
る高速な過渡電流などによシミ源雑音が発生するという
欠点があった。(Conventional technology) With the development of semiconductor technology and the increased integration on a single chip,
This type of package is becoming increasingly multi-terminal. In the conventional package structure of this type, the wiring layer from the chip's power and signal terminals to the package's external terminals was composed of a single layer. Wiring distances increase, resulting in increased resistance and inductance. For this reason, there is a drawback in that stain source noise is generated due to high-speed transient currents generated when many output circuits simultaneously switch output signals.
（発明の目的）
本発明は上記の欠点を改善するために提案されたもので
、その目的とする点はパッケージ内信号配線の寄生容量
を増加させずに、パッケージ内電詠配線の抵抗・インダ
クタンスを下げかつ容量を増加し、結果として電源配線
のインピーダンスを低下せしめ、多くの出力が同時に切
換る際に発生する電源雑音などを防止することにある。(Objective of the Invention) The present invention was proposed to improve the above-mentioned drawbacks, and its purpose is to reduce the resistance and inductance of the signal wiring inside the package without increasing the parasitic capacitance of the signal wiring inside the package. The purpose of this is to lower the power supply and increase the capacitance, thereby lowering the impedance of the power supply wiring and preventing power supply noise that occurs when many outputs are switched at the same time.
（発明の構成）
上記の目的を達成するため、本発明は半導体集積回路用
パッケージにおい・て、内側に前記集積回路を搭載する
部分を形成した少なくとも２層よシなる積層基板と、該
一方の基板上に前記集積回路の電源端子、信号端子を外
部へ導出させる第１の接続層と、他方の該基板上に上記
第１の接続層のうち電源端子を外部へ導出させる接続層
に等しい、あるいは同様な第２の接続層とを具備するこ
とを特徴とする半導体集積回路用低雑音パッケージを発
明の要旨とするものである。(Structure of the Invention) In order to achieve the above object, the present invention provides a package for a semiconductor integrated circuit, comprising: a laminated substrate having at least two layers, on the inside of which a portion for mounting the integrated circuit is formed; A first connection layer that leads out the power supply terminals and signal terminals of the integrated circuit to the outside on the substrate, and a connection layer that leads out the power supply terminals of the first connection layer on the other substrate, Alternatively, the gist of the invention is a low-noise package for a semiconductor integrated circuit characterized by comprising a second connection layer.
要約すれば本発明はパッケージ内の電源配線のみを２層
構造としたことを特徴とするものである。To summarize, the present invention is characterized in that only the power supply wiring within the package has a two-layer structure.
次に本発明の実施例を添附図面について説明する。なお
実施例は一つの例示であって、本発明の精神を逸脱しな
い範囲で、種々の変更ちるいは改良を行いうろことは云
うまでもない。Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.
第１図は本発明の低雑音パッケージの実施例を示すもの
であって、−において１は搭載する集積回路チップ、２
はチップ上の電源電極、３はリード線、４は放熱フィン
、５は基板、６は２層よシなる積層基板、７は一方の積
層基板上に形成され、集積回路の信号端子、電源端子を
外部へ導出させる第１接続層となるメタライズパターン
、８は他方の積層基板上に形成され、第１接続層のうち
電源端子を外部へ導出する接続層に等しい、あるいは同
様な第２接続層となるメタライズパターンである。また
９は第１．第２接続層を短絡するために設けた第１のス
ルーホール、１０は外部リードピン、１１は第１接続層
とリードピンを導通ずるための第２のスルーホールであ
る。FIG. 1 shows an embodiment of a low-noise package according to the present invention, in which 1 indicates an integrated circuit chip to be mounted, 2
are power supply electrodes on the chip, 3 are lead wires, 4 are heat dissipation fins, 5 is a substrate, 6 is a laminated board with two layers, 7 is formed on one of the laminated boards, and is a signal terminal and a power supply terminal of the integrated circuit. A metallized pattern 8 is formed on the other multilayer substrate and is equal to or similar to the connection layer that leads the power terminal to the outside of the first connection layer. This is the metallization pattern. Also, 9 is the first. A first through hole provided for short-circuiting the second connection layer, 10 an external lead pin, and 11 a second through hole for establishing electrical continuity between the first connection layer and the lead pin.
即ち、本発明のパッケージはパッケージ内電源配線とし
て平行な２層７，８を共通化して用いるために、従来の
パッケージ構造に比べて電源配線の抵抗およびインダク
タンスが大幅に小さくなシ、一方容量は増加する。この
ような構造になっているから、電源配線のインピーダン
スが極めて小さくなシ、その効果としては論理集積回路
の複数個の出力回路の同時切換動作などによる過渡的な
電流の急変と電源配線のインダクタンス成分との相互作
用によシ発生する電源雑音を、小さくできるという利点
を有する。That is, since the package of the present invention commonly uses two parallel layers 7 and 8 as power supply wiring within the package, the resistance and inductance of the power supply wiring are significantly smaller than those of the conventional package structure, while the capacitance is To increase. Because of this structure, the impedance of the power supply wiring is extremely low, and its effects include sudden changes in current caused by simultaneous switching of multiple output circuits of a logic integrated circuit, and inductance of the power supply wiring. This has the advantage that power supply noise generated due to interaction with components can be reduced.
さらに、具体的に本発明のパッケージ構造を用いた場合
のインダクタンス、容量値の変化を従来の場合と比較し
て説明する。第１図においてリード線部分については従
来構造と同じインダクタンス、容量管もつが、メタライ
ズパターンの部分では第１図のＡ、Ａで示した部分の断
面図である第２図から判るように電源配線のみ平行構造
をとる。第２図において第１図と同一部分には同一符号
を付しであるが、１２．１３は信号配線用メタライズパ
ターンである。Furthermore, changes in inductance and capacitance when the package structure of the present invention is specifically used will be explained in comparison with the conventional case. In Figure 1, the lead wire part has the same inductance and capacitance tube as the conventional structure, but the metallized pattern part has the power supply wiring as seen in Figure 2, which is a cross-sectional view of the part indicated by A and A in Figure 1. has a parallel structure. In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and 12 and 13 are metallized patterns for signal wiring.
このように構成されているので電源配線抵抗は従来よシ
約５０優減少し、電源配線と基板間の容量は平行配線８
のない従来構造に比べて約２．６倍に増加し、インダク
タンスについては約２１５に減少することが引算されて
いる。一方信号配線についてはスピードを低下させる寄
生容量の増加はほとんどない。以上説明したように、本
発明の構成では、電源配線についてのみその容量が増加
し、抵抗、インダクタンスが減少するので、電源配線の
インピーダンスは大幅に減少し、電源雑音を大幅におさ
える事ができる。With this configuration, the power supply wiring resistance is reduced by about 50% compared to the conventional one, and the capacitance between the power supply wiring and the board is reduced by 80% in parallel wiring.
The increase in inductance is about 2.6 times that of the conventional structure without a 215 inductance, and the inductance is reduced to about 215. On the other hand, for signal wiring, there is almost no increase in parasitic capacitance that reduces speed. As explained above, in the configuration of the present invention, only the capacitance of the power supply wiring increases and the resistance and inductance decrease, so the impedance of the power supply wiring is significantly reduced, and power supply noise can be significantly suppressed.
また、従来の集積回路のパッケージ実装においては、こ
の電源雑音を低減するために電流変化の大きな電源端子
は数端子を共通化して用いているが、本発明の構成によ
れば平行２層接続による低インピーダンス化が図れるた
め、高集債用多端子パッケージの共通化する電源ピン数
をへらしピンの使用効率を高めることができる。In addition, in conventional integrated circuit package mounting, several power supply terminals with large current changes are used in common in order to reduce power supply noise, but according to the configuration of the present invention, parallel two-layer connection is used. Since the impedance can be lowered, the number of common power supply pins in a high-density multi-terminal package can be reduced and pin usage efficiency can be increased.
（発明の効果）
以上説明したように、本発明のノくツケージ栴造は電源
線インピーダンスの低減が可能であるから大規模高速論
理集積回路を搭載するノくソケージに用いる限によシ、
電源誘導雑音などによる誤動作をなくシ、捷たパッケー
ジのピン使用効率を大幅に上げる事ができるという利点
がある。(Effects of the Invention) As explained above, the power supply line impedance of the present invention can be reduced, so it is suitable for use in a power supply cage equipped with large-scale high-speed logic integrated circuits.
It has the advantage of eliminating malfunctions caused by power supply induced noise and greatly increasing the pin usage efficiency of the shunted package.
第１図は本発明の一具体例に係るパッケージの配線に沿
った断面図、第２図は第１図のＡ、Ａ’線に沿う断面図
である。
１・・・集積回路チップ、２・・・チップ上の電源電極
、３・・・リード線、４・・・放熱フィン、５・・・基
板、６・・・籾層基板、７・・・第１接続層であるメタ
ライズツク、ターン、８・・・第２接続層であるメタラ
イズノくターン、９・・短絡用スルーホール、１０・・
・外部リードビン、１１・−・ピン導出用スルーホール
、１２．１３・・・信号配線用メタライズパターン
特許出願人
第１図
第２図
７FIG. 1 is a sectional view taken along the wiring of a package according to a specific example of the present invention, and FIG. 2 is a sectional view taken along lines A and A' in FIG. DESCRIPTION OF SYMBOLS 1... Integrated circuit chip, 2... Power supply electrode on chip, 3... Lead wire, 4... Heat radiation fin, 5... Substrate, 6... Rice layer substrate, 7... 1st connection layer metallized turn, 8... 2nd connection layer metallized turn, 9. Through hole for short circuit, 10...
・External lead bin, 11...Through hole for pin lead-out, 12.13...Metallized pattern for signal wiring Patent applicant Fig. 1 Fig. 2 Fig. 7
Claims (1)
回路を搭載する部分を形成した少なくとも２層よシなる
積層基板と、該一方の基板上に前記集積回路の電源端子
、信号端子を外部へ導出させる第１の接続層と、他方の
該基板上に上記第１の接続層のうち電源端子を外部へ導
出させる接続層に等しい、あるいは同様な第２の接続層
とを具備することを特徴とする半導体集積回路用低雑音
パッケージ。A package for a semiconductor integrated circuit, comprising: a laminated substrate having at least two layers on which a portion for mounting the integrated circuit is formed; A semiconductor characterized in that it comprises one connection layer and a second connection layer on the other substrate that is equal to or similar to the connection layer that leads the power supply terminal to the outside of the first connection layer. Low noise package for integrated circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9010183A JPS59215749A (en) | 1983-05-24 | 1983-05-24 | Low noise package for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9010183A JPS59215749A (en) | 1983-05-24 | 1983-05-24 | Low noise package for semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59215749A true JPS59215749A (en) | 1984-12-05 |
Family
ID=13989124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9010183A Pending JPS59215749A (en) | 1983-05-24 | 1983-05-24 | Low noise package for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59215749A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5339269A (en) * | 1991-07-30 | 1994-08-16 | Sony Corporation | Semiconductor memory module |
| US5885853A (en) * | 1990-06-22 | 1999-03-23 | Digital Equipment Corporation | Hollow chip package and method of manufacture |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5213772A (en) * | 1975-07-22 | 1977-02-02 | Kyocera Corp | Ic package |
-
1983
- 1983-05-24 JP JP9010183A patent/JPS59215749A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5213772A (en) * | 1975-07-22 | 1977-02-02 | Kyocera Corp | Ic package |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5885853A (en) * | 1990-06-22 | 1999-03-23 | Digital Equipment Corporation | Hollow chip package and method of manufacture |
| US5339269A (en) * | 1991-07-30 | 1994-08-16 | Sony Corporation | Semiconductor memory module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5903050A (en) | Semiconductor package having capacitive extension spokes and method for making the same | |
| US5283717A (en) | Circuit assembly having interposer lead frame | |
| US6163071A (en) | BGA type semiconductor device and electronic equipment using the same | |
| KR0134648B1 (en) | Multi-chip package | |
| US5834832A (en) | Packing structure of semiconductor packages | |
| US4530002A (en) | Connection lead arrangement for a semiconductor device | |
| JP3051011B2 (en) | Power module | |
| US20040164408A1 (en) | Noise eliminating system on chip and method of making same | |
| JP2546195B2 (en) | Resin-sealed semiconductor device | |
| US8362614B2 (en) | Fine pitch grid array type semiconductor device | |
| JPH0870090A (en) | Semiconductor integrated circuit | |
| JPH06163794A (en) | Multilayer lead frame of metal core type | |
| US7164194B2 (en) | BGA type semiconductor device and electronic equipment using the same | |
| JPS5854661A (en) | Multilayer ceramic semiconductor package | |
| JP2904123B2 (en) | Method for producing multilayer film carrier | |
| JPS59215749A (en) | Low noise package for semiconductor integrated circuit | |
| JPS6256664B2 (en) | ||
| JPH08274127A (en) | Semiconductor device | |
| WO1999013509A1 (en) | Semiconductor device | |
| US7187065B2 (en) | Semiconductor device and semiconductor device unit | |
| JP3290754B2 (en) | Multilayer substrate for semiconductor mounting | |
| JP2001077230A (en) | Lead frame and semiconductor device mounting body using the same | |
| JPH07130900A (en) | Semiconductor device | |
| JPH03106047A (en) | Semiconductor device | |
| JP3094953B2 (en) | Semiconductor device |